JP3450612B2 - Phase synchronous clock signal generator and phase synchronous clock signal generation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked clock signal generator and a phase-locked clock signal generation method for generating a clock signal synchronized with a sync trigger signal.

[0002]

2. Description of the Related Art In a laser beam printer (LBP), a photosensitive member is irradiated with a laser beam while scanning the photosensitive member at a constant speed, and only the irradiated portion is printed to attach toner. At this time, in order to synchronize the laser irradiation, a beam detect (BD) mirror is arranged at a mechanically constant position with respect to the photosensitive drum, and a laser beam is irradiated to this to photoelectrically convert the reflected light to generate an electric pulse signal. To a horizontal synchronization (NHD) signal.

In such an LBP system, conventionally, a synchronizing signal generator (first conventional example) as shown in FIG. 11 (a) is used.

A crystal oscillator 101 in the figure outputs a clock signal CK0 having a frequency N times the frequency (fo) of a required synchronous clock signal. This clock signal C
K0 is input to the N counter 102, and when the NHD signal = "H" is input to its clear terminal, the output terminal outputs the synchronous clock signal SCK having the frequency fo. When the NHD signal = "L" is input to the clear terminal, the N counter 102 is cleared and the output terminal becomes "L".

That is, since the N counter 102 starts counting at the rising edge of the NHD signal, it is possible to generate the synchronous clock signal SCK synchronized with this edge. FIG. 11B is a timing chart showing the operation of the first conventional example. Synchronous clock SCK
The synchronization jitter amount Ti is equal to one cycle (1 / Nfo) of the clock signal CK0.

FIG. 12 is a block diagram showing a configuration example of another conventional synchronization signal generator (second conventional example).

The output CK0 of the crystal oscillator 201 in the figure is
It is equal to the required frequency fo of the synchronization clock SCK and is input to the triangular wave generator 202. The triangular wave generator 202 has a C
The triangular wave signal TRI synchronized with the K0 signal and the clock signal Q having the rising slope period = “L” and the falling slope period “H” of the triangular wave signal TRI are output.

The output side of the triangular wave generator 202 is DC
It is connected to the positive input terminals of the generator 203 and the comparator 204. The DC generation unit 203 detects the upper 10 points of the triangular wave.
% Level DC1, 90% level DC5, DC1
DC5, DC3, DC4 of 30%, 50% and 70% levels are generated in four equal parts.

DC1 to DC5 are comparators 204, respectively.
Connected to the negative input terminal of and the comparison results P1 to P5 with the TRI input to the positive input terminal are generated. From the relationship between DC1 to DC5 and TRI, the comparison results P1 to P5 have a cycle of 1 / fo and a duty of 10% and 3 respectively.
The pulse signals are 0%, 50%, 70% and 90%.

Comparison results PI to P5 and clock signal Q
Is connected to the phase detection and SP / RP control unit 205. Phase detection and SP, RP control unit 20
5 is another input signal, a synchronization trigger signal NHD
It detects and stores where in the zone (Z0 to Z9) each rising edge of P1 to P5 produces, and outputs a set pulse SP and a reset pulse RP corresponding thereto. The output of the RS-flip-flop (RS-FF) 206 to which SP and RP are input becomes a synchronous clock signal synchronized with the synchronous trigger signal NHD.

FIG. 13 is a timing chart for explaining the operation of the second conventional example. In the detection and storage of the NHD phase, the latch result obtained by latching the comparison results P1 to P5 and the clock signal Q at the rising edge of the synchronization trigger signal NHD is used as phase data, and the data is stored until the next input edge of the synchronization trigger signal NHD. .

FIG. 14 shows a combination of SP and RP when an NHD edge is input to each zone of Z0 to Z9. The synchronous clock signal SCK becomes a clock signal synchronized with an MHD edge having a frequency fo and a duty of 50% by SP and RP. The synchronization jitter amount Tj is the interval between the zones Z0 to Z9.

FIG. 15 is a block diagram showing an example of the configuration of another conventional synchronizing signal generator (third conventional example).

The output CK0 of the crystal oscillator 301 is connected to a delay circuit group 302 which is equal to the required synchronous clock frequency fo and has N delays of To / N and which are connected in series. Outputs DCK0 to DCK (N of delay circuit group 302
-1) is input to the latch unit 303 for the purpose of phase detection, and is latched at the edge of the synchronization trigger signal NHD.

The latch outputs Q0 to Q (N-1) and the outputs DCK0 to DCK (N-1) of the delay circuit group 302 are selected by the selector 30.
4 and outputs the synchronous clock signal SCK synchronized with the NHD edge according to the latch data Q0 to Q (N-1).

FIG. 16 is a timing chart showing the operation of the third conventional example.

The synchronization jitter amount Tj with respect to the NHD edge of the synchronization clock signal SCK is the delay amount of one delay circuit. Although it is easy to use a CMOS gate input / output delay as the delay circuit, in order to cover the frequency of the synchronous clock signal in a wide range, it is better to configure the variable delay circuit by a bipolar process as shown in FIG. .

FIG. 18 is a timing chart showing the operation of the variable delay circuit shown in FIG. The constant current source current value I1 given by the bias VB is kept constant, and the bias Vd
Constant current source current value (delay amount control current value) Io given by
Is larger, the delay amount is smaller, and when Io is smaller, the delay amount is larger. Td (delay amount) is about (2V
Co / Io) (where V = R1 · I
1).

[0019]

However, in the LBP which requires colorization and further high speed and high definition, the synchronization clock frequency is increased and the desired synchronization jitter amount Tj is also reduced. However, the first, second and third conventional examples have the following problems.

In the first conventional example, since the clock signal CK0 having a frequency N times the required clock frequency fo is required, for example, fo = 50 Mhz and the synchronization jitter amount Tj = T.
To realize o / 32, it is necessary to generate a clock signal of 1.6 Ghz. This is a crystal unit and CMO
There is a problem that it cannot be realized with an inexpensive combination of S and the like, and the cost also increases in terms of noise countermeasures when handling such high frequencies.

In the second conventional example described above, the crystal oscillator may have a required synchronous clock frequency, but similarly fo = 50 Mh.
In order to realize z and the amount of synchronization jitter Tj = To / 32, each zone width in FIG. 16 must be set to 0.625 nsec, and the triangular wave signal TRI and the highest DC level D
It is difficult to output and transmit a thin pulse such as 0.625 nsec as the comparison result of C1. When an inexpensive and relatively high-speed bipolar process is used, a pulse width handled inside the IC is about 2 nsec at most.

In the third conventional example described above, the crystal oscillator may have a required synchronous clock frequency, but similarly fo = 50 Mh.
In order to realize z and the synchronization jitter amount Tj = To / 32, the delay amount of one variable delay circuit must be set to 0.625 nsec as in the second conventional example. Even in the calculation, the capacitance Co in FIG.
= 0.5v, the delay amount control current Io is 4.8mA.
Since the input / output delay of the circuit shown in FIG. 19 has a delay of about 0.5 to 1 nsec in practice, the minimum delay amount of about 4 nsec is appropriate for the variable delay circuit output, and It is almost impossible to get .625nsec.

In view of the above problems of the prior art, it is an object of the present invention to provide a synchronous clock signal generator and a synchronous clock signal generating method which are high speed and high in synchronization accuracy and have a relatively wide frequency range by an inexpensive bipolar process. To do.

[0024]

In order to achieve the above object, a phase locked clock signal generator of the first invention is
Based on the input clock signal, the synchronization jitter amount is To
In a phase synchronous clock signal generator for generating a synchronous clock signal synchronized with a synchronous trigger signal at / N (To is a cycle, N is an integer), a duty reproducing section for reproducing the duty of the inputted clock signal to 50%. , The output of the duty reproducing section is input, and the delay amount is To · M / N
A variable delay means group in which a plurality of variable delay means (M is an integer) are connected in series, a latch section for latching the output of each variable delay means of the variable delay means group at the edge of the synchronization trigger signal, and the latch section. A selector for selectively outputting the first and second signals from the outputs of the variable delay means group according to the output of the selector, first delay means for delaying the first output of the selector, and the synchronization. Second delay means for delaying the trigger signal, latch means for latching the output of the first delay means at the output edge of the second delay means, output of the first delay means and the selection section Switching means for switching the second output according to the output of the latch means and outputting as the synchronous clock signal.

In the phase-locked clock signal generator of the second invention, in the first invention, the duty recovery section includes a first variable delay circuit for delaying the input clock signal by a predetermined delay amount. , Taking an exclusive OR of the clock signal and the output of the first variable delay circuit,
A first exclusive OR circuit for outputting the result to the variable delay means group; and a first charge pump circuit for receiving the output of the first exclusive OR circuit as input,
The delay amount of the first variable delay circuit is controlled based on the output of the charge pump circuit.

According to a third aspect of the present invention, in the phase-locked clock signal generator according to the second aspect of the present invention, the first flip-flop which takes in the output of the first variable delay circuit in synchronization with the falling edge of the clock signal is provided. And this first
A first logical sum circuit for taking the logical sum of the inverted output of the flip-flop and the output of the first exclusive logical sum circuit, and the output of the first logical sum circuit is It is used as an input to the first charge pump circuit.

In the phase-locked clock signal generator of the fourth invention, in the first to third inventions, a delay amount control means for controlling the delay amount of each variable delay means in the variable delay means group is provided. It is provided.

According to a fifth aspect of the present invention, in the phase locked clock signal generator according to the fourth aspect of the invention, the delay amount control means includes a signal output from a predetermined stage in the variable delay means group and the duty recovery section. A second exclusive-OR circuit that takes an exclusive-OR with the output of the second charge-pump circuit and a second charge pump circuit that receives the output of the second exclusive-OR circuit as an input. The delay amount of each variable delay means in the variable delay means group is controlled based on the output of the pump circuit.

In the phase locked clock signal generator of the sixth invention, in the fifth invention, the output of the first stage in the variable delay means group is taken in in synchronization with the falling edge of the output of the duty recovery section. The delay amount control means is provided with a second flip-flop, and a second logical sum circuit for taking a logical sum of the output of the second exclusive logical sum circuit and the inverted output of the second flip-flop. The output of the second OR circuit is used as the input of the second charge pump circuit.

According to a seventh aspect of the present invention, in the phase-locked clock signal generator according to the sixth aspect, the preceding stage of the predetermined stage in the variable delay means group is synchronized with the falling edge of the output of the duty reproducing section. The delay amount control means is provided with a third flip-flop for taking in the output of the second flip-flop, and a logical product circuit for taking the logical product of the output of the second logical sum circuit and the inverted output of the third flip-flop. The output of the AND circuit is used as the input of the second charge pump circuit.

According to the eighth aspect of the present invention, the phase-locked clock signal generating method inputs a clock signal, and based on this clock signal, the synchronization jitter amount is To / N (To is a cycle, N is an integer) and becomes a synchronization trigger signal. In a phase-locked clock signal generation method for generating a synchronized synchronous clock signal, a variable delay means group in which a plurality of variable delay means having a delay amount To · M / N (M is an integer) are connected in series, and the variable delay means group. A latch unit that latches the output of each variable delay unit at the edge of the synchronous trigger signal, and selectively outputs the first and second signals from the outputs of the variable delay unit group according to the output of the latch unit. A selector, first delay means for delaying the first output of the selector, second delay means for delaying the synchronization trigger signal, and output of the first delay means for the second delay means Prepared and latch means for latching the output edge, 50 the duty of the input clock signal
%, The reproduction processing result of the duty reproduction processing is input to the variable delay means group, and the output of the first delay means and the second output of the selection section are input to the latch means. The output is switched according to the output and output as the synchronous clock signal.

A ninth aspect of the present invention is the phase-locked clock signal generation method according to the eighth aspect, wherein the duty recovery processing delays the input clock signal by a predetermined delay amount, and the first variable delay circuit. Clock signal and the first
A first exclusive-OR circuit that takes an exclusive-OR with the output of the variable delay circuit and a first charge pump circuit that receives the output of the first exclusive-OR circuit as an input, The first exclusive OR circuit calculates the exclusive OR of the output of the first variable delay circuit and the clock signal and outputs the result as a reproduction processing result to the variable delay means group. , Based on the output of the first charge pump circuit, which receives the result of this regeneration processing,
The delay amount of the variable delay circuit is controlled.

In the phase-locked clock signal generating method of the tenth invention, in the ninth invention, the duty recovery processing synchronizes the output of the first variable delay circuit in synchronization with the falling edge of the clock signal. A first flip-flop to be taken in and a first logical sum circuit for taking the logical sum of the inverted output of the first flip-flop and the exclusive OR result are prepared, and the output of the first logical sum circuit is provided. Is input to the first charge pump circuit, and the delay amount of the first variable delay circuit is controlled based on the output of the first charge pump circuit.

In the phase-locked clock signal generating method of the eleventh invention, in the eighth to tenth inventions, a delay amount control process for controlling the delay amount of each variable delay means in the variable delay means group is performed. It was done like this.

According to a twelfth aspect of the present invention, in the phase-locked clock signal generating method according to the eleventh aspect, the delay amount control processing includes a signal output from a predetermined stage in the variable delay means group and the duty recovery section. A second exclusive-OR circuit that takes an exclusive-OR with the output and a second charge pump circuit that receives the output of the second exclusive-OR circuit are provided, and the second charge is provided. The delay amount of each variable delay means in the variable delay means group is controlled based on the output of the pump circuit.

In the phase locked clock signal generating method of the thirteenth invention, in the twelfth invention, the delay amount control processing is performed in the variable delay means group in synchronization with the falling edge of the output of the duty reproducing section. A second flip-flop for taking in the output of the first stage of the above, and a second OR circuit for taking the logical sum of the output of the second exclusive OR circuit and the inverted output of the second flip-flop are prepared. , The output of the second OR circuit is input to the second charge pump circuit, and the delay amount of each variable delay means in the variable delay means group is controlled based on the output of the second charge pump circuit. It is something that is done.

According to a fourteenth aspect of the present invention, in the phase locked clock signal generating method according to the thirteenth aspect of the present invention, the delay amount control processing is performed in the variable delay means group in synchronization with a falling edge of the output of the duty reproducing section. A third flip-flop for fetching the output of the preceding stage of the predetermined stage;
A logical product circuit that takes the logical product of the output of the logical sum circuit of FIG. 3 and the inverted output of the third flip-flop, and the output of the logical product circuit is input to the second charge pump circuit. The delay amount of each variable delay means in the variable delay means group is controlled based on the output of the second charge pump circuit.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of a synchronous clock signal generator according to an embodiment of the present invention, and FIGS. 2 and 3 are synchronous clock signal generators according to an embodiment of the present invention. It is a specific configuration diagram of.

This synchronous clock signal generator receives a clock duty reproducing unit 11 for reproducing the duty of an input clock signal CK0 to 50%, and an output of the clock duty reproducing unit 11 as an input, and a delay amount is To · M / N
A variable delay means group 12 in which a plurality of variable delay means (M is an integer) are connected in series; and a latch section 13 for latching the output of each variable delay means of the variable delay means group 12 at the edge of the synchronization trigger signal NHD, A selection unit 14 that selectively outputs the first and second signals from the outputs of the variable delay unit group 12 according to the output of the latch unit 13 and a first unit that delays the first output of the selection unit 14 The delay means 15, the second delay means 16 for delaying the synchronization trigger signal NHD, the latch means 17 for latching the output of the first delay means 15 at the output edge of the second delay means 16, and the first delay means 16. Delay means 15
Of the synchronous clock signal SC and the second output of the selector 14 are switched according to the output of the latch means 17.
And a switching means 18 for outputting as K.

2 and 3, the synchronous clock signal generator (synchronous jitter amount To / 3 according to the present embodiment will be described.
A specific configuration of 2) will be described. 2 and 3 are as follows.
They are connected by connectors K1 to K19, respectively.

In the synchronous clock signal generator of this embodiment shown in FIGS. 2 and 3, the crystal oscillator 21 outputs the clock signal CK0 having the same frequency as the required synchronous clock signal frequency fo. The clock signal CK0 is input to the frequency divider 22 and has a frequency fo / 2 and a duty ratio of 50%.
It becomes K2.

The clock signal CK2 is supplied to the variable delay circuit 11
a and the input circuit of the EXOR gate 11b. The output of the variable delay circuit 11a is connected to the other input terminal of the EXOR gate 11b.
The output P0 of the gate 11b is connected to the input terminal of the variable delay circuit group 12 and the input terminal of the OR gate 11c.
The DFF 11 is connected to the other input terminal of the OR gate 11c.
The negative output of f is connected.

The output of the variable delay circuit 11a is connected to the data input terminal of the DFF 11f, and the clock input terminal (falling edge is effective), which is the negative input terminal, is the output of the divide-by-2 frequency divider 22, CK2. Are connected.
The negative output of the DFF 11f outputs "H" when the delay amount of the variable delay circuit 11a is the "H" period of CK2, that is, To or less, and outputs "L" when it exceeds To.

The output of the OR gate 11c is connected to the charge pump (CP) 11d, and the output of the CP 11d is connected to the low pass filter (LPF) 11e.
The output of 11e is the variable delay circuit 11a and the variable delay circuit 16
It is connected to the delay amount control terminals A and 31 (FIG. 3).

In the variable delay circuit group 12, seven variable delay circuits 12a to 12h having the same delay amount are connected in series, and respective variable delay circuit outputs are set to PI to P7. The DFF 23 is
The output P1 of the first-stage variable delay circuit 12a of the variable delay circuit group 12 is connected to the data input terminal, and the variable delay circuit group 12 is connected to the clock input terminal (falling edge is effective) which is a negative input terminal. Input signal P0 is connected.

The output of the DFF 23 is the variable delay circuit group 12
If the delay amount of the variable delay circuit 12a at the first stage is less than To / 2, "L" is output, and if it exceeds To / 2, "H".
Is output. To the input terminal of the EXOR gate 25, P0 and the negative output NP4 of the variable delay circuit 12d at the fourth stage of the variable delay circuit group 12 are connected. The output of the EXOR gate 25 is connected to the input terminal of the OR gate 26,
The negative output of the DFF 23 is connected to the other input terminal of the R gate 26.

The output of the OR gate 26 is the AND gate 27.
Is connected to the input terminal of. The negative output of the DFF 24 is connected to the other input terminal of the AND gate 26. The output of the third stage variable delay circuit 12c of the variable delay circuit group 12 is connected to the data input terminal of the DFF 24, and the clock input terminal that is the negative polarity input terminal (falling edge is effective) is variable. The input signal P0 of the delay circuit group 12 is connected.

The output of the AND gate 27 is commonly connected to the delay amount control terminals of all the variable delay circuits 12a to 12g of the variable delay circuit group 12 and the variable delay circuit 15 via the CP 28 and the LPF 29. The input / output P9 to P7 of the variable delay circuit group 12 are the DFFs 13a to 2 of the latch unit 13.
3h is connected to each data input terminal. A synchronization trigger signal NH is input to the clock input terminal of the latch unit 13.
D has been entered. Latch data Q0 to Q7 output from the latch unit 13 are connected to the selection unit 14. Selector 14
Further, P0 to P7 are also input to.

The selector 14 selects two clock signals PD and PX from P0 to P7 according to the states of Q0 to Q7. As shown in FIG. 3, its configuration is a switch (SW) 14 including an AND gate and a NAND gate.
a four-input OR gate WOR (4) 14q having the outputs of the switches 14a-14d as input
And the WOR whose inputs are the outputs of the switches 14d to 14h
(4) 14r, WOR (4) 14q and WOR (4) 1
An OR gate 14s that receives the output of 4r and a WOR (4) 14t that receives the outputs of the switches 14i to 14l
And the WOR whose inputs are the outputs of the switches 14m to 14p
(4) 14u, WOR (4) 14t and WOR (4) 1
An OR gate 14V which receives the output of 4u is provided.

Then, the switches (SW) 14a to 14p
Operates by selecting an AND gate when the input Q0 is "H" and a NAND gate when the input Q0 is "L".
The output PD from the gate 14s and the OR gate 14v
The output PX is output from each.

The output PD of the selector 14 is the variable delay circuit 15
Is connected to the input terminal of. The output of the variable delay circuit 15 is connected to the data input terminal of the DFF 17,
The clock input terminal 7 is connected to the synchronous trigger signal NHD1 after passing through the variable delay circuit 16A and the delay circuit 16B.

The delay amount of the variable delay circuit 16A is relatively designed to be To when the delay amount of the variable delay circuit 11a is To / 2. The delay circuit 16B has the same configuration as the circuit for generating the input / output delay of the selection unit 14 because the input / output delay of the selection unit 14 is the same. The DFF17 output is
It is connected to the control terminal of the changeover switch 18.

The output of the variable delay circuit 15 is connected to the first input terminal of the changeover switch 18, and the output PX of the selector 14 is connected to the second input terminal.
The delay amount of the variable delay circuit 15 is the delay amount of each of the variable delay circuits 12 a to 12 g of the variable delay circuit group 12 (To · 14 /
In the case of 32), it is relatively designed to be (To 7/32).

The control signal of the changeover switch 18 is "L".
When it is, the second input terminal side (PX) is selected, and when it is "H ', the first input terminal side (output of the variable delay circuit 15) is selected. The output of the changeover switch 18 is connected to the AND gate 32. The other input terminal of the AND gate 32 has the NHD 1 after passing through the variable delay circuit 31 of the NHD 1.
2 is connected. The delay amount of the variable delay circuit 31 is 0.75To when the delay amount of the variable delay circuit 11a is To / 2.
Relatively designed to be.

The variable delay circuit 11a is the same as that shown in FIG.
7, the configuration shown in FIG. The CP 11d has a structure as shown in FIG.

Next, the operation of the clock duty reproducing section 11 will be described.

The CP 11d operates as shown in the timing chart of FIG. That is, the input pulse I
According to the duty of N (clock signal CK2), when the "L" period of the input pulse IN increases, the output OUT of the CP 11d rises, and when the "L" period of the input pulse IN decreases, the output OUT of the CP 11d falls. , The output level changes.

The stable condition of this CP11d is that the duty of the input pulse signal IN is 50% and the capacitor C1 (FIG. 4).
This is when the ratio of the charging period and the discharging period of is equal. In the output P0 of the EXOR gate 11b, CK2 is doubled, and the duty becomes "L" period when the delay amount of the variable delay circuit 11a becomes large, and becomes small when the delay amount becomes small.

When the duty of the output of the EXOR gate 11b becomes "L"period>"H" period (delay amount> To / 2), the output level of CP11d rises, and its LPF11e.
Of the variable delay circuit 11a, which is the output of the variable delay circuit 11a, increases the Io (FIGS. 17 and 18) of the variable delay circuit 11a and reduces the delay amount. Conversely, the duty of the output of the EXOR gate 11b is "L" period <"H" period (delay amount <
To / 2), the output level of CP11d drops,
The control terminal voltage of the variable delay circuit 11a, which is the output of the LPF 11e, decreases, the Io of the variable delay circuit 11a increases, and the delay amount increases. Therefore, the output P0 of the EXOR gate 11b has a duty of 50% at the frequency fo.
Clock signal of the crystal oscillator 21, and the oscillation pulse C of the crystal oscillator 21.
This means that the duty of K0 is reproduced to 50%.

The DFF 11f and the OR gate 11c function as an abnormal operation prevention circuit when the delay amount of the variable delay circuit 11a as shown in FIG. 6 exceeds the "H" period of the rising edge. That is, when the delay control current is small, when the duty reproducing unit 11 operates from a value where the delay amount exceeds (t2-t1) as shown in FIG.
The mode in which the variable delay circuit 11a outputs a periodic pulse signal three times as large as the input, and the EXOR gate 11b outputs the signal P0 at which the "H" / "L" ratio which is the stable condition of CP11d is 1 Exists.

In order to cancel this abnormal operation, DFF1
1f is "L" (normal) when the rising edge of the output of the variable delay circuit 11a is before the input falling edge, and "H" when the rising edge of the output of the variable delay circuit 11a is after the input falling edge. When it is abnormal, the OR gate 11c forcibly inputs the “H” level to the CP 11d and determines that the delay amount is “large”, and the output of the CP 11d is increased to increase the delay amount control current. And reduce the delay amount.

Next, the delay amount control of the variable delay circuit group 12 will be described with reference to the timing chart of FIG. The positive and negative polarities of the input / output signals of the variable delay circuit group 12 are shown as P0 to P7, and the negative polarities are shown as NP0 to NP7.

In this embodiment, the delay amount of one variable delay circuit in the variable delay circuit group 12 is set to To · 7/16. Under this condition, the output of the EXOR gate 25 having the delayed NP4 as an input, which is obtained by integrating P0 and four variable delay circuits, has a duty of 50% at a cycle To / 2. This satisfies the stability condition of CP11d described above and can be stabilized. By this delay amount control, as shown in FIG. 7, the rising and falling edges of the input / output of the variable delay circuit group 13 are always present in the required synchronous clock period (To) at To / 16 intervals. It will be.

The DFF 23 and the OR gate 26 are for canceling the abnormal operation mode of the variable delay circuit 11a described in the duty reproducing section 11. DFF24 and A
The ND gate 27 is for avoiding another stable condition of the variable delay circuit group 12. As a condition for the phase of P0 and NP4 to become π / 4, there is a variable delay circuit delay amount To · 3/16 as shown in FIG. 9A.

The EQ in FIGS. 9 (a), 9 (b) and 9 (c) is
EXOR of P0 and NP4 regardless of the output of DFF24
Shows the output when is taken. However, the DFF 24 outputs "L" under this stable condition, and the AND gate 27 receives it and outputs "L" regardless of the output of the EXOR gate 25, whereby the CP 28 lowers the output potential and controls the delay amount. The current is reduced and the delay amount To / 3 in FIG.
The F24 outputs "H", and the EXOR gate 25 outputs the phase difference signal between P0 and NP4 (EQ in FIG. 9B).
In FIG. 9B, since the output of the EXOR gate 25 is in the “L” period> “H” period, the CP 28 lowers the output potential and reduces the delay amount control current to further reduce the delay amount. In the case of FIG. 9C, the delay amount becomes To · 7/16, which is stable here.

The latch section 13 includes the variable delay circuit 12 described above.
Input / output P0 to P7 of a to 12g are synchronized with trigger signal NHD
By latching with, the synchronous trigger signal input phase data (Q0 to Q7) is obtained. The selection unit 14 outputs PD and PX according to the synchronization trigger signal input phase data (Q0 to Q7) according to the logic table shown in FIG. PX is the zone (Z0 shown in FIG. 7 where the synchronous trigger signal NHD is input.
.About.Z15) is the output pulse of the variable delay circuit group 12 that forms the leading edge. The PD uses a variable delay circuit 15 to
It is an output pulse of the variable delay circuit group 12 having a rising edge in the center of the zone (Z0 to Z15) to which the synchronization trigger signal NHD is input after being delayed by 7/32.

The variable delay circuit 15 delays the PD output of the selection section 14 by To · 7/32. The delay amount control of the variable delay circuit 15 is performed by the control signal of the variable delay circuit group 12. Variable delay circuits 12a to 12 of the variable delay circuit group 12
g, the capacitor Co of the variable delay circuit 15 (see FIG.
7), or control current Io is doubled,
The delay amount of the variable delay circuit group 12 can be relatively halved. Delay amount of To 7/32 is 50M
The synchronous clock frequency of hz is 4.375 nsec, which can be sufficiently configured by an inexpensive bipolar process.

The output Pnd of the variable delay circuit 15 (n = 0,
1 ... 7) are variable delay circuits 16A and delay circuits 16
With the synchronous trigger signal NHD1 delayed by B (To
+ Α), the synchronization trigger signal input phase is selected in the DFF 17. It is determined whether the synchronization trigger signal input phase is before or after the rising edge of the delayed output Pnd of the variable delay circuit 15. The DFF 17 outputs "L" if the synchronization trigger signal input phase is before, and outputs "H" after. The delay amount α of the delay circuit is the delay amount until the output of the variable delay circuit group 12 is selected as the PD by the selection unit 14. The changeover switch 18 selects the output PX of the selection unit 14 when the output of the DFF 17 is “L” and the output Pnd of the variable delay circuit 15 when the output is “H”.

As a result, the output of the changeover switch 18 is synchronized with the synchronization trigger signal NHD by the phase difference between PX and Pnd, that is, the synchronization jitter amount of To / 32. Since it takes (1 + 1/32) · To at maximum from the input of the synchronization trigger signal to the determination of the synchronization clock phase, the NHD input to the DFF 17 should not generate an uncertain pulse.
The NHD3 signal obtained by further delaying the two signals by 0.75To is masked by the AND gate 32 and the synchronous clock signal S
Output as CK. The time from the input of the synchronous trigger signal NHD to the output of the synchronous clock signal SCK is 2To.
Is.

As described above, in this embodiment, the minimum delay amount of the variable delay circuit is set to the required synchronization jitter amount (for example, T / 3).
By setting it larger than 2) (for example, To 7/32), it is possible to generate a highly accurate synchronous clock signal at 50 Mhz or more even in an inexpensive bipolar process.

[0072]

As described in detail above, according to the phase-locked clock signal generator of the first invention, it is possible to generate a highly-accurate synchronized clock signal at, for example, 50 Mhz or more even in an inexpensive bipolar process. .

According to the phase-locked clock signal generator of the second aspect of the invention, in the first aspect of the invention, the duty recovery section can be simply and accurately constructed.

According to the phase-locked clock signal generator of the third aspect of the invention, in the second aspect of the invention, an abnormal operation in which the delay amount of the first variable delay circuit exceeds the "H" period in the rising edge is performed. Can be prevented.

According to the phase-locked clock signal generator of the fourth invention, the delay amount of each variable delay means in the variable delay means group can be controlled in the first to third inventions.

According to the phase-locked clock signal generator of the fifth aspect of the invention, the delay amount control means in the fourth aspect of the invention can be simply and accurately constructed.

According to the phase-locked clock signal generator of the sixth invention, in the fifth invention, it is possible to prevent an abnormal operation in which the delay amount of the variable delay means exceeds the "H" period for the rising edge. You can

According to the phase-locked clock signal generator of the seventh invention, in the sixth invention, the variable delay circuit group can be stably operated.

According to the phase-locked clock signal generating method of the eighth invention, it is possible to generate a highly accurate synchronous clock signal at, for example, 50 Mhz or more even in an inexpensive bipolar process.

According to the phase-locked clock signal generating method of the ninth invention, in the eighth invention, the duty recovery processing can be simply and accurately executed.

According to the phase-locked clock signal generating method of the tenth invention, in the ninth invention, an abnormal operation in which the delay amount of the first variable delay circuit exceeds the "H" period in the rising edge is performed. Can be prevented.

According to the phase locked clock signal generating method of the eleventh invention, in the eighth to tenth inventions, the delay amount of each variable delay means in the variable delay means group can be controlled.

According to the phase-locked clock signal generating method of the twelfth invention, in the eleventh invention, the delay amount control process can be executed easily and accurately.

According to the phase locked clock signal generating method of the thirteenth invention, in the twelfth invention, it is possible to prevent an abnormal operation in which the delay amount of the variable delay means exceeds the "H" period in the rising edge. You can

According to the phase-locked clock signal generation method of the fourteenth invention, in the thirteenth invention, the variable delay circuit group can be stably operated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a synchronous clock signal generator according to an embodiment of the present invention.

FIG. 2 is a specific configuration diagram of a synchronous clock signal generator according to an exemplary embodiment of the present invention.

FIG. 3 is a continuation of FIG. 2.

FIG. 4 is a diagram showing a configuration of a CP 11d in FIG.

FIG. 5 is a timing chart showing the operation of CP 11d.

FIG. 6 is a timing chart illustrating an abnormal operation mode of the variable delay circuit.

7 is a timing chart showing an operation of the synchronous clock signal generator shown in FIG.

8 is a timing chart showing an operation of the synchronous clock signal generator shown in FIG.

FIG. 9 is a timing chart for explaining how to avoid the abnormal stable mode of the variable delay circuit group.

FIG. 10 is a diagram showing a logical table of a selection unit.

FIG. 11 is a diagram showing a configuration and an operation of a first conventional example.

FIG. 12 is a diagram showing the configuration and operation of a second conventional example.

FIG. 13 is a diagram showing a configuration and an operation of a second conventional example.

FIG. 14 is a diagram showing a configuration and an operation of a second conventional example.

FIG. 15 is a diagram showing a configuration and an operation of a third conventional example.

FIG. 16 is a diagram showing the configuration and operation of a third conventional example.

FIG. 17 is a diagram showing a configuration and an operation of a variable delay circuit.

FIG. 18 is a diagram showing a configuration and an operation of a variable delay circuit.

FIG. 19 is a circuit diagram showing a simple bipolar circuit.

[Explanation of symbols]

11 Clock duty reproduction section 12 Variable delay means group 13 Latch part 14 Selector 15 First delay means 16 Second delay means 17 Latch means 18 Switching means NHD synchronization trigger signal CK0 clock signal SCK Synchronous clock signal

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03L 7/06 G06F 1/06 H03K 5/13

Claims (14)

(57) [Claims] 1. A phase synchronous clock signal generator for generating a synchronous clock signal synchronized with a synchronous trigger signal with a synchronous jitter amount To / N (To is a cycle, N is an integer) based on an input clock signal, A duty reproducing unit for reproducing the duty of the input clock signal to 50%, and an output of the duty reproducing unit as an input, and a delay amount of To.
A variable delay means group in which a plurality of M / N (M is an integer) variable delay means are connected in series; and a latch unit that latches the output of each variable delay means of the variable delay means group at the edge of the synchronization trigger signal, A selection unit that selectively outputs first and second signals from the outputs of the variable delay unit group according to the output of the latch unit; and a first delay unit that delays the first output of the selection unit. Second delay means for delaying the synchronization trigger signal, latch means for latching an output of the first delay means at an output edge of the second delay means, output of the first delay means and the A phase-locked clock signal generator, comprising: switching means for switching the second output of the selection section according to the output of the latch means and outputting the synchronized clock signal. 2. The duty recovery section includes a first variable delay circuit that delays the input clock signal by a predetermined delay amount, and an exclusive logic of the clock signal and an output of the first variable delay circuit. A first exclusive-OR circuit for taking the sum and outputting the result to the variable delay means group; and a first charge pump circuit for receiving the output of the first exclusive-OR circuit as an input 2. The phase-locked clock signal generator according to claim 1, wherein the delay amount of the first variable delay circuit is controlled based on the output of the first charge pump circuit. 3. A first variable delay circuit that captures an output of the first variable delay circuit in synchronization with a falling edge of the clock signal.
And a first logical sum circuit for taking the logical sum of the inverted output of the first flip flop and the output of the first exclusive logical sum circuit, in the duty recovery section. 3. The phase-locked clock signal generator according to claim 2, wherein the output of the OR circuit is used as the input of the first charge pump circuit. 4. The phase-locked clock signal generator according to claim 1, further comprising delay amount control means for controlling a delay amount of each variable delay means in the variable delay means group. . 5. The second delay amount control means obtains an exclusive OR of a signal output from a predetermined stage in the variable delay means group and an output of the duty reproducing section.
And a second charge pump circuit that receives the output of the second exclusive OR circuit as an input, and the variable delay means group is based on the output of the second charge pump circuit. 5. The phase-locked clock signal generator according to claim 4, wherein the delay amount of each variable delay means is controlled. 6. A second flip-flop that takes in the output of the first stage in the variable delay means group in synchronization with the falling edge of the output of the duty recovery section, and an output of the second exclusive OR circuit. The delay amount control means is provided with a second logical sum circuit for performing a logical sum with the inverted output of the second flip-flop, and the output of the second logical sum circuit is input to the second charge pump circuit. 6. The phase-locked clock signal generator according to claim 5, wherein. 7. A third flip-flop for fetching the output of the preceding stage of the predetermined delay stage in the variable delay means group in synchronization with the falling edge of the output of the duty reproducing unit, and the second OR circuit. An AND circuit that takes the logical product of the output and the inverted output of the third flip-flop is provided in the delay amount control means, and the output of the AND circuit is used as the input of the second charge pump circuit. The phase-locked clock signal generator according to claim 6, characterized in that 8. A clock signal is input, and a synchronization jitter amount is To / N (To is a cycle, N based on this clock signal).
Is a integer) and a phase synchronous clock signal generating method for generating a synchronous clock signal synchronized with a synchronous trigger signal. A variable delay means in which a plurality of variable delay means having a delay amount To · M / N (M is an integer) are connected in series. Group, a latch unit for latching the output of each variable delay unit of the variable delay unit group at the edge of the synchronization trigger signal, and a first and a second output from the outputs of the variable delay unit group according to the output of the latch unit. A selection unit that selectively outputs a second signal, a first delay unit that delays the first output of the selection unit, a second delay unit that delays the synchronization trigger signal, and the first delay unit. And a latch means for latching the output of the second delay means at the output edge of the second delay means, and a duty reproduction process for reproducing the duty of the input clock signal to 50% is performed. The reproduction processing result of the duty reproduction processing is input, the output of the first delay unit and the second output of the selection unit are switched according to the output of the latch unit, and output as the synchronous clock signal. Method for generating phase-locked clock signal. 9. The duty recovery process is an exclusive OR operation between a first variable delay circuit that delays an input clock signal by a predetermined delay amount, and the clock signal and an output of the first variable delay circuit. And a first charge pump circuit having the output of the first exclusive OR circuit as an input, and the first exclusive OR circuit The exclusive OR of the output of the first variable delay circuit and the clock signal is output and the result is output to the variable delay means group as the reproduction processing result, and the reproduction processing result is input. 9. The phase-locked clock signal generating method according to claim 8, wherein the delay amount of the first variable delay circuit is controlled based on the output of the charge pump circuit. 10. The duty recovery processing comprises: a first flip-flop that captures the output of the first variable delay circuit in synchronization with a falling edge of the clock signal; and an inverted output of the first flip-flop. A first logical sum circuit for obtaining a logical sum with the exclusive logical sum result, and the output of the first logical sum circuit is input to the first charge pump circuit; 10. The phase locked clock signal generating method according to claim 9, wherein the delay amount of the first variable delay circuit is controlled based on the output of the circuit. 11. The phase-locked clock signal generating method according to claim 8, wherein a delay amount control process for controlling a delay amount of each of the variable delay means in the variable delay means group is performed. 12. The second delay amount control processing comprises an exclusive OR of a signal output from a predetermined stage in the variable delay means group and an output of the duty reproducing section.
Of the exclusive OR circuit and a second charge pump circuit that receives the output of the second exclusive OR circuit as input, and the variable delay means is based on the output of the second charge pump circuit. 12. The phase-locked clock signal generation method according to claim 11, wherein the delay amount of each variable delay means in the group is controlled. 13. The second delay amount control processing captures an output of a first stage in the variable delay means group in synchronization with a falling edge of an output of the duty reproducing section.
And a second logical sum circuit that takes the logical sum of the output of the second exclusive logical sum circuit and the inverted output of the second flip flop, and the second logical sum circuit The input of the output of the variable charge delay circuit is input to the second charge pump circuit, and the delay amount of each variable delay means in the variable delay means group is controlled based on the output of the second charge pump circuit. 13. The method for generating a phase-locked clock signal according to item 12. 14. The delay amount control process includes a third flip-flop that captures an output of the preceding stage of the predetermined stage in the variable delay means group in synchronization with a falling edge of an output of the duty reproducing unit. A logical product circuit that takes a logical product of the output of the second logical sum circuit and the inverted output of the third flip-flop is prepared, and the output of the logical product circuit is input to the second charge pump circuit, 14. The phase-locked clock signal generating method according to claim 13, wherein the delay amount of each variable delay means in the variable delay means group is controlled based on the output of the second charge pump circuit.