JPH0575590A - Synchronizing clock generating circuit - Google Patents

Abstract

PURPOSE:To preliminarily avoid an unexpected state by providing another filter different from a loop filter by time constant and generating a clock switching signal at the time when the difference value between output signals of these filters exceeds a threshold indicating the clock switching and allowing lower-order devices to detect that the clock is switched. CONSTITUTION:When an input clock is switched, the output voltage of a phase comparator 1 is generated in accordance with the phase difference. That is, the output voltage is larger according as the phase difference is larger, and the output voltage is smaller according as the phase difference is smaller. Since filters 2 and 20 which receive this output voltage of the phase comparator 1 have different time constants, the voltage difference is gradually increased till arrival at an input voltage (the output voltage of the comparator 1) when the output voltage of the phase comparator 1 is increased by the increase of the phase difference due to switching of the input clock. Consequently, an abnormality detecting circuit 4 generates the clock switching signal when the voltage difference of time constants is large enough to indicate the clock switching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generating circuit, and more particularly to a synchronous clock generating circuit for synchronizing an output signal with an input signal.

A clock signal is indispensable for transmitting and receiving a digital signal. Since this clock signal is always required to have stability in phase and frequency, a clock signal output from an input clock signal is phase-synchronized. A clock generation circuit is required and used in many clock circuits.

[0003]

2. Description of the Related Art FIG. 4 shows a well-known synchronous clock generation circuit. Reference numeral 1 denotes a phase comparator () for comparing the phases of an input signal and an output signal and outputting the difference value as a voltage ( PC), 2 is a loop filter (LF: low pass filter) for removing harmonic components from the output voltage of the phase comparator 1, and 3 is an output clock whose frequency changes according to the output signal of the filter 2. And a voltage controlled oscillator (VCXO) that is applied to the phase comparator 1,
A phase locked loop (PLL) is formed by these loops.

In the operation of such a synchronous clock generating circuit, the input clock signal and the output clock signal are compared by the phase comparator 1 and the phase difference is output in the form of a voltage signal and given to the filter 2. In the filter 2, when the harmonic component is removed from the output voltage of the phase comparator 1 and given to the voltage controlled oscillator 3, the voltage controlled oscillator 3 changes the oscillation frequency in proportion to the input voltage. The phase difference with the clock signals gradually decreases, and eventually the frequencies and phases of both clock signals match and synchronize.

[0005]

In such a synchronized state, assuming that the input clock signal is a high-level sync clock, the high-level sync clock fails for some reason and the low-level sync clock is changed. Even when it is unavoidable to switch, the phase locked loop synchronizes with the lower level clock.

Therefore, in the lower device which receives the output clock signal of the synchronous clock generating circuit, the lower clock continues to be synchronized, and the operation continues without knowing that the clock level has been switched, There was a problem that a shortage of accidents might occur.

Therefore, an object of the present invention is to make it possible to detect the occurrence of switching of a synchronous clock in a synchronous clock generation circuit in which a phase locked loop is formed by a phase comparator, a loop filter and a voltage controlled oscillator. And

[0008]

FIG. 1 shows a synchronous clock generating circuit according to the present invention for solving the above-mentioned problems, in which another filter 20 having a time constant different from that of the loop filter 2 is provided. The abnormality detection circuit 4 is provided to generate a clock switching signal when the difference value between the output signals 2 and 20 exceeds a threshold value indicating clock switching.

[0009]

In the synchronous clock generating circuit according to the present invention, when in the steady synchronous state, there is no voltage difference between the output signals of the two filters 2 and 20 connected to the phase comparator 1, so that an abnormality is detected. The circuit 4 does not generate the abnormality detection signal, but when the input clock is switched, the output voltage of the phase comparator 1 is generated according to the phase difference. That is, the larger the phase difference, the larger the output voltage, and the smaller the phase difference, the smaller the output voltage.

The filters 2 and 20 receiving the output voltage of the phase comparator 1 have different time constants (time-output voltage characteristics) a and b as shown in FIG. When the phase difference increases and the output voltage of the phase comparator 1 also increases, the voltage difference between the time constants a and b gradually increases until the input voltage (the output voltage of the phase comparator 1) is reached. go.

Therefore, when the voltage difference between the time constants a and b is large enough to indicate clock switching, the abnormality detection circuit 4 generates a clock switching signal. You can know that it has been switched and you can be prepared for an unexpected situation.

[0012]

FIG. 3 shows an embodiment of the synchronous clock generating circuit according to the present invention shown in FIG. 1. In this embodiment, the loop filter 2 is an integrating circuit composed of a resistor r1 and a capacitor c1. The filter 20 provided separately from the loop filter 2 is configured by an integrating circuit including a resistor r2 and a capacitor c2. Each of these filters 2 and 20 has a time constant t1 of the characteristic a shown in FIG.
(= C1 · r1) and the time constant t2 of the characteristic b (= c2 · r)
2). However, the time constant t1 <t2 is set. Further, the abnormality detection circuit 4 is composed of an operational amplifier 41 that takes a difference value between the output signals of the filters 2 and 20 and a comparator 42 that compares the output signal of the operational amplifier 41 with a threshold Th that indicates the switching of the clock. There is.

In such an embodiment, when in a steady synchronization state, the output signal of the phase comparator 1 is almost zero, so there is no voltage difference between the output voltages of the two filters 2, 20. Therefore, the output voltage of the operational amplifier 41 also becomes zero, and the comparator 42 generates the output signal of the level "L" indicating the normal state (the state where the switching of the clock has not occurred).

On the other hand, when the input clock is switched,
When the output voltage of the phase comparator 1 increases according to the phase difference, the output voltage of the filter 2 is the output of the filter 20 with the time constant t2 of the characteristic b according to the time constant t1 of the characteristic a of FIG. Since it approaches the input voltage (the output voltage of the phase comparator 1) more rapidly than the voltage, the difference between both input voltages of the operational amplifier 41, that is, the output voltage gradually increases.

Therefore, when the comparator 42 receiving the output voltage of the operational amplifier 41 is large enough to exceed the threshold value Th indicating the switching of the clock, the output signal becomes the level "H", and the abnormality detection signal (alarm signal) is generated. Since it is output, it is possible to know that the clock has been switched in a lower device that uses this synchronous clock.

[0016]

As described above, according to the present invention, another filter having a time constant different from that of the loop filter is provided, and when the difference value of the output signals of these filters exceeds the threshold value indicating clock switching. Since the abnormality detection circuit that generates the clock switching signal is provided in the device, the lower device can know that the clock has been switched, and an unexpected situation can be avoided in advance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle of a synchronous clock generation circuit according to the present invention.

FIG. 2 is a graph diagram for explaining characteristics of a filter used in the synchronous clock generation circuit according to the present invention.

FIG. 3 is a circuit diagram showing an embodiment of a synchronous clock generation circuit according to the present invention.

FIG. 4 is a block diagram showing a conventionally known synchronous clock generation circuit.

[Explanation of symbols]

 1 Phase Comparator 2 Loop Filter 3 Voltage Controlled Oscillator 4 Abnormality Detection Circuit 20 Filter In the figure, the same symbols indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a synchronous clock generation circuit (10) in which a phase-locked loop is formed by a phase comparator (1), a loop filter (2) and a voltage controlled oscillator (3), the loop filter (2) is Another filter with different constants
(20) is provided, and the abnormality detection circuit (4) that generates the clock switching signal when the difference value of the output signals of these filters (2, 20) exceeds the threshold value indicating clock switching is provided. Characteristic synchronous clock generation circuit.