JPS6226607B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for eliminating steady phase errors and variations thereof between an input clock and a VCO (voltage controlled oscillator) clock in a PLL circuit (phase lock loop). For example, the present invention is a synchronous type
It can be used to regenerate clock pulses in PCM switches.

FIG. 1 shows an example of a circuit configuration used to reduce the steady-state phase error between the input clock and the VCO clock and its fluctuations in a conventional PLL circuit. 1st
In the figure, 1 is a phase comparator, 2 is a voltage amplifier and filter, and 3 is a VCO.

Input clock 4 and VCO clock 5 are input to phase comparator 1, and the phase information is determined by input clock 4 and VCO clock 5.
If it is ahead of the clock, the phase difference pulse advances and the detection output 7 causes the input clock to
If it lags behind the VCO clock, the phase difference pulses are sent by the lag detection output 8 to the voltage amplifier and filter circuit 2, respectively. The amplification filter output 6 becomes a control voltage for the VCO 3, controls the oscillation frequency of the VCO, and operates so that the VCO clock matches the input clock.

In order to reduce steady-state phase errors and fluctuations, the DC gain of the voltage amplifier is increased to increase the DC loop gain. Further, countermeasures have been taken such as reducing the offset of the phase comparator output voltage by independently outputting advance detection and delay detection of the phase comparator output.

However, these measures are insufficient to sufficiently suppress steady phase errors and their fluctuations, and some error fluctuations remain.

Therefore, an object of the present invention is to provide a PLL circuit in which the steady-state phase error and its fluctuations are further reduced, and its characteristics are as follows: The input clock signal 4 is used as one input, and the output of the voltage controlled oscillator 3 is used as the other input. It has a phase comparator 1 having an output 7 for detecting an advance state of the phase difference between the two and an output 8 for detecting a lag state, and a circuit 2 for voltage amplifying/filtering each output. The voltage controlled oscillator 3 is configured such that the oscillation frequency of the voltage controlled oscillator 3 is controlled by the output.
In a PLL circuit that matches the phase of the output of the phase comparator 1 with the phase of the input clock signal, the phase comparator 1
When a circuit 9 is inserted between each output of the circuit 2 and the input of the circuit 2, the circuit 9 stretches the pulse width in proportion to the time width.
It is in the PLL circuit.

FIG. 2 is a block diagram of a PLL circuit according to the present invention, in which reference numbers 1 to 8 indicate the same components as in FIG.
9 is a pulse width expansion circuit.

The operating principle is the same as that of the circuit shown in Figure 1, but compared to the configuration shown in Figure 1, lead detection 7 and delay detection 8 are
A pulse width expansion circuit 9 is added between the two.

When a pulse is input to the pulse width expansion circuit, a pulse whose input pulse width is expanded by a constant ratio is output. This is equivalent to increasing the output voltage gain with respect to the phase difference of the phase comparator by that ratio. By equivalently increasing the gain of the phase comparator, the effects of both the offset of the phase comparator output and the offset of the voltage amplifier, which were the main causes of steady-state phase errors and fluctuations in the circuit shown in Figure 1, can be reduced. becomes possible. PLL is created using the above method.
The steady state phase error and fluctuation of the circuit can be made extremely small.

One embodiment of the invention is shown in FIG. 31 is a phase comparator with two outputs for lead detection and delay detection;
Further, 32 is a complete integral type loop filter.
33 is a pulse width expansion circuit, 34 is a VCO, and 35 is an input clock.

FIG. 4 shows an example of the configuration of the pulse expansion circuit 9, in which the pulse width applied to the input terminal (1N) is expanded and provided to the output terminal (OUT). Here, COMP is a comparison circuit, and between the reference voltages V ₁ and V ₂ , V ₁ >
It is assumed that the relationship V ₂ is satisfied. The switching transistor Tr is turned on/off by an input pulse.
off, and is in the off state when there is no input pulse. At this time, the potential of collector a is the first reference voltage
equal to V ₁ , at which time the comparator circuit (COMP) does not generate an output. When an input pulse is applied, the transistor Tr turns on, and the potential at point a becomes the second
equal to the reference voltage V ₂ , comparator circuit (COMP)
produces output. At the same time, capacitor C is C×
Charged with a time constant of _R1 . When the input pulse turns off, the transistor Tr also turns off, but a
Since the capacitor C is charged, the potential at the point does not immediately reach _V1 , and the comparator circuit (COMP) still generates an output. As the charge in the capacitor C is discharged through the resistors _R1 and _R2 , the potential at point a approaches the reference voltage _V1 , and the output of the comparison circuit (COMP) is turned off. Therefore, depending on the size of the capacitor C and the resistors R ₁ and R ₂ ,
A pulse obtained by expanding the input pulse width is obtained as an output pulse. It is assumed that the charging time constant (C×R ₁ ) is smaller than the input pulse width.

The clock signal in a PCM switch is obtained by multiplying the 64KHz reference pulse, but when using conventional technology, the phase error of the 64KHz pulse is 1 μsec.
It exists to some extent. On the other hand, when the pulse width is expanded by 100 to 150 times according to the present invention, the above phase error is
It can be 10 to 20 nsec or less.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a general PLL circuit for suppressing steady phase errors and fluctuations, Fig. 2 is a block diagram showing the principle of the present invention, and Fig. 3 is an embodiment of the PLL circuit of the present invention. The circuit diagram shown in FIG. 4 is a pulse width expansion circuit. 1; Phase comparator, 2; Voltage amplification/filter,
3; voltage controlled oscillator; 4; clock input signal;
9; Pulse expansion circuit, C ₁ to C ₄ ; Capacitor, R ₁
~R ₆ ; resistance.

Claims (1)

[Claims] 1. A phase comparator which takes the input clock signal 4 as one input, takes the output of the voltage controlled oscillator 3 as the other input, and has an output 7 for detecting a leading state of the phase difference between the two, and an output 8 for detecting a lagging state. 1, and a circuit 2 for voltage amplifying/filtering each output,
In a PLL circuit configured such that the oscillation frequency of the voltage controlled oscillator 3 is controlled by the output of the circuit 2, and the phase of the output of the voltage controlled oscillator 3 matches the phase of the input clock signal, each output of the phase comparator 1 A PLL circuit characterized in that a circuit 9 for expanding the pulse width in proportion to the time width is inserted between the input of the circuit 2 and the input of the circuit 2.