JPS5784624A - Pll circuit - Google Patents

Abstract

PURPOSE:To remove the phase error of clocks, by performing pulse width extension of signals in leading and lagging states having a phase difference being the phase comparison output between an input clock and VCO clock in a PLL circuit and performing voltage amplification/filtering. CONSTITUTION:An input clock 4 and a clock 5 being the output of a VCO3 are inputted to a phase comparator 1, a detected output 7 is generated with leading pulse of the phase difference when the input clock is advanced further than the VCO clock in the phase information and a detected output 8 is generated through delayed pulse of phase difference when the input clock is delayed further than the VCO clock inversely. The pulse width of the outputs 7, 8 is extended at a pulse width extension circuit 9 and supplied to a voltage amplification/filter circuit 2 to control the phase of clocks through the input to the VCO3 at amplification and filtering. Since the pulse width is extended at the pulse width extension circuit 9, the gain of the phase comparator is increased equivalently and the offset of the phase comparator and voltage amplifier can be reduced for both the effects, allowing to prevent phase error.