JPS6477336A - Clock timing control circuit - Google Patents

Clock timing control circuit

Info

Publication number
JPS6477336A
JPS6477336A JP62234192A JP23419287A JPS6477336A JP S6477336 A JPS6477336 A JP S6477336A JP 62234192 A JP62234192 A JP 62234192A JP 23419287 A JP23419287 A JP 23419287A JP S6477336 A JPS6477336 A JP S6477336A
Authority
JP
Japan
Prior art keywords
clock
resonator
signal
output
phase difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62234192A
Other languages
Japanese (ja)
Inventor
Takashi Toma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62234192A priority Critical patent/JPS6477336A/en
Publication of JPS6477336A publication Critical patent/JPS6477336A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To always obtain optimum phases of a clock and data by comparing a phase difference between a demodulated signal and a signal latched by a clock. CONSTITUTION:A demodulated signal is applied to a resonator 2 through a gate 1. The resonator 2 extracts a clock component from the digital signal and a comparator 3 shapes the extracted component to form a reference input to a PLL 4. The demodulated digital signal and the output of a latch 5 are inputted to a phase comparator 6 and an error signal corresponding to a phase difference between two input signals is outputted. The output is smoothed by a low pass filter 7, amplified by an amplifier 8 and its output is applied to the resonator 2 as a control voltage. Consequently, the phase difference between the input data of the latch 5 and the clock is always set up to 90 deg..
JP62234192A 1987-09-18 1987-09-18 Clock timing control circuit Pending JPS6477336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234192A JPS6477336A (en) 1987-09-18 1987-09-18 Clock timing control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234192A JPS6477336A (en) 1987-09-18 1987-09-18 Clock timing control circuit

Publications (1)

Publication Number Publication Date
JPS6477336A true JPS6477336A (en) 1989-03-23

Family

ID=16967124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234192A Pending JPS6477336A (en) 1987-09-18 1987-09-18 Clock timing control circuit

Country Status (1)

Country Link
JP (1) JPS6477336A (en)

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