JPS5651128A - Pll - Google Patents

Pll

Info

Publication number
JPS5651128A
JPS5651128A JP12833979A JP12833979A JPS5651128A JP S5651128 A JPS5651128 A JP S5651128A JP 12833979 A JP12833979 A JP 12833979A JP 12833979 A JP12833979 A JP 12833979A JP S5651128 A JPS5651128 A JP S5651128A
Authority
JP
Japan
Prior art keywords
phase
comparator
sensitivity
output
phase difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12833979A
Other languages
Japanese (ja)
Inventor
Satoshi Yokoya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP12833979A priority Critical patent/JPS5651128A/en
Publication of JPS5651128A publication Critical patent/JPS5651128A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

PURPOSE:To prevent the lock failure dependent upon disturbance, by providing the comparator of a low phase sensitivity and the comparator of a high phase sensitivity in parallel. CONSTITUTION:Input signal SL and signal SV' obtained by delaying the phase of reference signal SV out of the output of VCO11 by pi/2 are supplied to phase comparator 12A, and input signal SL and reference signal SV are supplied to phase and frequency comparator 12B. The phase sensitivity of phase comparator 12A is selected low comparatively, but the phase sensitivity of phase and frequency comparator 12B is selected very higher than that of comparator 12A. When the phase difference is smaller than the reefrence phase difference, only the pulse output of phase and frequency comparator 12B is obtained, but the pulse output is not input to charge pump 16. When the phase difference exceeds the reference phase difference, VCO11 is controlled mainly by the output of phase and frequency comparator 12B, and the response speed of PLL10 becomes rapid correspondingly to extension of the loop band width.
JP12833979A 1979-10-04 1979-10-04 Pll Pending JPS5651128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12833979A JPS5651128A (en) 1979-10-04 1979-10-04 Pll

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12833979A JPS5651128A (en) 1979-10-04 1979-10-04 Pll

Publications (1)

Publication Number Publication Date
JPS5651128A true JPS5651128A (en) 1981-05-08

Family

ID=14982346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12833979A Pending JPS5651128A (en) 1979-10-04 1979-10-04 Pll

Country Status (1)

Country Link
JP (1) JPS5651128A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267035A2 (en) * 1986-11-07 1988-05-11 Archive Corporation Data smoother for a streaming cartridge tape drive
EP0361746A2 (en) * 1988-09-26 1990-04-04 Nec Corporation Automatic phase controlling circuit
EP0474673A1 (en) * 1989-05-01 1992-03-18 Motorola Inc Current reduction of a synthesizer.
WO1994024792A1 (en) * 1993-04-08 1994-10-27 Northern Telecom Limited Phase alignment methods and apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267035A2 (en) * 1986-11-07 1988-05-11 Archive Corporation Data smoother for a streaming cartridge tape drive
EP0361746A2 (en) * 1988-09-26 1990-04-04 Nec Corporation Automatic phase controlling circuit
EP0474673A1 (en) * 1989-05-01 1992-03-18 Motorola Inc Current reduction of a synthesizer.
WO1994024792A1 (en) * 1993-04-08 1994-10-27 Northern Telecom Limited Phase alignment methods and apparatus

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