JPS644117A - Phase locked loop oscillator - Google Patents

Phase locked loop oscillator

Info

Publication number
JPS644117A
JPS644117A JP62157659A JP15765987A JPS644117A JP S644117 A JPS644117 A JP S644117A JP 62157659 A JP62157659 A JP 62157659A JP 15765987 A JP15765987 A JP 15765987A JP S644117 A JPS644117 A JP S644117A
Authority
JP
Japan
Prior art keywords
input signal
oscillator
phase
phase locked
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62157659A
Other languages
Japanese (ja)
Inventor
Yoshikazu Era
Takashi Miyamoto
Katsuyuki Nagano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62157659A priority Critical patent/JPS644117A/en
Publication of JPS644117A publication Critical patent/JPS644117A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a reception fault due to out of phase after the next and succeeding stages from being caused at the restoration from a fault by decreasing the open loop gain of a phase locked loop oscillator more than the open loop gain of other phase locked loop oscillator at the restoration from the fault. CONSTITUTION:An input signal 1 is fed to a phase comparator 4 together with an output signal 3 of a voltage controlled oscillator 2 and a voltage 5 proportional to the phase difference of the both is outputted. The said voltage 5 is fed to an oscillator 2 via a filter 6 and a gain limit circuit 7 to vary the oscillating frequency of the oscillator 2 in a direction that the phase difference between the input signal 1 and the output signal 3 is decreased. On the other hand, when the input signal is interrupted and another input signal arrives again, the gain limit circuit 7 is controlled by an input signal interruption detecting circuit 8 and a timer 9 so as to keep the open loop gain of the said phase locked oscillator to a smaller value in comparison with the value at the normal operation for a prescribed time elapsed after the input signal interruption and the re-arrival of the input signal.
JP62157659A 1987-06-26 1987-06-26 Phase locked loop oscillator Pending JPS644117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62157659A JPS644117A (en) 1987-06-26 1987-06-26 Phase locked loop oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62157659A JPS644117A (en) 1987-06-26 1987-06-26 Phase locked loop oscillator

Publications (1)

Publication Number Publication Date
JPS644117A true JPS644117A (en) 1989-01-09

Family

ID=15654564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62157659A Pending JPS644117A (en) 1987-06-26 1987-06-26 Phase locked loop oscillator

Country Status (1)

Country Link
JP (1) JPS644117A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011188305A (en) * 2010-03-09 2011-09-22 Nippon Dempa Kogyo Co Ltd Pll apparatus
JP2017073700A (en) * 2015-10-08 2017-04-13 富士通株式会社 Clock regenerative circuit, optical module and clock regeneration method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011188305A (en) * 2010-03-09 2011-09-22 Nippon Dempa Kogyo Co Ltd Pll apparatus
JP2017073700A (en) * 2015-10-08 2017-04-13 富士通株式会社 Clock regenerative circuit, optical module and clock regeneration method

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