JP2813183B2 - Frequency phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a frequency and phase synchronization circuit that performs frequency synchronization operation and phase synchronization operation and generates each timing signal that is frequency- or phase-synchronized with an external synchronization signal. In order to reduce or eliminate the difference in time following characteristics, a first control voltage corresponding to a high / low frequency difference between a first synchronization signal and a timing signal output by a timing signal generation means during a frequency synchronization operation. Controls the oscillation frequency of the timing signal generating means, and during the phase synchronization operation, the timing signal is controlled by the second control voltage corresponding to the lead / lag phase difference between the second synchronization signal and the timing signal output by the timing signal generating means. In a frequency phase locked loop that controls the oscillation frequency of the generating means, a servo signal and a timing signal are generated when recording data on a medium. A frequency comparison circuit for outputting a frequency difference signal corresponding to a frequency difference between the timing signal output from the means and a timing signal output means for outputting a read signal from the medium when reproducing data recorded on the medium; A phase comparison circuit that outputs a phase difference signal corresponding to a lead / lag phase difference with a timing signal; a first filter that filters the frequency difference signal to generate the first control voltage; And a second filter that generates the second control voltage by filtering, wherein a rising characteristic of the first filter is slower than a rising characteristic of the second filter.

[Industrial applications]

The present invention relates to a frequency / phase synchronization circuit that performs a frequency synchronization operation using a frequency comparator and a phase synchronization operation using a phase comparator to generate timing signals that are frequency-synchronized or phase-synchronized with an external synchronization signal. .

[Conventional technology]

The frequency comparator is used not only as a single unit but also as a component of a frequency phase locked loop. The frequency phase synchronization circuit is used as a circuit that synchronizes a timing signal generated inside the circuit with a frequency or phase of a synchronization signal input from the outside. For example, when recording the digital data pulse code on the recording medium, the frequency phase synchronization circuit, digital data and generates a timing signal TS _f synchronized with the servo signal frequency of the servo system of the recording medium to the recording medium Record. During reproduction, the same frequency phase locked loop, the timing signal TS _p synchronized with the phase of the read signal from the recording medium occurs, demodulates the digital data by the timing signal.

As shown in FIG. 6, the frequency and phase synchronization circuit comprises a frequency comparator 21, a phase comparator 22, a D / A converter 23, a filter 2
4 and a timing signal generator 25, and a PLL (Phase lock
ed loop) timing signal synchronized with the first synchronization signal FS frequency or the second synchronizing signal PS phase by TS _f or TS _p
Is generated.

LKTSV (Lock to servo) signal and LKTDT (Lock to dat)
e) The signal is a switching control signal. When the frequency comparator 21 is operated, the LKTSV signal is set to ON (high (H) level). When the phase comparator 22 is operated, the LKTDT signal is set to ON (high). (H) level).

Frequency comparator 21, a first synchronization signal FS and for generating a pulse signal having a time width proportional to the frequency difference between the generated timing signal TS _f of the timing signal generator 25 (first reference signal FS and the timing signal The frequency difference from TS _f is essentially the phase difference between the two signals). If the frequency of the timing signal TS _f first reference signal is lower than the frequency of FS namely former phase is behind the latter phase, is proportional to the difference (lag phase with respect to FS of TS _f) that frequency When an INC _f signal with a time width is generated and the frequency is high, that is, when the phase is advanced, a DEC _f signal with a time width proportional to the difference in the frequency (lead phase of FS of TS _f with respect to FS) is generated, and D is generated. /
Send to A converter 23.

The phase comparator 22 compares the phase difference between the timing signal TS _p generated by the second synchronizing signal PS and the timing signal generator 25, the phase of TS _p of the timing signal is delayed than the phase of the second reference signal PS If it has generates a INC _p signal of a time width proportional to the delay phase difference to PS of TS _p, if you are advanced, a time width proportional to the phase difference proceeds to PS of TS _p D
An EC _p signal is generated and sent to the D / A converter 23.

The D / A converter 23 includes a charge pump circuit 231. The charge pump circuit 231 charges the capacitor 241 of the filter 24 from the charge current source 232 through the analog charge switch 233, and discharges the charge in the capacitor 241 of the filter 24 through the analog discharge switch 235 by the discharge current source 234. Discharge. The charge switch 233 is opened and closed by each ING signal of the frequency comparator 21 or the phase comparator 22, and the discharge switch 2
35 is opened and closed by each DEC signal. This allows the filter 24
The control voltage (voltage of capacitor 241) VC output by
The voltage decreases in proportion to the time width of the signal and increases in proportion to the time width of the INC signal. That is, the filter 24 is
For frequency comparator 21, the first of the first control voltage CV _f analog varies in proportion to the frequency difference (phase difference) of the synchronization signal FS and a timing signal TS _f occurs, if the phase comparator 22 and a second control voltage CV _P analog varies in proportion to the phase difference of the second synchronizing signal PS and the timing signal TSp generated and sent to the timing signal generator 25.

Note that the filter 24 is configured by an active or passive integral type filter circuit.
This is equivalent to an integration capacitor of a filter.

The timing signal generator 25, a variable voltage controlled oscillator (hereinafter, indicated by VCO) is composed of a timing signal TS _f changes in proportion to the voltage level of the control voltage VC _f or VC _p supplied from the filter 24 or Generates TS _p and generates frequency comparator 21
And feedback to the phase comparator 22.

In this frequency phase synchronization circuit, the frequency comparator 21 or the phase comparator 22, the D / A converter 23, the filter 24, and the timing signal generator 25 each form a PLL. Thus, in the case of frequency synchronization operation using the frequency comparator 21, the timing signal TS _f synchronized with the frequency of the first synchronization signal FS is generated, if the phase synchronization operation using a phase comparator 22, the second timing signal TS _p synchronized with the phase of the synchronizing signal PS is generated for.

Next, referring to FIG. 7 to FIG. 10, the detailed configuration of the frequency comparator 21 and the phase comparator 22, and * INC, INC, * DEC and D
The generation operation of each signal of EC will be described.

(1) Configuration and operation of frequency comparator First, referring to the configuration diagram of FIG. 7 and the operation timing chart of FIG. 8, the detailed configuration of the frequency comparator 21 and *
The operation of generating the INC _f signal and the * DEC _f signal will be described.

FIG. 7 shows the configuration of the frequency comparator 21.
In the figure, 211A and 211B are JK-type flip-flops (hereinafter referred to as JKFF), 212A and 212B are set / reset-type flip-flops (hereinafter referred to as RSFF), and 213A and 213B have two inputs both at low level ( Hereafter, a pulse signal which becomes a high level (hereinafter, shown by H level) at the time of L level is generated. JKFF211A generates a divided clock of the timing signal TS _f at its Q terminal, *
The inverted signal * is generated at the Q terminal. The JKFF211B generates a frequency-divided clock obtained by further dividing the frequency-divided clock at a Q terminal, and generates a frequency-divided clock * which is an inverted pulse signal thereof at a * Q terminal. An AND circuit 214 generates a pulse signal that goes high when all inputs are low. 215A and 215B are H when all inputs are L level
Generates DEC and INC signals at each Q terminal,
An AND circuit that generates * DEC and * INC signals obtained by inverting them at the Q terminal.

Is the inverted signal of the LKTSV signal * LKTSV signal becomes L level, to enable the AND circuits 215A and 215B for synchronizing the timing signals TS _f the first synchronization signal FS.

In this configuration, JKFF211A is (see FIG. 7 of the TS _f and *) which receives the timing signal TS _f than VCO25 not shown, * Q terminal to generate the divided clock *.

JKFF211B the timing signal TS _f and receives the divided clock, further the divided clock to generate the Q terminal (in FIG TS _f, *, see).

The AND circuit 213A generates an H-level pulse signal when both the Q terminal output (DEC signal) of the AND circuit 215A and the frequency-divided clock are at the L level (see the inverted signal of * DEC and * DEC). Because of the response time of the AND circuit 213A, the pulse signal rises slightly later than the rising point of the divided clock, and the pulse signal falls slightly later than the rising point of the divided clock, as shown in the figure. .

The RSFF 212A generates a pulse signal using the pulse signal generated by the AND circuit 213 as a reset signal and the pulse signal generated by the AND circuit 214 as a set signal (see, in the figure). Also in this case, due to the response time of the RSFF 212A, the pulse signal rises slightly later than the pulse signal, and rises slightly later than the pulse signal as shown in the figure.

On the other hand, the AND circuit 213B is connected to the first synchronization signal FS and the AND circuit 21.
H when 5B Q terminal output (INC _f signal) is both L level
Level pulse signal (FS and * I in the figure)
Refer to the inverted signal of NC). Also in this case, the pulse signal is the first signal.
As shown in FIG.

The RSFF 212B generates a pulse signal using the pulse signal generated by the AND circuit 213 as a reset signal and the pulse signal generated by the AND circuit 214 as a set signal (see, in the figure). The rising and falling of the pulse signal causes a response delay as shown in the figure with respect to each rising of the pulse signal.

The AND circuit 214 generates an H-level pulse signal when the pulse signals generated by the AND circuits 213A and 213B and the pulse signals generated by the RSFFs 212A and 212B are both at the L level. That is, the timing signal TS _f
Is a phase advanced from the first synchronization signal FS, the pulse signal rises at the falling point of the pulse signal that falls latest among the pulse signals 、, and the pulse signal that rises first and simultaneously among the pulse signals 及 び and The pulse signal falls at the time of rising. On the other hand, when the timing signal TS _f
, The pulse signal rises when the pulse signal falls, and falls when the pulse signal and the pulse signal rise simultaneously (see FIG. 6 to FIG. 12). The rise and fall of the pulse signal cause a response delay as shown in the figure with respect to the fall of the pulse signal or the rise of the pulse signal.

When the pulse signals generated by the AND circuits 213A and 214, the pulse signal generated by the RSFF 212A, and * LKTSV are all at L level, the AND circuit 215A generates an L level * DEC _f signal at the * Q terminal, Generates an inverted signal of the * DEC signal at the terminal. In the case of frequency synchronous operation, since * LKTSV is always at the L level, the * DEC _f signal falls at the falling point of the pulse signal and the pulse signal that falls the latest among the The * DEC _f signal rises at the rising edge of the pulse signal that rises earlier (see FIG. 1,, * DEC _f ). Note that the falling and rising of the * DEC _f signal has a response delay as shown in the figure with respect to the falling of the pulse signal and the rising of the pulse signal.

On the other hand, the AND circuit 215B, the pulse signal generated by the AND circuit 213B and 214 and, when the pulse signal and * LKTSV both are L level occurs in RSFF212B, * Q an L level * INC _f signal generated terminal , Q terminal generates an inverted signal of the * INC signal (INC signal). In the case of the frequency synchronization operation, since * LKTSV is always at the L level, the * INC _f signal falls at the falling point of the pulse signal and the pulse signal that falls latest among the pulse signals, and * IN at the rising edge of the pulse signal that rises earlier
The C _f signal rises (see the figure,, * INC _f ). Incidentally, * fall and rise of the INC _f signal is the rising of falling and the pulse signal of the pulse signal, the response delay as shown occurs.

As apparent from the above description of operation, * DEC _f signal and * INC signal is rising at the same time in synchronization with the rising edge of the pulse signal, * DEC _f signal falling in synchronism with the falling edge of the pulse signal, * INC The signal falls in synchronization with the falling of the pulse signal.

On the other hand, the falling of the pulse signal is synchronized with the rising of the timing signal TS, and the falling of the pulse signal is the first signal.
Is synchronized with the rise of the synchronization signal FS. The timing signal TS _f the first synchronization signal FS from the high frequency (TS _f is FS
In this case, the rising of the pulse signal is synchronized with the falling of the pulse signal, that is, the rising of the first synchronization signal FS. When the timing signal TS _f is in the first synchronization signal FS from the lower frequency (TS _f is delayed from the FS phase) Conversely, the rise of the pulse signal falling edge of the pulse signal, i.e. synchronized to the rising edge of the timing signal TS _f I do.

That is, the pulse width of the * DEC _f signal (negative polarity) is proportional to the time difference between the rise of the timing signal TS _{f and} the rise of the first synchronization signal TS _f , and the pulse width of the * INC _f signal (negative polarity) is
It becomes a value proportional to the time difference between the rising edge of the rising and the timing signal TS _f of the first synchronization signal FS. Therefore, * DEC _f signal and * INC _f signal having a pulse width (time width) is a value proportional to the phase difference between the timing signal TS _f the first synchronization signal TS _p (frequency difference). When the frequency of the timing signal TS _f is higher than the frequency of the first synchronization signal FS, that is, when the phase is advanced, the pulse width of the * DEC _f signal becomes larger than the pulse width of the * INC _f signal, and the frequency becomes When the frequency is low (lag phase), the pulse width of the * INC _f signal is larger than the pulse width of the * DEC _f signal, and when the frequency of both signals is equal (in phase), both * DEC _f and * INC _f The pulse widths of the signals are equal.

By opening and closing the charge switch 233 and the discharge switch 235 of the charge pump circuit 231 by the * INC _f signal and the * DEC _f signal generated in this manner, the timing signal T
S _f a first first control voltage VC _f having a level proportional to the frequency difference in height (lead-lag phase difference) of the synchronization signal FS is generated by the filter 24. As the frequency of the first control voltage VC _f by the timing signal TS and the first synchronization signal FS _f (phase) match, the oscillation frequency of the VCO25 is controlled.

(2) Configuration and Operation of Phase Comparator Next, referring to the configuration diagram of FIG. 9 and the operation timing chart of FIG. 10, the detailed configuration of the phase comparator and the generation of the INC _p signal and the DEC _p signal The operation will be described.

FIG. 9 shows the configuration of the phase comparator 22. In the figure, 221A and 221B are AND circuits, which generate an L-level output when an L-level is input. Reference numerals 222A to 222D denote NOT circuits which generate an H level output when an L level is input. 223A and 223B are flip-flops (hereinafter referred to as STFF),
A pulse signal which rises at the input signal of the terminal and falls at the input signal of the CC terminal is generated at the Q terminal, and its inverted signal is generated at the * Q terminal. 224A to 224C are AND circuits that generate an H level output when all inputs are at an L level. 225 is a delay circuit integration type, delayed by a 1/2 period of the timing signal TS _f by integrating the pulse signal generated Q terminal of STFF223A.
226 is a comparator, compares the output level of the reference level V _s of the delay circuit 225, it generates the H level match signal when a match occurs.

* LKTDT are taken for synchronizing the timing signals TS _p to the second synchronizing signal PS and L level, the AND circuit 224B and 224
Enable C.

In this configuration, the AND circuit 221A outputs the timing signal TS
And generates a pulse signal that falls at the time of the fall.
NOT circuit 222A, the pulse signal is inverted, to generate a standing climb inverted pulse signal at the falling time of the timing signal TS _p (see TS _p of FIG. 9). The pulse signal, for a response time of the AND circuit 221A and the NOT circuit 222A, resulting in delays as shown with respect to the timing signal TS _p.

The AND circuit 224A generates a pulse signal that becomes H level when both the pulse signal generated by the timing signal TS _p NOT circuit 222A and the pulse signal generated at the Q terminal of the STFF 223B are L level. That is, the timing signal T
The pulse signal rises at the falling point of S _p , the pulse signal, and the timing signal TS _p falling at the latest time, and the pulse signal falls at the rising time of the pulse signal rising at the earliest time among the three signals. TS _p ,,, in the figure). Incidentally, the rise and fall of the pulse signal is the rising of the rising and the pulse signal of the timing signal TS _p, produces a response delay as shown.

The STFF 223B outputs a pulse signal that rises at the time of the rise of the pulse signal generated by the AND circuit 224A, and that falls at the time of the rise of the second synchronization signal PS to the Q terminal. * Is generated (see PS, in the figure). Note that the falling and rising of the pulse signal causes a response delay as shown in the figure with respect to the rising of the second synchronization signal PS and the rising of the pulse signal.

On the other hand, the STFF 223A generates a pulse signal (not shown) which rises at the rising point of the coincidence signal generated by the comparator 226 and falls at the rising point of the second synchronizing signal PS at the Q terminal, and inverts the pulse signal. * Is generated at the * Q terminal (see TS _p ,, * in the same figure). Incidentally, the rise and fall of the pulse signal is the rising of the rising and the coincidence signal of the second synchronizing signal TS _p, produces a response delay as shown.

The delay circuit 225 receives the pulse signal generated from the Q terminal of the STFF 223A and generates an integrated signal that decreases according to the time constant (see FIG. 3).

The comparator 226 compares the integrated signal with a reference level V _s generated by the integrator circuit, for generating a coincidence signal when they match. Upon receiving the coincidence signal, the pulse signal at the Q terminal of STFF223A rises, and the pulse signal * at the * Q terminal falls. As a result, the capacitor of the integrating circuit 225 rapidly discharges, so that the integration signal rises rapidly and the comparator 22
The coincidence signal generated at 6 falls (, *,
reference).

The NOT circuits 222B and 222C generate a pulse signal obtained by delaying the pulse signal generated at the Q terminal of the STFF 223B by their response time (see).

On the other hand, the AND circuit 221B and the NOT circuit 222D
It inverts the pulse signal * generated at the Q terminal and generates a pulse time delayed by their response time (see * in the figure).

In this case, NOT circuits 222B and 222C and AND circuits 221B and NO
The response delay time with the T circuit 222D is configured to be equal.

Since the * LKTDT signal is at the L level, the AND circuit 224B
When both the pulse signal generated by the STFF 223A and the pulse signal generated by the NOT circuit 222C are at the L level, an INC _p signal that goes to the H level is generated. That is, the INC _p signal is
It rises when the pulse signal * falls, and falls when the pulse signal rises (see *, INC _{p in the} figure). The rise and fall of the INC _p signal cause a response delay as shown with respect to the fall of the pulse signal * and the rise of the pulse signal.

On the other hand, since the * LKTDT signal is at the L level, the AND circuit 224C generates the DEC _p signal which goes to the H level when both the pulse signals * generated by the STFF 223B are at the L level. That is, the DEC _p signal rises at the time of the falling (rising) of the pulse signal *, and falls at the time of the rising of the pulse signal (see the inverted signal and reference in the figure). The rising and falling of the DEC _p signal causes a response delay as shown in the drawing with respect to the falling (rising) of the pulse signal * and the rising of the pulse signal.

As is apparent from the above description of the operation, the time width of the INC _p signal is proportional to the time difference between the time when the pulse signal * falls and the time when the pulse signal rises.

On the other hand, the rising point of the pulse signal * is the second synchronization signal.
Proportional to the rise time of the PS, the rise time of the pulse signal is proportional to the fall time of the timing signal TS _p. Therefore, the time width of the INC _p signal is a time width proportional to the delay phase difference of the timing signal TS _p with respect to the second synchronization signal PS (see *, INC in the figure).

Further, the time width of the DEC _p signal is proportional to the time difference between the time when the pulse signal * falls (rises) and the time when the pulse signal rises. On the other hand, the falling of the pulse signal * (rising) time is proportional to the fall time of the timing signal TS _p, the rise time of the pulse signal is proportional to the rise time of the second synchronization signal PS. Therefore, the time width of the DEC _p signal is proportional to the advance phase difference of the timing signal TS _p with respect to the second synchronization signal PS (see, DEC in the figure).

Since the response times of the STFFs 223A and 223B are equal, the rising time of the pulse signal and the falling time of * and * coincide. Also, NOT circuits 222B to 222D and AND circuit 21
Since the response time of 2B is also equal, when the timing signal TS and the second synchronization signal PS have the same phase, the INC _p and DEC _p signals have the same time width and the same phase. When the phase of the timing signal TS _p with respect to the second synchronization signal PS is delayed, the time width of the INC _p signal increases, and conversely, the time width of the DEC _p signal decreases. As the phase advances, the time width of the INC _p signal decreases, and conversely, DEC _p
The time width of the signal increases.

By opening and closing the charging switch 233 and discharging switch 235 in the charge pump circuit 231 by this way INC _p signal was created and DEC _p signals, the timing signal TS _p and the second synchronizing signal PS proceeds and the delay phase difference second control voltage VC _p having a level proportional to are generated from filter 24. Timing signal TS by the second control voltage VC _p
The oscillation frequency of the VCO 25 is controlled so that the phase of the second synchronization signal PS and the phase of the second synchronization signal PS match.

When this phase synchronization circuit is used in a recording / reproducing apparatus for a recording medium, a servo clock signal of a servo system is used as the first synchronization signal FS, and a read signal from the recording medium is used as the second synchronization signal. Thus, at the time of recording, a timing signal TS synchronized with the servo clock signal is generated, and the recording of digital data on a recording medium is performed by the timing signal TS. At the time of reproduction, a timing signal TS synchronized with the phase of a read signal from a recording medium is generated, and demodulation of digital data is performed by the timing signal.

[Problems to be solved by the invention]

In the frequency-phase synchronization circuit, the pulse width of the first synchronization signal FS applied to the frequency comparator 21 is
Is generally wider than the pulse width of the second synchronizing signal PS added to. For example, in the case of a magnetic recording / reproducing device, the pulse width of the servo clock signal corresponding to the first synchronization signal FS is about several times wider than the pulse width of the read signal corresponding to the second synchronization signal PS. And generated by the frequency comparator 21 *
The maximum pulse width of the INC _f and * DEC _f signals is the first synchronization signal
The maximum pulse width of the INC _p and DEC _p signals generated by the phase comparator 22 equal to the pulse width of FS is equal to the second synchronization signal
It is equal to the pulse width of PS (however, if there is a missing clock, it becomes even larger). That is, as shown in the operation timing charts of FIGS. 8 and 10, the pulse widths of the * INC _f and * DEC _f signals at the time of frequency comparison are different from those at the time of phase comparison.
It is generally wider than the pulse width of the INC _p and DEC _p signals.

On the other hand, the church pump circuit 231 includes * INC _f , * DEC _f , INC
_When the pulse width of each signal such as _p and DEC _p increases, the energization time increases, the charge / discharge current increases, and the loop gain of the synchronous loop increases. That is, the pulse widths of * INCf and * DECf output by the frequency comparator are wider than the pulse widths of INCp and DECp output by the phase comparator.
A control voltage as shown in the figure is generated from the charge pump circuit 231, and the loop gain when using the frequency comparator becomes larger than the loop gain when using the phase comparator.

Here, the frequency comparator is used when recording digital data on the recording medium, and the phase comparator is used when reading digital data from the recording medium. A problem occurs in that the data recording timing and the reading timing are shifted.

When the recording density of digital data to be recorded on the medium is not high, the data read margin is large, so that the read timing shift due to the above-mentioned fluctuation of the servo clock signal, that is, at the time of frequency synchronization operation and phase synchronization movement operation The following differences in the following characteristics of the respective timing signals did not cause any particular problem.

However, when high-density recording is performed recently, the pulse width of each signal and the interval between signals are shortened, and as described in FIGS.
Since the response time of the data cannot be ignored, the data read margin has been reduced. For this reason, even when a slight difference between the timing of data recording and the timing of reading due to the fluctuation of the servo clock signal (first synchronization signal FS _f ), an error occurs at the time of reading data.

The present invention, frequency phase difference modified to reduce or eliminate the follow-up characteristics and tracking performance of the timing signal TS _p during phase synchronization operation of the synchronization circuit of the frequency synchronization Operation timing signal TS _f, and frequency synchronization from the phase It is an object of the present invention to provide a frequency-phase synchronization circuit that is quickly brought into a synchronization state when switching from synchronization to phase synchronization to frequency synchronization.

[Means for solving the problem]

Means adopted by the present invention to solve the above-mentioned problem will be described with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, 11 is a frequency comparator, 12 is a phase comparator, 13 is D / A conversion means, 14 is a first filter, and 15 is a second filter.
Reference numeral 16 denotes a timing signal generating means.

Frequency comparator 11, a frequency having a first comparing the frequency of the generated timing signal TS _f of the synchronization signal FS and a timing signal generator 16, its height frequency difference i.e. time width corresponding to the lead-lag phase Generate a difference signal DF.

Phase comparator 12, the second comparing the phases of the generated timing signals TS _p of the synchronization signal PS and the timing signal generator 16, the lead-lag generating a phase difference signal DP having a time width corresponding to the phase difference I do.

The D / A conversion means 13 receives the frequency difference signal DF from the frequency comparator 11 or the phase difference signal DP from the phase comparator 12, and receives a D / A conversion signal DAF or DAP having an output level corresponding to the time width. Respectively occur.

The first filter 14 generates a first control voltage VC _f to filter the D / A conversion signal DAF of the frequency difference signal DF.

The second filter 15 generates a second control voltage VC _p to filter the D / A conversion signal DAP of the phase difference signal DP.

Timing signal generating means 16, each receiving a second control voltage VC _p from the first control voltage VC _f or the second filter from the first filter 14, the frequency in proportion to the voltage level changes generating a timing signal TS _f or TS _p.

In this configuration, the frequency comparator 11, the D / A conversion means 1
3. The loop of the first filter 14 and the timing generator 16 and the loop of the phase comparator 12, the D / A converter 13, the second filter 15 and the timing generator 16
L is formed.

(Operation)

The operation of the frequency phase locked loop circuit of the present invention shown in FIG. 1 will be described with reference to the characteristic diagrams of each control voltage shown in FIG.

When generating the timing signal TS synchronized with the first synchronizing signal FS, the frequency comparator 11 compares the frequency of the first synchronizing signal FS with the frequency of the timing signal TS generated by the timing signal generating means 16, and compares the frequency. A frequency difference signal DF having a time width corresponding to the high / low frequency difference (lead / lag phase difference) is generated.

The D / A conversion means 13 receives the frequency difference signal DF from the frequency comparator 11, and generates a D / A conversion signal DAF having an output level proportional to the time width.

The first filter 14 is to filter the D / A conversion signal ADF that received from D / A converter 13 generates a first control voltage VC _f.

Timing signal generating means 16 receives the first control voltage VC _f from the first filter 14 and fed back to the frequency comparator 11 generates a timing signal TS _f which changes the frequency to follow the voltage level .

Frequency comparator 11, D / A conversion means 13, first filter 14
And since the loop of the timing generating means 16 forms a PLL, from the timing signal generator 16, the timing signal TS _f synchronized with the frequency of the first synchronization signal FS is generated.

If for generating a timing signal TS _p synchronizing the second synchronizing signal PS, the phase comparator 12, a timing signal TS _p generated by the second synchronizing signal PS and the timing signal generator 16
And a phase difference signal DP having a time width corresponding to the lead / lag phase difference is generated.
Send to

Hereinafter, as in the case of the frequency comparator 11, the D / A conversion means 13 generates a D / A conversion signal DAP having an output level proportional to the time width of the phase difference signal DP.

The second filter 15 is to filter the D / A conversion signal DAP which has received from the D / A converter 13 generates a second control voltage VC _p.

Timing signal generating means 16 receives the second control voltage VC _p from the second filter 14, generates a timing signal TS _p which changes its frequency in proportion to the voltage level.

Since the loop of the phase comparator 12, the D / A conversion means 13, the second filter 15, and the timing generation means 16 forms a PLL, the timing signal generation means 16 outputs the phase of the second synchronization signal FS. synchronized timing signal TS _p is generated.

FIG. 2 (A) shows a first control voltage VC _f when thus generated frequency synchronous operation, FIG. (B) showed a second control voltage VC _p in Phase ratios synchronous operation Things.

In FIG. 7A, a broken line VC _f ′ indicates a frequency comparator 1
1 shows the first control voltage characteristic in the case where a conventional filter is used without providing the first filter 14 for the output of FIG.
_f indicates a first control voltage characteristic when the first filter 14 is provided.

In FIG. 7B, the solid line VC _p indicates the second filter 1.
5 shows a second control voltage characteristic when 5 is provided.

The gain of the frequency comparator 11 and the D / A conversion means 13 at the time of frequency comparison is the phase comparator 12 and the D / A conversion means 1 at the time of phase comparison.
3, the rising characteristic of the first control voltage VC _f ′ when the filters 14 and 15 are not provided
Is sharper than the rising characteristic of the control voltage VC _p ′.

When the first filter 14 and the second filter 15 are provided,
The former is configured to have a relatively slow rise characteristic than the latter, a decrease in the slope of the rising characteristics of the first control voltage VC _f output from the first filter 14 is large, the second Second control voltage VC output from filter 15
The slope of _p decreases less.

Therefore, the first filter 14 and the second filter 15
By selecting the rise characteristics from
Rising characteristic of the first control voltage VC _f is set to be slower than the rise characteristics of the second control voltage VC _p, or decreases the difference of the rising characteristics of the control voltage VC _p and VC _f is output from both the filter Can be eliminated.

Thus, it is possible to eliminate reduction or the difference between the follow-up characteristic and the phase synchronizing operation at the follow-up characteristics of each timing signal TS _f and TS _p timing signal TS during frequency synchronization operation of the frequency phase locked loop.

By generating each timing signal for recording and reading digital data at the time of recording / reproducing by using the frequency / phase synchronizing circuit thus configured, the first synchronizing signal is generated.
Even if the servo clock signal corresponding to FS fluctuates, the difference between the timing of digital data recording and the timing of reading can be reduced or eliminated.Therefore, eliminate errors during data reading even in high-density recording. Can be.

By the way, during the frequency synchronizing operation using the frequency comparator 11 and the first filter 14, the second filter 15 is not used, so that the capacitor (not shown) constituting the second filter 15 is in a discharged or fully charged state. Conversely, during the phase synchronization operation using the phase comparator 12 and the second filter 15, since the first filter 14 is not used, the capacitor (not shown) constituting the same is in a discharged or fully charged state.

For this reason, when switching from frequency synchronization operation to phase synchronization operation or vice versa, the timing signal generation means
Since the level of the control voltage VC applied to 16 changes greatly,
The frequency transition of the timing signal TS becomes large, and the transition to the predetermined frequency is delayed or a transient occurs.

In order to solve this, in another embodiment of the present invention, the control voltage VC generated by one filter is fed back to the other filter that is not in use.

As a result, the capacitor constituting the other unused filter is charged to a certain level, so that when the synchronous operation is switched, the control voltage VC fluctuates little. The transition can be made to the signal frequency.

First Embodiment A first embodiment of the present invention will be described with reference to FIG. 3 and FIG. FIG. 3 is an explanatory diagram of the configuration of the first embodiment of the present invention, and FIG. 4 is an explanatory diagram of the configuration of first and second filters used in the first embodiment.

(A) Configuration of Embodiment In FIG. 3, the frequency comparator 11, the phase comparator 12, and the D /
The A conversion means 13, the first filter 14, the second filter 15, and the timing signal generation means 16 are as described in FIG.

The LKTSV and LKTDT signals are switching control signals and are used as frequency comparators.
When operating the 11 side, the LKTSV signal is on (high (H)
LKTDT signal is set to ON (high (H) level) to operate the phase comparator 12 side.

Frequency comparator 11 compares the frequency of the timing signal TS _f generated by the first synchronization signal FS and a timing signal generator 16, when TS _f is the frequency lower than FS, i.e. than TS _f is FS When the phase is lagging, an INC _f signal with a time width proportional to the frequency (phase) difference is generated. When the frequency is high, that is, when TS _f is ahead of FS, the frequency (phase) is generated. DE with a time width proportional to the difference
Generate the C _f signal. As the frequency comparator 11, for example, the frequency comparator shown in FIG. 7 is used.

The phase comparator 12 compares the phases of the timing signal TS _p generated by the second synchronizing signal PS and the timing signal generator 16, when TS _p is phase lag than PS is proportional to the delay phase difference An INC _p signal having a predetermined time width is generated. If the signal has a leading phase, a DEC _p signal having a time width proportional to the leading phase difference is generated. As the phase comparator 12, for example, the phase comparator shown in FIG. 9 is used.

In the D / A conversion means 13, reference numeral 131 denotes a multiplexer (hereinafter, referred to as MPX). When the LKTSV signal is on, an INC _f and a DEC _f signal generated by the frequency comparator 11 are selected.
When the signal is on, INC _p generated by the phase comparator 12 and
Select the DEC _p signal.

Reference numeral 132 denotes a charge pump circuit that supplies a charging current to the filter for the time width of the INC signal and discharges the current on the filter side for the time width of the DEC signal.

Reference numeral 133 denotes a first switch, which is constituted by an analog switch. The common contact c is on the charge pump circuit 132 side, the contact f is on the first filter 14 side, and the contact p is on the second filter 15 side.
The common contact c is connected to the contact f at the time of the frequency synchronous operation, and the common contact c is connected to the contact p at the time of the phase simultaneous operation.
Connected to

In the timing signal generating means 16, reference numeral 161 denotes a second switch, which is a contact f connected to the first filter 14,
Having a contact p and a common contact c connected to the filter of
At the time of frequency synchronization operation, the common contact c is connected to the contact f,
During the phase synchronization operation, the common contact c is connected to the contact p.
Note that the switching between the first switch 133 and the second switch 161 is performed in an interlocked manner.

162 is a buffer amplifier, connected to the common contact c, which functions as a buffer for each control voltage VC _f or VC _p inputted from the first filter 14 or the second filter 15.

163 voltage controlled oscillator (hereinafter, indicated by VCO), the timing signal TS _f or TS _p varies in proportion to the voltage level of the control voltage VC _f or VC _p is input from the buffer amplifier 162
Is generated and fed back to the frequency comparator 11 and the phase comparator 12.

FIG. 4 (A) is an illustration of an example of a first filter 14, and a series circuit of a capacitor C _A and the resistor R _A.
Figure 4 (B) is an illustration of an example of the second filter 15, composed of a series circuit of a capacitor C _B and a resistor R _B.

(B) Operation of the First Embodiment The first embodiment using the frequency comparator 11 and the first filter 14
If the generation of the timing signal TS _f synchronized with the synchronizing signal FS is, LKTSV signal ON (LKTDT signal off) is set to the first switch 133 and second switch 161 is switched to the contact f side.

The frequency comparator 11 operates when the LKTSV signal is on,
The first compares the frequencies of the generated timing signal TS _f of the synchronization signal FS and a timing signal generator 16, when TS _f is a frequency lower than FS, the frequency difference as a frequency difference signal DF (delayed phase) It generates INC _f signal proportional to the time width, when a high frequency, generates a DEC _f signal proportional to the time width to the frequency difference (leading phase) as the frequency difference signal DF. In the case where the frequency comparator shown in FIG. 7 is used as the frequency comparator 11,
An INC _f signal and a * DEC _f signal are generated.

When the LKTSV signal is on, the MPX131
The INC _f and DEC _f signals generated by 1 are selected and supplied to the charge pump circuit 132.

The charge pump circuit 132 outputs the INC _f signal (* I in FIG. 8).
When NC _f signal) is supplied, the charge current through the first switch 133 is supplied to the first filter 14 to charge the capacitor C _A, the DEC _f signal (FIG. 8 * DEC _f when the signal) is supplied to discharge the capacitor C _a. IN
When the time width of the C _f signal and DEC _f signal is equal, i.e., when the frequency of the first synchronization signal FS and a timing signal TS _f matches the charge amount of the capacitor C _A is not changed.

The first filter 14 receives the charging and discharging by a charge pump circuit 132 generates a first control voltage VC _f the output level in accordance with the time constant C _A R _A is changed.

The first control voltage VC _f is supplied to VCO163 through the second switch 161 and the buffer amplifier 162.

VCO163 receives a first control voltage from the buffer amplifier 163 (indicated by the same VC _f), is fed back to the frequency comparator 11 generates a timing signal TS _f which changes the frequency to follow the voltage level.

Frequency comparator 11, D / A conversion means 13, first filter 14
And since the loop of the timing signal generating means 16 forms a PLL, from the timing signal generating means 16 (VCO163), the timing signal TS _f synchronized with the frequency of the first synchronization signal FS is generated.

 Next, the phase synchronization operation will be described.

If for generating a timing signal TS _p synchronizing the second synchronizing signal PS by using the phase comparator 12 and the second filter 15, LKTDT signal is set to ON (LKTSV signal off), the first The switch 133 and the second switch 161 are connected to the contact p
Side.

The phase comparator 12 is actuated when the LKTDT signal is on, to compare the frequency of the timing signal TS _p generated by the second synchronizing signal PS and the timing signal generator 16, the phase of TS _p is PS
If the phase is delayed from the phase of the PS, an INC _p signal with a time width proportional to the phase difference is generated.If the phase of the TS _p is ahead of the phase of the PS, the time width proportional to the phase difference is generated. Of the DEC _p signal. When the phase comparator of FIG. 9 is used as the phase comparator 12, the INC _p signal and the DEC _p signal are generated by the operation described in FIG.

When the LKTDT signal is on, the MPX131
Supplied to the charge pump circuit 132 by selecting the INC _p and DEC _p signal generated.

The charge pump circuit 132 outputs an INC _p signal (INC in FIG. 10).
_{When p} signal) is supplied, the charge current through the first switch 133 is supplied to the second filter 15 to charge the capacitor C _B, DEC _p signal (DEC _p signal in FIG. 10) when it is supplied discharges the electric charge of the capacitor C _B. When the time width of the INC _p signal and DEC _p signal is equal, i.e., when the second synchronization signal PS and the timing signal TS _p of phase with the charge amount of the capacitor C _B is not changed.

The second filter 14 receives the charging and discharging by a charge pump circuit 132, it generates a second control voltage VC _p the time constants C _B R output level according to _B is changed.

The second control voltage VC _p is supplied to VCO163 through the second switch 161 and the buffer amplifier 162.

VCO163 receives the second control voltage from the buffer amplifier 163 (indicated by the same VC _p), then it follows the voltage level and generates a timing signal TS _p whose phase change fed back to the phase comparator 12.

Since the loop of the phase comparator 12, the D / A converter 13, the second filter 15, and the timing signal generator 16 forms a PLL, the timing signal generator 16 (VCO 163) outputs the second synchronization signal. Timing signal synchronized with PS phase
TS _p is generated.

Thus generated in the frequency synchronization control voltage VC _f during operation is as shown in FIG. 2 (A), the control voltage VC _p during the phase synchronization operation is as shown in FIG. 2 (B) .

By the way, in the transfer functions of the first PLL including the frequency comparator 11 and the first filter 14 and the second PLL including the phase comparator 12 and the second filter 15, the natural angular frequency ω _n and the damping factor ζ , Are given by the following equations (1) and (2).

ω _n = (I ₀ K ₀ / 2πC) ^2/1 (1) ζ = (RC / 2) ω _n (2) I ₀ : Filter input current (output current of charge pump circuit 132) K ₀ (loop _{gain) = K 1 · K 2 K} 1: gain K ₂ frequency 11 or the phase comparator 12: VCO163 gain R: resistors constituting the filter (R _a or R _B) C: constituting a filter Capacitor (C _A or C _B ).

Generally, the following characteristic becomes faster as ω _n is higher. Since the time width of the INC _f and DEC _f signals output from the frequency comparator 11 is generally larger than the time width of the INC _p and DEC _p signals output from the phase comparator 12, the output current I of the former charge pump circuit is ₀ is larger than the latter output current I ₀ .

Therefore, if filters with the same configuration are used,
Since the natural angular frequency ω _np of the first PLL is higher than the natural angular frequency ω _nf of the second PLL, the following speed during the frequency synchronization operation is faster than the following speed during the phase synchronization operation.

As in this embodiment, the first filter 14 is constituted by a series circuit of a resistor R _A and capacitor C _B, resistor R _B and capacitor C _B
When the second filter 15 is configured by the series circuit of
If the resistors R _A and R _B and the capacitors C _A and C _B are selected so that the condition of the following equation (3) is satisfied, the natural frequency ω _nf of the first PLL is reduced, and the following is performed during the frequency synchronization operation. Speed can be reduced.

C _A > C _B R _A <R _B (3) By making such selections, it is possible to reduce or eliminate the difference in the following characteristics between the frequency synchronization operation and the phase synchronization operation.

Therefore, by generating each timing signal for recording and reading digital data at the time of recording / reproducing by using the frequency / phase synchronizing circuit thus configured, a fluctuation occurs in the servo clock signal corresponding to the first synchronizing signal FS. However, since the difference between the timing of recording and reading digital data can be reduced or eliminated, it is possible to eliminate the occurrence of errors in reading data even in the case of high-density recording.

[Second Embodiment] In the first embodiment, when the first filter 14 is used, the second filter 15 is not used, so that the capacitor B of the second filter 15 is discharged. Conversely, the second
Since the first filter when using the filter 15 is not used, the capacitor C _A of the first filter 14 becomes discharged.

Therefore, as described above, when switching from the frequency synchronization operation to the phase synchronization operation or vice versa, the VCO
Since the level of the control voltage VC applied to the timing signal TS changes greatly, the frequency transition of the timing signal TS increases, and the transition to the predetermined frequency is delayed or a transient occurs.

The second embodiment is designed to eliminate this problem. Hereinafter, the second embodiment will be described with reference to FIG.

In FIG. 5, the first switch 1 in the D / A conversion means 13
34 and the buffer amplifier 162 to the first switch 134
Other configurations except for the configuration fed back
This is the same as the first embodiment shown in the figure.

The first switch 134 has an F switch 134F and a P switch 1
It has two sets of switches of 34P. F of F switch 134F
P ₂ contacts ₁ contact and P switch 134 is connected to the charge pump circuit 132 in common. P ₁ contact of F switch 134F and P
F ₂ switches of the switch 134P is common to the buffer amplifier 16
Common contact c ₁ of F switch 134F connected to the second output side is connected to the first filter 14, common contact c ₂ of P switch 134P is connected to the first filter 15. The second switch 161 is switched to the f side during the frequency synchronization operation, and is switched to the p side during the phase synchronization operation. F switch 134F and P switch 134P is switched in conjunction with the second switch 161, when frequency synchronization operation, c ₁ is c ₂ to f ₁ is connected to f _2, when the phase synchronization operation, c ₁ Is connected to p ₁ and c ₂ to p ₂ .

In this configuration, when the LKTSV signal is turned on (the LKTDT signal is turned off) and the first switch 134 and the second switch 161 are connected to the f-side, the frequency comparator 11 is turned on, as described in the first embodiment. and frequency synchronization operations are performed using the first filter 14, from VCO163, the timing signal TS _f synchronized with the frequency of the first synchronization signal FS is generated.

In this case, the first control voltage VC _f to the output of the buffer amplifier 162, is fed back to the second filter 15 through the contacts of f ₂ and c ₂ of the P switch 134P to charge the capacitor C _B.

Next, when the LKTDT signal is turned on (the LKTSV signal is turned off) and the first switch 134 and the second switch 161 are switched to the p-side, the phase comparator 12 and the second Phase synchronization operation using the filter 15 of
From VCO163, the timing signal TS _p synchronized with the phase of the second synchronizing signal PS is generated.

In this case, the capacitor C _B of the second filter 15, since it is charged at a constant level of voltage by the first control voltage VC _f before switching, the second control voltage VC with the switching
The level change of _p is small, so that VCO163
It is possible to quickly and smoothly perform phase synchronization with the second synchronization signal PS.

On the other hand, VC _p of the second control voltage output of the buffer amplifier 162 is fed back to the first filter 14 through the respective contacts of the p ₁ and c ₁ of the P switch 134P to charge the capacitor C _A.

Therefore, even if it switches to the frequency synchronization operation again,
Since the capacitor C _A of the first filter 14 has already been charged to a predetermined level, the level change of the first control voltage VC _f is small, VCO163 is quickly and smoothly frequency synchronization with the first synchronizing signal FS Can be.

If the control voltage level to be fed back is too high, the control voltage is fed back to the counterpart filter via the voltage dividing resistor.

The embodiments of the present invention have been described above, but the embodiments of the present invention are not limited to these embodiments. For example, the first and second filters can be used for various known filters other than a series circuit of a resistor and a capacitor.

〔The invention's effect〕

As described above, according to the present invention, the following effects can be obtained.

(1) It is possible to reduce or eliminate the difference between the tracking characteristic at the time of the frequency synchronization operation using the frequency comparator and the tracking characteristic at the time of the phase synchronization operation using the phase comparator.

(2) By feeding back the control voltage at the time of one synchronous operation to the filter used for the other synchronous operation, the fluctuation of the control voltage when switching the frequency and phase synchronous operation is reduced, and the synchronous operation after the switching is quickly performed. And smoothly.

(3) By generating each timing signal for recording and reading digital data at the time of recording / reproducing by using the frequency / phase synchronizing circuit thus configured, a fluctuation occurs in the servo clock signal corresponding to the first synchronizing signal. Even
Since the difference between the timing of digital data recording and the timing of reading digital data can be reduced or eliminated, it is possible to eliminate errors during data reading even in the case of high-density recording.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention, FIG. 2 is an explanatory diagram of each control voltage characteristic in the present invention and an embodiment, FIG. 3 is an explanatory diagram of a configuration of an embodiment of the present invention, FIG. FIG. 5 is an explanatory diagram of the configuration of each filter used in the embodiment, FIG. 5 is an explanatory diagram of the configuration of the second embodiment of the present invention, FIG. 6 is an explanatory diagram of the configuration of a conventional frequency phase locked loop circuit, 7 is an explanatory diagram of a configuration of a conventional frequency comparator, FIG. 8 is an operation timing chart of the conventional frequency comparator, FIG. 9 is an explanatory diagram of a configuration of the conventional phase comparator, and FIG. FIG. 11 is an explanatory diagram of control voltage characteristics generated by a conventional frequency / phase locked loop circuit. 1, 3 and 5, 11... Frequency comparator, 12... Phase comparator, 13... D / A converter, 131... Multiplexer (MPX), 132. , 133,134… First switch, 14…
1st filter, 15 ... second filter, 16 ... timing signal generation means, 161 ... second switch, 162 ... buffer amplifier, 163 ... voltage controlled oscillator (VCO).

────────────────────────────────────────────────── (5) References JP-A-59-23926 (JP, A) JP-A-60-249429 (JP, A) JP-A-61-77429 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H03L 7/08-7/113

Claims (1)

(57) [Claims] In the frequency synchronizing operation, the oscillation frequency of the timing signal generating means is controlled by a first control voltage corresponding to a high / low frequency difference between the first synchronizing signal and the timing signal output by the timing signal generating means. During the phase synchronization operation, the frequency and phase synchronization controls the oscillation frequency of the timing signal generation means by the second control voltage corresponding to the lead / lag phase difference between the second synchronization signal and the timing signal output by the timing signal generation means. A frequency comparison circuit that outputs a frequency difference signal corresponding to a high / low frequency difference between a servo signal and a timing signal output by the timing signal generating means when recording data on the medium; and reproducing the data recorded on the medium. When the read signal from the medium and the timing signal output by the timing signal generating means A phase comparison circuit that outputs a phase difference signal corresponding to a phase difference; a first filter that filters the frequency difference signal to generate the first control voltage; and a second filter that filters the phase difference signal. And a second filter that generates the control voltage of (i), wherein a rising characteristic of the first filter is slower than a rising characteristic of the second filter.