JPS5839372Y2 - Noise elimination type delay circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an improvement of a delay circuit that electrically corrects the mechanical deviation of each pen in a multiplex recording device configured to record with a plurality of pens. The present invention relates to a noise elimination type delay circuit characterized by reducing the influence of noise superimposed on a signal.

Conventionally, in a multiplex recording device having multiple pens, since the other pens record at positions temporally advanced on the recording paper with respect to the first pen, a signal delaying means is inserted for each, and the recording by each pen is delayed. The trajectory is made so that there is no progress in time.

Such delay means are provided in each pen, and an example of the configuration of one set of delay means is shown in FIG.

In Fig. 1, an input signal is digitized by an analog-to-digital converter (hereinafter referred to as an AD converter) 1 every time a sample clock is applied, and after being delayed by a delay circuit 2 by a time N times the sample clock, the input signal is digitized. - Analog conversion is performed by an analog converter (hereinafter referred to as a DA converter) 3.

In this case, N is selected so that the delay time is equal to the time corresponding to the phase shift of each pen, and the sampling period is synchronously proportional to the paper feed speed, so that when the paper feed speed is slow, the sample interval becomes longer. It has become.

However, as shown in Figure 2A, the sampling period T, (second
(Figure 2) When noise with a shorter period is superimposed on the input signal, the output of the AD converter 1 not only does not show the average value of the input signal as shown in Figure 2 (C), but also may differ from the input signal in some cases. There was a drawback that the output signal fluctuated at different slow cycles and the recording waveform fluctuated.

The present invention aims to solve these drawbacks and realize a noise-cancelling delay circuit that can reduce errors based on sample calculation when noise with a period shorter than the sample period is superimposed on the input signal. It is.

The present invention will be explained in detail below using the drawings.

FIG. 3 is a block diagram showing an actual example of a noise-cancelling delay circuit according to the present invention, in which the average calculation circuit 31 is placed before the delay circuit 2, and the sample period of the AD converter 1 is the same as that of the delay circuit 2. It is the same as that in FIG. 1 except for the difference in period.

The average calculation circuit 31 samples the output of the AD converter 1 every time the sample clock CL2 as shown in the middle of FIG. It calculates and outputs the average of sample values.

The frequency f2 of the sample clock CL2 is selected to be sufficiently higher than the frequency f1 of the sample clock CL1.

In such a configuration, the highest frequency fn of noise superimposed on the input signal and the sample clock CL1°CI, ! The frequency f1. It is assumed that the following relationship exists between f2.

f n << f 2 f2=n' fl (where n is an integer) (1) AD
If the sample value of the input signal sampled by the converter 1 is ei, the average calculation circuit 31 calculates and outputs the average a of the sample values e· based on the following equation for each sample clock CL1.

As shown in FIG. 4, the average value row of the sample values has a value that is almost close to the average value of the input signal due to the effect of the average calculation.

Delay circuit 2 has a sampling period 1 that is proportionally synchronized with the paper feed speed.
The average values are delayed by one cycle of /f1.

The delayed average value is given as an input signal to a servo circuit (not shown) via the DA converter 3.

In this way, sample calculation errors caused by noise superimposed on the input signal can be reduced.

Note that the frequency f2 of the sample clock CL2 can be arbitrarily selected based on the relationship in equation (1). In this case, the average calculation circuit 31 is composed of a digital circuit, and the averaging process is performed by digital calculation. The constant n can be easily changed.

Further, the average calculation circuit and the delay circuit are not limited to the calculation processing performed by hardware as shown in the actual case, but may be made to perform calculation processing by software using a microprocessor or the like.

Furthermore, the delay circuit of the present invention can be applied not only to multiplex recording devices but also to other devices as appropriate.

As explained above, the noise-cancelling delay circuit of the present invention can easily reduce the sampling calculation error that occurs when noise with a period shorter than the sampling period is superimposed on the input signal, and is suitable for practical use. The effect is profound.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example of delay means for a phase-synchronous multiplexing recording device.
FIG. 2 is a time chart for explaining the operation of the means shown in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the noise elimination type delay circuit according to the present invention, and FIG. 4 is the circuit shown in FIG. 3. FIG. 2 is a time chart for explaining the operation of FIG.

Claims (1)

[Scope of utility model registration request] Multiple pens draw recording trajectories on recording paper that moves at a constant speed, each in response to a signal from a different channel, and input is made according to the arrangement of each pen so that the time axis of each pen's recording trajectory coincides. In a phase-locked multiplex recording device equipped with a delay circuit for delaying a signal, each pen is provided with an averaging circuit for averaging input signals sampled at a cycle shorter than the sampling cycle of the delay circuit, and A noise elimination type delay circuit, characterized in that an input signal is applied to the delay circuit via an arithmetic circuit.