JPS6348016A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To compress phase noise and to simplify the circuit form by supplying a switching pattern of a frequency division number stored in advance to a switching type frequency divider. CONSTITUTION:A reference signal generator 1 generating a required output signal, a voltage controlled oscillator 3, a switching frequency divider 4 frequency-dividing the output signal of the reference signal generator 1 and converting the frequency division number into a binary value, a circuit of a control system supplying the switching pattern having the frequency division number stored in advance to the switching frequency divider, a sampler 5 sampling an output signal of the voltage controlled oscillator 3 by the output signal of the reference signal generator 1 and a phase frequency detector 2 detecting a phase error of each output signal from the frequency divider 4 and the sampler 5, feeding back the error signal to the voltage controlled oscillator 3 negatively and revising the output signal frequency of the voltage controlled oscillator 3 are provided respectively. Since the control circuit has only to select a pattern in response to the required frequency, the output signal phase noise characteristic with simple circuit constitution and very excellent state is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an indirect frequency synthesizer, and more particularly to a frequency synthesizer with small frequency variable steps and good output phase noise characteristics.

[Conventional technology]

Conventionally, the circuit configuration shown in FIG. 2 is well known as an indirect frequency synthesizer configuration.

This frequency synthesizer divides the output signals f and l of the reference signal generator 11 by M using a fixed frequency divider 14, and divides the output signal r0 of the lightning pressure control oscillator 13 by a variable frequency whose frequency division number N can be varied. The frequency is divided by the divider 15, the frequency phase of both is compared by the phase frequency detector 12, and the obtained error signal is negatively fed back to the frequency control terminal of the voltage controlled oscillator 13, and the variable frequency divider 15
The output frequency of the voltage controlled oscillator is controlled by controlling the frequency division number N of f. = N/M - frequency step f according to fR
This occurs in R/M.

[Problem that the invention seeks to solve]

The above-mentioned conventional indirect frequency synthesizer has the advantage of simple configuration, but when the frequency step is made small, the comparison frequency of the phase frequency detector becomes low, and the loop bandwidth of the negative feedback loop generally needs to be smaller than the comparison frequency. As a result, the loop bandwidth of the negative feedback loop becomes smaller. Also, the output signal of the voltage controlled oscillator is frequency-divided by N and the phase frequency is compared, but this is equivalent to multiplying the phase comparison frequency f, I/M signal by N, and is proportional to the frequency division number N. It has problems such as deterioration of output phase noise.

In order to solve these problems, various proposals have been made, such as combining it with a direct synthesizer, but in all cases the circuit format is very complex and expensive.

[Means for solving problems]

The frequency synthesizer of the present invention makes it possible to compress phase noise while simplifying the circuit format.

The frequency synthesizer of the present invention includes a reference signal generator and a voltage controlled oscillator that generate respective required output signals, and a switchable frequency synthesizer that divides the output signal of the reference signal oscillator and can change the frequency division number into two values. a frequency divider, a control system circuit that supplies a pre-stored frequency division number switching pattern to the switching type frequency divider, and a sampler that samples the output signal of the voltage controlled oscillator using the output signal of the reference signal generator. , a phase frequency detector capable of detecting a phase error between each output signal of the switching frequency divider and the sampler, feeding back this error signal negatively to the voltage controlled oscillator, and changing the output signal frequency of the voltage controlled oscillator. The structure is equipped with the following.

Here, the switching frequency divider divides the output signal of the reference signal generator according to the pulse pattern output from the control system circuit, and the control system circuit stores in advance the pulse pattern of the output signal of the sampler. a data storage circuit for setting the pulse pattern to the switching frequency divider in synchronization with the output signal of the switching frequency divider, a parallel/serial data converter for sending this pulse pattern to the switching frequency divider in synchronization with the output signal of the switching frequency divider, and a and a control circuit that selects frequency division number switching data for the data storage circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. In the figure, this frequency synthesizer includes a reference signal generator 1 and a voltage controlled oscillator 3, each of which generates a required output signal, and divides the output signal of the reference signal oscillator 1, and changes the frequency division number into a binary value. A switchable frequency divider 4 that can
a control system circuit that supplies a pre-stored frequency division number switching pattern to the switching frequency divider; a sampler 5 that samples the output signal of the voltage controlled oscillator 3 using the output signal of the reference signal generator 1; Phase frequency detection capable of detecting the phase error of each output signal of the switching frequency divider 4 and the sampler 5, feeding back this error signal negatively to the voltage controlled oscillator 3, and changing the output signal frequency of the voltage controlled oscillator 3. It is equipped with a container 2.

Further, the control system circuit includes a data storage circuit 7 that stores in advance the pulse pattern of the output signal of the sampler 5;
A parallel/serial data converter 6 sends this pulse pattern to the switching frequency divider in synchronization with the output signal of the switching frequency divider, and a data storage circuit 7 is used to set the output signal of the voltage controlled oscillator 3. It is composed of a control circuit 8 that selects frequency switching data.

Here, it is assumed that the reference signal generator 1 outputs a signal with a frequency fR, and the voltage controlled oscillator 3 outputs a signal with a frequency fo.

In the sampler 5, the output signal f of the reference signal generator 1 is
The output signal f0 of the voltage controlled oscillator 3 is sampled at R.

This sampler uses a D flip-flop,
Therefore, when the output signal fo of the voltage controlled oscillator 3 is supplied to the D input and the output signal fR of the reference signal generator 1 is supplied to the clock input, the output terminal Q of the sampler is supplied with a signal having a frequency that satisfies the following relational expression. f0 is obtained.

However, fo>fR9m is a positive integer.

゛The connection is with Motorola's MOTOROLA MEC.
rMC12000DIG of L DEVICE DATA
This is illustrated using a diagram in the device description of ITAL MIXERJ. However, since this output signal r0 is essentially sampled at fR, its period is 1/
f is a multiple of R, and the time of one cycle is 1 / f except for frequencies where f, 1 = pfa (p is a positive integer)
Instead of o, the period in the long-term average is simply 1/f0. That is, when the above equation holds in the same period of A of fo, the output signal f0 can be considered as follows. During a certain long cycle, the period of (pi)fo is n cycles/f R is cycled (A-n), so fo is equal to fR/(p-1) and f
*/p, and the average frequency in the A cycle of fo satisfies the above equation (1) according to the probability of its appearance.

The period of the A cycle is expressed as A/fo=n(p1)/f*+(An)p/fR...(3). From this, as the average frequency, fo = A
fo / (Ap n) - (4) is obtained. The order in which fR/(p-1) and fat/p appear is uniquely determined when fo and fR are determined, and can be determined by calculation. Furthermore, p is, on the other hand, the reference signal generator 1
The output signal fR of is supplied to the switching frequency divider 4. The switching type frequency divider 4 operates to switch the frequency division numbers p-1 and 2 (U of p) by the 1 and 0 signals inputted to the frequency division number switching terminal.

Next, the operation of this switching signal will be described.

First, p-1 and p calculated from the relationship between the required output frequency of the voltage controlled oscillator 3 and the output frequency of the reference signal generator 1.
The control circuit 8 selects which switching pattern to use from the data storage circuit 7 which stores in advance several types of patterns over the frame length A in the order of appearance.

The switching pattern signal over the selected frame length A is
Input to parallel/serial data converter 6 and switchable frequency divider 4
It is input as a 1.0 signal in parallel, that is, in time series, to the frequency division number switching terminal of . p- input to this frequency division switching terminal
The signal patterned with the appearance order of Lp as a 1.0 signal is synchronized so that it is input to the frequency division number switching terminal of the switchable frequency divider 4 every cycle of the output signal of the switchable frequency divider 4. In order to perform the required frequency division based on the operating conditions of the switching frequency divider, it is necessary to hold the input signal to the frequency division number switching terminal for the setup time before starting frequency division. .

In the present invention, regarding this point, the output signal of the switching type frequency divider 4 is used as a synchronizing signal for outputting the data of the parallel/serial data converter 6. It is input as a synchronization signal to the synchronization signal input terminal of the parallel/serial data converter 6. From this, the parallel output data of the parallel/serial data converter 6 is delayed in total by the set/assign time of the parallel/serial data converter 6 with respect to the output signal of the switching type frequency divider 4. Can be synchronized.

That is, since the setup time of the switching frequency divider 4 is generally sufficiently shorter than one cycle of the output frequency divided signal, the switching frequency divider 4 converts the parallel-to-serial data converter using a pulse one cycle before the output signal. The frequency division number switching data outputted by 6 is input to the frequency division number switching terminal, the held data is read, and the next frequency division is started. Since the output data of the parallel/serial data converter 6 is synchronized with the output signal of the switching type frequency divider 4, the output data of the switching type frequency divider 4 and the output data of the parallel/serial data converter 6 are synchronized. is definitely 1:1
It will be supported.

The output signal of the reference signal generator 1 can be frequency-divided by the parallel-to-serial converter 6 repeatedly sending a switching pattern of frame length A according to the switching pattern of the data storage circuit 7.

What is the control of the output signal of the switching type frequency divider mentioned above? 1 is a major feature of this embodiment.

From the above, the output signal f of the voltage controlled oscillator 3 mentioned above. When is the required frequency, the output signal f0 of the sampler 5
f++/p appearing in 1. A matching order of appearance of f*/p is produced by the switched frequency divider 4.

Next, the output signal of the switching type frequency divider 4 and the output signal of the sampler 5 are supplied to the phase frequency detector 2, and the phase and frequency of the two are compared. For comparison, retiming is applied to the output signal of the sampler 5 and the output signal of the switching type frequency divider 4 as necessary, so that the phases of both signals accurately match the timing of the reference signal of the reference signal generator 1.

The output detection error signal of the phase frequency comparator 2 is negatively fed back to the frequency control terminal of the voltage controlled oscillator 3.
to stabilize the output frequency to the required frequency. frequency f0
From equations (1), (4), and (5), if f0≦(m+1/2)r*, then fo = (m+A/ (Ap+n))fx ・”
(6) If ro≧(m21/2) r, l, then f(1-(m+ L A/ (Ap n))
f++ −B).

Now let's give the actual values.

m=3. A=167, n=1. fm=50MH
z, p=23 and fo=166.7 M
Hz.

Next, m=3. A=168, n=4.
f R = 50MH2, p = 3, f o
=166.8 MHz.

Furthermore, m=3. A=169, n=7. fm=50M
In FI2, p=3. fo = 166.9 MH2, and if we increase A by 1 and n by 3 in this way, 1
A frequency synthesizer with 00KH2 steps can be constructed. That is, it is sufficient to prepare p-1 and p switching patterns corresponding to one frequency step.

Next, the initial M value of fo is fixed by appropriately selecting the oscillation frequency range of the voltage controlled oscillator 3, or is superimposed on the output signal of the phase frequency detector 2 at the frequency control terminal of the voltage controlled oscillator 3. It can be fixed by supplying a separately prepared voltage.

When the output signal f0 of the voltage controlled oscillator 3 is stabilized, the output signal of the sampler 5 and the output signal of the switching type frequency divider 4, both of which are supplied to the phase frequency detector 2, have very low frequency components. However, there is always no phase difference between the two signals, and no low frequency component appears in the output detection error signal of the phase frequency detector 2, and the output detection error signal becomes completely zero.

However, the phase detection accuracy of the phase frequency detector 2 is higher than that of the sampler 5.
approximately f0/f+tx2π
Since the unit is rad, fR is required to obtain sufficient detection accuracy.
>) must be fo.

The output frequency is set by selecting the switching pattern of p-1 and p stored in advance by the control circuit 8 in accordance with the frequency value manually input to the control circuit 8. Ru.

〔Effect of the invention〕

As explained above, in the present invention, the phase frequency comparison frequency does not become smaller than f*/p, so if p is appropriately selected, the phase comparison frequency can be set to a high value.

Therefore, it is possible to widen the loop bandwidth of the phase-locked loop within a range not exceeding fR/p, and as a result, it is possible to sufficiently compress the phase noise of the voltage controlled oscillator. Additionally, since a sampler is used and the output signal frequency of the voltage controlled oscillator is replaced with a lower frequency by frequency conversion rather than frequency division, the phase noise characteristics do not deteriorate due to frequency division as in conventional frequency synthesizers. , even if you configure a frequency synthesizer with small frequency variable steps,
A frequency synthesizer with good phase noise characteristics can be provided. Furthermore, the switching data given to the switching frequency divider is simple because all patterns for the frequency band to be used are stored in advance, so the control 4111 circuit only has to select the pattern according to the required frequency. Very good output signal phase noise characteristics can be obtained with the circuit configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 2 is a conventional circuit configuration diagram. 1... Reference signal oscillator, 2... Phase frequency detector,
3... Voltage controlled oscillator, 4... Switchable frequency divider, 5...
... Sampler, 6... Parallel/serial data converter, 7.
...Data storage circuit, 8...Control circuit, 11...Reference signal generator, 12...Phase frequency detector, 13...
・Voltage controlled oscillator, 14...Fixed frequency divider, 15...
Variable frequency divider. Figure 1 Figure 2

Claims (2)

[Claims] (1) a reference signal generator and a voltage controlled oscillator that generate respective required output signals, and a switchable frequency divider that divides the output signal of the reference signal oscillator and can change the frequency division number to binary; a control system circuit that supplies a pre-stored frequency division number switching pattern to the switchable frequency divider; a sampler that samples the output signal of the voltage controlled oscillator using the output signal of the reference signal generator; and the switchable frequency divider. and a phase frequency detector capable of detecting a phase error between each output signal of the frequency divider and the sampler, feeding back this error signal negatively to the voltage controlled oscillator, and changing the output signal frequency of the voltage controlled oscillator. frequency synthesizer. (2) The switching type frequency divider divides the output signal of the reference signal generator according to the pulse pattern output from the control system circuit, and the control system circuit stores in advance the pulse pattern of the output signal of the sampler. a data storage circuit for setting the pulse pattern to the switching frequency divider in synchronization with the output signal of the switching frequency divider, a parallel/serial data converter for sending this pulse pattern to the switching frequency divider in synchronization with the output signal of the switching frequency divider, and a 2. The frequency synthesizer according to claim 1, further comprising a control circuit for selecting frequency division number switching data of the data storage circuit.