JPH0653952A - 576khz clock generation circuit - Google Patents

Abstract

PURPOSE:To provide a small-sized 576kHz clock generation circuit with high reliability by constituting the clock generation circuit with a digital circuit relating to a circuit for generating 576kHz clocks by frequency-dividing the clocks of a frequency 19.44MHz. CONSTITUTION:This circuit is provided with a frequency divider circuit 10 for 33-frequency dividing and 34-frequency dividing the clocks of the frequency 19.44MHz and a control circuit 20 for synchronizing with 8kHz frame pulses and controlling the frequency dividing operation of the frequency divider circuit 10. Then, the 576kHz clocks synchronized with the 8kHz frame pulses are generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a frequency of 19.44 MHz.
The present invention relates to a circuit that divides the clock of 1 to generate a clock of 576 kHz.

In the new synchronous network, a clock of 155.52 MHz is used as a basis, and a frequency of 19.44 MHz, 576 kH.
Various clocks such as z are used. Further, the frame pulse generally uses a clock of 8 kHz, and it is required that the frame pulse is a clock signal synchronized with the 8 kHz frame pulse.

There is a demand for a 576 kHz clock generation circuit having a small circuit scale, which stably generates such a 576 kHz clock in synchronization with an 8 kHz frame pulse.

[0004]

2. Description of the Related Art FIG. 5 shows a block diagram for explaining a conventional example. The figure shows an example in which a phase locked loop (hereinafter referred to as PLL) is used as a 576 kHz clock generation circuit. In the figure, 30 and 70 are frequency dividers, 40 is a phase comparator, 50 is a low-pass filter, and 60 is a voltage. It is a controlled oscillator.

In the figure, the frequency divider 30 is divided by the phase comparator 40.
And the phase of the output from the frequency divider 70 are compared, and the difference output is applied as a control voltage of the voltage controlled oscillator 60 through the low pass filter 50 so that the phase comparator 40 eliminates the phase difference. By operating in 19.4
A 576 kHz clock is generated from the 4 MHz clock.

[0006]

In the conventional example using the above-mentioned PLL, it is difficult to reduce the size because there is an analog circuit such as a low-pass filter in the configuration. Further, since an analog circuit is used, the frequency may change due to fluctuations in power supply voltage, fluctuations in ambient temperature, and the like.

The present invention intends to realize a compact and highly reliable 576 kHz clock generation circuit by configuring the clock generation circuit entirely by digital circuits.

[0008]

FIG. 1 is a block diagram for explaining the principle of the present invention. 100 in the figure is a frequency of 19.
A 576 kHz clock generation circuit that divides a 44 MHz clock to generate a frequency 576 kHz clock, 10 is a division circuit that divides the frequency 19.44 MHz clock by 33 and 34, and 20 is synchronized with an 8 kHz frame pulse. The control circuit controls the frequency dividing operation of the frequency dividing circuit 10, and generates a 576 kHz clock synchronized with the 8 kHz frame pulse.

[0009]

When the 19.44 MHz clock is divided by 33.75, a 576 kHz clock can be obtained. 33.
The frequency division of 75 can be realized by performing frequency division of 33 once and frequency division of 34 three times.

Here, the 8 kHz frame pulse is 19.
Since it is 1/2430 of the 44 MHz clock, 2430 = (33 + 34 × 3) × 18 That is, the frequency division operation is performed 18 times by combining the frequency division of 33 of the 19.44 MHz clock once and the frequency division of 34. Results in 8 kHz.

Therefore, by synchronizing this operation with the 8 kHz frame pulse, the 5
A 76 kHz clock can be generated. Also, 8
When the kHz frame pulse is not input, the frequency divider circuit 10 is self-synchronized by the outputs of the counters 21 and 22 to generate a 576 kHz clock synchronized with 19.44 MHz in a cycle of 8 kHz.

[0012]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
The counters 11 and 12 and the OR circuits 13 and 14 in FIG.
The control circuit 20 is composed of 3, 24.

When an 8 kHz frame pulse is input,
The 8 kHz frame pulse is input to the load terminals L of the counters 11 and 12 through the OR circuit 14 and becomes a load signal to load the initial value.

At this time, the 8 kHz frame pulse is ORed.
Since it is input to the input terminal DA of the counter 11 through the circuit 13, the input becomes "1", and the counters 11 and 1
“DF” is loaded in 2.

When the 19.44 MHz clock is counted up to "FF" by "33" from this state, the carry-out CO is output from the counter 12 and self-loading is performed by this signal. At this time, since the 8 kHz frame pulse is not input, the input of the input terminal DA of the counter 11 becomes “0”, and the counters 11 and 12 are loaded with “DE”.

When counting "34" from this state to "FF", the carry-out CO is output from the counter 12. On the other hand, the counter 21 outputs “1” through the AND circuits 23 and 24 once every four counts by counting the carry-out CO of the counter 12 after “0” is loaded by the 8 kHz frame pulse. Then, the load values of the counters 11 and 12 are set to "DF".

By this operation, the frequency division of 33 and the frequency division of 34 are made 1
The output of QA of the counter 12 is output through an inverter (hereinafter, referred to as INV) 15 by taking out the inverted output, and a 576 kHz clock synchronized with the 8 kHz frame pulse can be output. .

FIG. 3 is a diagram for explaining another embodiment of the present invention. 3 is configured by adding a counter 22, an OR circuit 25, and AND circuits 26 and 27 to the configuration of FIG. In the configuration shown in FIG. 3, “DF” is loaded into the counters 11 and 12 by the 8 kHz frame pulse, and “3” is loaded.
3 "is counted," 34 "is counted the next 3 times," 33 "is counted once every 4 times, and this operation is repeated in the same manner as described with reference to FIG.

Here, it is assumed that the 8 kHz frame pulse is no longer input after the operation is started by being initialized by the 8 kHz frame pulse. The counters 21 and 22 count the carry-out CO of the counter 12,
When the count (actually 72 counts from 0 to 71) is reached, "1" is output from the AND circuit 26, and this "1" is passed through the AND circuit 27 to the counter 1
The load signal is input to 1, 12, 21, and 22 and the load value of the counter 11 at that time is set to "DF" to perform self-loading.

After that, once every four times thereafter, "33" is counted,
By counting "34" 3 times in 4 times, 1
A 576 kHz clock can be generated from the 9.44 MHz clock.

FIG. 4 shows a time chart of the embodiment of the present invention. The operation will be described below with reference to a time chart. 8
8 kHz frame pulse 8 input every 125 μS
A kHz frame pulse is shown.

CO of counter 12 The output timing of the carry-out CO of the counter 12 is shown. It is initialized by an 8 kHz frame pulse, the carry-out CO is output at the first "33" count, and the "34" count at the next three times. The carry-out CO is output by and this operation is repeated thereafter.

Outputs of counters 21 and 22 Counter 2
The output of 1 and 22 is shown in hexadecimal, and "00"
To "47 (decimal 71)" are repeated 72 times.

The output of the AND circuit 23, which is output once every four times. Indicates the self-load signal output from the AND circuit 27, 8
Even if the kHz frame pulse is not input, the self-loading is performed by this signal and the operation is continued.

A to M are enlarged views of the above time axis. A shows a 19.44 MHz clock. B shows a 8 kHz frame pulse.

C to F Output Q of counter 11 which counts up after being initialized by 8 kHz frame pulse
A to QD are shown. The outputs QA and QB of the counter 12 that counts up after being initialized by the G to H 8 kHz frame pulse are shown.

The carry-out CO of the I counter 12 is shown. With this signal, the counters 11 and 12 are loaded with initial values. The hexadecimal output of the J counters 21 and 22 is shown.

The output of the K AND circuit 23 is shown. (The same as above.) The output of the L AND circuit 27 is shown. (The same as the above.) The output QA of the M counter 12 is an output obtained by inverting the output QA by the INV 15, and the clock is 576 kHz.

[0029]

According to the present invention, by controlling the initial value of the frequency dividing counter, the 33 frequency division and the 34 frequency division are 1: 3.
Since it is executed at a rate of 576 kHz, the jitter is leveled.
A z clock generation circuit can be realized.

Further, since all the circuits are digitized, the analog circuit such as the low-pass filter as shown in the conventional example is eliminated and the size can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram for explaining another embodiment of the present invention.

FIG. 4 is a time chart of an example of the present invention.

FIG. 5 is a block diagram illustrating a conventional example.

[Explanation of symbols]

 576 kHz clock generation circuit 10 frequency divider circuit 11, 12, 21, 22 counter 13, 14, 25 OR circuit 15 inverter 20 control circuit 23, 24, 26, 27 AND circuit 30, 70 frequency divider 40 phase comparator 50 low band Filter 60 Voltage controlled oscillator

Claims (2)

[Claims] 1. A 576k which divides a frequency of 19.44MHz clock to generate a frequency of 576kHz clock.
A Hz clock generation circuit (100) for dividing a frequency of 19.44 MHz clock by 33 and
The frequency dividing circuit (10) for frequency division and the frequency dividing circuit (1
And a control circuit (20) for controlling the frequency dividing operation of 0), and generating a 576 kHz clock synchronized with an 8 kHz frame pulse. 2. The 576 kHz clock generation circuit (100) according to the preceding paragraph, wherein counters (21, 22) for counting the number of operations of the frequency dividing circuit (10) are provided, and when the 8 kHz frame pulse is not input, By the output of the counters (21, 22), the frequency dividing circuit (10) is self-synchronized, and the frequency is 19.44 M at 8 kHz cycle.
The 576 kHz clock generation circuit according to claim 1, wherein the 576 kHz clock is generated in synchronization with the Hz clock.