JPH02243021A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain an oscillation circuit whose time required for lock is reduced with simple constitution by switching a frequency division ratio in a prescribed order sequentially and driving the oscillator based on a frequency division signal to be obtained. CONSTITUTION:A frequency divider 22 initializes the frequency division operation with a reset signal SRST and its frequency division ratio is switched in response to a control signal SC. A counter circuit 23 counts a frequency division signal SREFFS and outputs the count obtained as a result to a memory circuit 25 as an address data DR. The circuit 25 outputs the signal SC based on the data DR to switch the frequency division ratio of the frequency divider 22 in a prescribed order sequentially. An oscillation circuit 21 comprising a phase comparator 31, a VCO 32 and a frequency divider 33 outputs an output signal SFS with a prescribed frequency based on the signal SREFFS. Thus, the oscillation circuit whose time required for lock is reduced with simple constitution is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an oscillation circuit. For example, the present invention relates to an oscillation circuit for a clock signal in a video tape recorder that converts an audio signal together with a video signal into a digital signal and records the same. Applicable and Preferred Outline of the Invention The present invention has a simple structure and reduces the locking time by driving an oscillator in an oscillator circuit based on a frequency-divided signal obtained by switching frequency division ratios in a predetermined order. time can be shortened.

C. Prior Art Conventionally, in a video tape recorder that converts an audio signal into a digital signal together with a video signal and records the same, a clock signal is generated based on the video signal, and the clock signal is used to convert the audio signal into a digital signal. The signal is sampled and predetermined signal processing is performed.

In other words, as shown in FIG. 4, in a video tape recorder configured to record a PAL video signal, the oscillation circuit 1 generates a subcarrier signal of the video signal (that is, the frequency is 4.43361875CM&). Reference signal S avsc with four times the frequency
is applied to the frequency divider 2.

The frequency divider 2 divides the reference signal S, .

Here, the reference signal S4□. Frequency of 17734475
(Hz), the frequency of the clock signal S is 48
[k7], so the relationship of the following formula % formula % holds true, and the frequency of the reference signal S□2 is 25 [翫]
is the greatest common divisor of the frequencies of the reference signal S4□0 and the clock signal srs.

On the other hand, the phase comparator 3 is a voltage controlled oscillator (VC
O) 4, PLL (phase
1ocked 1oop) circuit, and generates the clock signal SF3 using the reference signal s2r as a reference.

That is, the phase comparator 3 receives the output signal SCO of the frequency divider 6.
The phase comparison result of MF and the reference signal S@IF is output to the voltage controlled oscillator 4, and thereby the frequency of the clock signal SFS is changed from the voltage controlled oscillator 4 to F.

The oscillation output signal s osc has a frequency of 384 F.
It is made to obtain.

On the other hand, the frequency divider 5 divides the oscillation output signal s osc into 1
The frequency is divided by /384 and output, thereby obtaining a clock signal srs of frequency Fs (48 (kHz)).

Furthermore, the frequency divider 6 divides the clock signal srs into 1/1920.
Comparison signal S C0III with frequency divided and frequency 25 (Hz)
F, thereby generating a comparison signal SCO
□ is the reference signal S II! The voltage controlled oscillator 4 is controlled to lock to the reference signal S4□. A clock signal srs locked to the clock signal srs can be obtained.

In this way, in the oscillation circuit 1, in order to generate the clock signal Srs locked to the reference signal 34FIC, the clock signal sy
s.

Furthermore, in this type of oscillation circuit 1, it is necessary to lock the clock signal srs to the vertical synchronization signal as well.

For this reason, in the frequency dividers 2 and 6, the frequency dividing operation can be initialized with a reset signal SRI synchronized with the vertical synchronization signal, thereby obtaining the clock signal S0 locked to the vertical synchronization signal. There is.

Problems to be Solved by the Invention By the way, in the configuration of FIG. 4, the reference signal 34F$1e and the comparison signal S, each having a frequency of 25. Since the clock signal srs is generated based on the phase comparison result of □, the clock signal srs is the reference signal S4□. There is a problem in that it takes time to lock the device.

As one method for solving this problem, an oscillation circuit 10 having a configuration as shown in FIG. 5, for example, can be considered.

That is, the horizontal synchronization signal Sw (frequency 15.625 (k
7]) to the frequency divider 11 to generate a first reference signal S□ with a frequency of 2.25(k)tz) divided by 175.

The phase comparator 12 includes a voltage controlled oscillator 13 and a frequency divider 14.
The first PLL circuit is configured together with the first PLL circuit.
The first oscillation output signal 5o is based on the reference signal S□□ of
sc+.

That is, the frequency divider 14 outputs the first oscillation output signal 5osc+
The frequency is divided by 1/(144x32), so that the following relationship holds true for the first PLL circuit, and the frequency is 14.4 (MH
z) first oscillation output signal SO3:l as the horizontal synchronization signal 8
．． Lock it to 4.

On the other hand, the frequency divider 15 outputs the first oscillation output signal 5os
Divide c+ by 1/125 to obtain a frequency of 115.2 (kHz
) second reference signal S□. generate.

The phase comparator 16 constitutes a second PLL circuit together with a voltage controlled oscillator 17 and a frequency divider 17, and
The second oscillation output signal 5o is based on the reference signal S□□ of
sct.

That is, the frequency divider 18 outputs the second oscillation output signal s osc
t is frequency-divided by 1/160, so that the following relationship (3) holds true for the second PLL circuit.

As a result, the frequency of 384×48 (
k) Lock the second oscillation output signal SO3° of tz) to the horizontal synchronization signal SN.

On the other hand, the frequency divider 20 outputs the second oscillation output signal S 0
The frequency of mC1 is divided by 1/384 and outputted, and as a result, the reference signal 34WSC is output via the horizontal synchronization signal S8.
A clock signal srs locked to the clock signal srs is obtained.

Furthermore, the frequency divider 20, together with the frequency divider 15.18, receives a reset signal S. ? The frequency division operation can be initialized by the clock signal SFI, thereby synchronizing the clock signal SFI with the vertical synchronization signal.

Thus, according to the configuration shown in FIG. 5, compared to the configuration shown in FIG. 4, since the frequencies of the first and second reference signals 5ittr+ and S□r for phase comparison are higher, the time required for locking is reduced. Can be shortened.

However, since the oscillation circuit 10 uses a two-stage PLL circuit, there is a problem that the overall configuration becomes complicated.

The present invention has been made in consideration of the above points, and aims to propose an oscillation circuit that has a simple configuration and can shorten the time required for locking.

E Means for Solving the Problem In order to solve this problem, in the present invention, the input signal 34FIC is frequency-divided to generate the frequency-divided signal S II! A control circuit 2 that switches the frequency division ratio of the frequency divider 22 in a predetermined order based on the frequency divider 22 that outputs FFI and the frequency division signal S□□.
3.25 and the frequency divided signal S 1111! FF! oscillators 31, 32, and 33 that output an output signal srs of a predetermined frequency F3 based on .

The frequency division ratio of the F-action frequency divider 22 is switched in a predetermined order, and the predetermined frequency F is set based on the resulting frequency-divided signal Sat□3.
By outputting the output signal S0 of , the time required for locking can be shortened with a simple configuration.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, 21 indicates an oscillation circuit as a whole, which supplies a frequency divider 22 with a reference signal s arsc having a frequency four times that of the subcarrier signal of the video signal.

As shown in FIG. 2, the frequency divider 22 receives a reset signal S,
7 initializes the frequency division operation and switches the frequency division ratio according to the control signal S, thereby dividing the reference signal 5aysc (FIG. 2(A)) by 17369 or by 1.
/370 divided signal 311! □3 (Figure 2 (B)
) is output.

On the other hand, the counter circuit 23 is configured to count the frequency-divided signal S□□ at 1920 cycles, and stores the resulting count value in the memory circuit 25 as address data D.
It is designed to be output as one.

The memory circuit 25 is composed of a read-only memory (ROM), and is configured to sequentially switch the frequency division ratio of the frequency divider 22 in a predetermined order by outputting a control signal S based on address data D. ing.

That is, the frequency of the reference signal Savsc is 1773447
5 (Se) is the frequency 4B (kH) of the clock signal S□
z) (FIG. 2(C)), the following equation holds.

Therefore, the reference signal 34Fle is divided by 1/369 or 1/3.
It is not possible to obtain the clock signal srs with a frequency of 48 (kHz) only by dividing the frequency by 70, and in this case, the frequency-divided signal S
l! FF! causes a deviation ΔT with respect to the period of the clock signal srs.

Therefore, in this embodiment, the frequency division ratio of the frequency divider 22 is set to 1.
By switching between /369 frequency division and 1/370 frequency division in a predetermined order, the deviation ΔT becomes the reference signal S4□. No. 1
/2 clock cycle, thereby creating a frequency-divided signal S□21. with a frequency of 4B (kHz) and a slightly fluctuating cycle. generate.

That is, let the count value of the counter circuit 23 be n,
Solving the relational expression of the following formula % formula %, when the value below the decimal point is less than 0.5,
Continuation (When the frequency division ratio of the frequency divider 22 is selected as 369 division in the frequency division operation, and the value below the decimal point is 0.5 or more, the frequency division ratio of the frequency divider 22 is selected as 370 in the subsequent frequency division operation) Selected by Zhou.

As a result, the frequency division ratio can be changed in the order shown in FIG.

Thus, since the greatest common divisor of the frequency 17734475 (7) and the frequency 48 (k&) is the value 25,
The frequency dividing ratio is changed so that it circulates at a cycle of 25 [7], and the frequency divided signal Sml! of frequency 48 (kHz) is generated. FFfi can be generated.

On the other hand, the phase comparator 31 is connected to the voltage controlled oscillator 32.
, and a frequency divider 33 to form a PLL circuit, and generate a clock signal sea based on the frequency-divided signals S□, .

That is, the frequency divider 33 divides the oscillation output signal 5osca of the voltage controlled oscillator 32 having a frequency of 384 Fm into 173
The frequency is divided by 84 to generate the clock signal S0, and the clock signal S0 is output to the phase comparator 31, thereby directly controlling the voltage controlled oscillator 32 based on the phase comparison result of the clock signal S0. There is.

Therefore, by comparing the phases at a higher frequency than in the configuration shown in FIG. 4, the time required for locking can be shortened.

Furthermore, since it can be configured with a single stage PLL circuit, the overall configuration can be simplified compared to the configuration shown in FIG.

Incidentally, the frequency divided signal SIEFF! In this case, there is a possibility that jitter may occur in the clock signal srs since the period fluctuates minutely.

However, the periodic fluctuation of the frequency-divided signals S, E□ itself is the reference signal 34F! The fluctuation is minute, less than 1/2 clock cycle of e, and furthermore, in this embodiment, a flywheel effect of the PLL circuit can be expected, and a clock signal S0 with sufficient accuracy for practical use can be obtained.

Incidentally, in the conventional oscillation circuit 1 or 10, it is necessary to initialize the frequency divider 2.6 and 15.18.20 at the same time using the reset signal smst, and if there is jitter in the reference signal sapse or Sn, it will be detected. There is a risk that the timing of initialization may be different between the clocks, making it difficult to synchronize, or that the cycle of the clock signal srs is thick (fluctuations) at the time of initialization.

However, in this embodiment, since it is only necessary to initialize the frequency divider 22, synchronization with the vertical synchronization signal can be performed easily and reliably, and the clock signal S□ can be reliably locked immediately after initialization. be able to.

Thus, in this embodiment, the counter circuit 23 and the memory circuit 25 output the divided signal S II! A control circuit is configured to switch the frequency division ratio of the frequency divider 22 in a predetermined order based on the FF3, whereas the phase comparator 31, voltage controlled oscillator 32, and frequency divider 33 switch the frequency division ratio of the frequency divider 22 in a predetermined order. □21. An oscillator that outputs an output signal SFl of a predetermined frequency is configured based on the oscillator.

According to the above configuration, by switching the frequency division ratio of the frequency divider 22 in a predetermined order and driving the oscillators 31, 32, and 33 based on the resulting frequency division signal S□□,
It is possible to obtain an oscillation circuit with a simple configuration and shortening the time required for locking.

In the above-described embodiments, the present invention is applied to an oscillation circuit of a video tape recorder configured to record video signals of the PAL system, but the present invention is not limited to this. It may also be applied to a video tape recorder adapted to record video signals.

Furthermore, in the above-described embodiment, a case was described in which a clock signal for audio signal processing was generated. However, the present invention is not limited to this. In short, if the frequency division ratio is selected as an integer ratio,
It can be widely applied to cases where the frequency of phase comparison becomes low.

Effects of the Invention As described above, according to the present invention, the time required for locking can be reduced with a simple configuration by driving the oscillator based on the divided signal obtained by sequentially switching the dividing ratio in a predetermined order. It is possible to obtain an oscillation circuit with a shortened .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an oscillation circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, FIG. 3 is a chart showing switching of the frequency division ratio, and FIGS. FIG. 5 is a block diagram showing a conventional oscillation circuit. 1.10.21...Oscillation circuit, 2.5.6.1
1.14.15.18.20.22.33...
Frequency divider, 3.12.16.31... Phase comparator, 4.13.17.32... Voltage controlled oscillator, 23... Counter circuit, 25 ...Memory circuit.

Claims (1)

[Claims] A frequency divider that divides an input signal and outputs a frequency-divided signal; and a control circuit that switches a frequency division ratio of the frequency divider in a predetermined order based on the frequency-divided signal. and an oscillator that outputs an output signal of a predetermined frequency based on the frequency-divided signal.