JPS6014525B2 - digital phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase synchronization circuit that generates an output signal that is phase synchronized with an input pulse signal.

A digital phase-locked loop (hereinafter referred to as DPLL) is a conventional circuit for performing phase locking, and a typical circuit configuration example thereof is shown in FIG.

In FIG. 1, 11 is an input signal line, 12 is a signal line for inputting the timing signal output from the timing extraction circuit 21 to the phase comparator 22, and 13 is for inputting the output from the frequency divider 26 to the phase comparator 22. 23 is a quantization circuit, 24 is a loop filter, 25 is a pulse addition/removal circuit, 27 is an oscillator that oscillates at a constant frequency, and 28 is an output signal line. When the input signal from the input signal line 11 contains various components, a timing extraction circuit 21 is provided to extract only the basic components necessary for the DPLL, and the output timing signal is connected to the signal line 12 to the phase comparator 22. However, if the input signal is only a basic component, the timing extraction circuit 21 is not necessary. As is well known, this timing signal is typically a single frequency square wave.
(Depending on the performance of the phase comparator 22, it may be a sawtooth wave or the like, but in DPLL it is mostly a rectangular wave.) This timing signal and the signal obtained from the frequency divider 26 (internal clock) are connected to the signal line. The signals are input to the phase comparator 22 via 12 and 13, and their phase differences are compared. The compared phase difference is given to the quantization circuit 23 and converted into binary values of 1 and -1, and the output thereof is accumulated in the loop filter 24.
When the accumulated value exceeds a certain value, the loop filter 24 outputs an output, and the output is sent to the pulse addition/removal circuit 25.
A pulse is added to or removed from the output pulse of the oscillator 27 in a direction that reduces the phase difference given to the frequency divider 26.
given to. The frequency divider 26 divides the frequency of the output pulse of the oscillator 27 obtained through the pulse addition/removal circuit 25 and supplies it to the phase comparator 22 (feedback) as described above, and also sends the input pulse signal (and A signal that is phase-synchronized with the timing signal) can be obtained. In other words, it compares the phase of the timing signal and the internal clock, quantizes the phase difference, and digitally controls the phase of the internal clock.
It is designed to obtain an output signal that is phase-synchronized with the timing signal, and DPLLs with configurations other than those shown in FIG. 1 have basically the same configuration. Such a dependent circuit configuration requires circuits such as the phase comparator 22 and the quantization circuit 23 as described above, and has the drawback that the circuit configuration is complicated, and therefore, the scale is large and expensive. In addition to DPLL, phase-locked circuits can be roughly divided into analog phase-locked circuits (A
However, DPLL has more stable characteristics, does not require adjustment, and is suitable for IC implementation, so it has been widely used in various communication technology fields in recent years.

In order to solve these drawbacks, the present invention realizes a digital phase synchronization circuit with an extremely simple circuit configuration based on directly controlling a frequency divider with an input pulse signal, and will be described in detail below.

FIG. 2 shows the basic circuit configuration of the present invention. 11 is an input signal line; 27 is an oscillator that oscillates at a constant frequency; 240 is a filter; 260' is a frequency divider with an initial setting terminal (hereinafter referred to as a divider).

Basically, the point of significant change in the input pulse signal from the input signal line 11 (for example, in the case of NRZ code, the point of change of the pulse from 0 to 1 or from 1 to 0) The change point) is detected by the change point detection circuit 30, and the output thereof is applied to a frequency divider 26 which divides the frequency of the clock pulse (internal clock) oscillated from the oscillator 27, thereby controlling the signal output from the divided period 260. This outputs a signal that is phase synchronized (hereinafter simply referred to as synchronization) with the input pulse signal.

Note that the filter 24 is shown as a broken line because it is used to prevent synchronization from becoming unstable when noise is introduced into the input pulse signal, and is not essential for phase synchronization operation.
FIGS. 3 and 4 show a circuit configuration of an embodiment of the present invention, and FIGS. 5 and 6 show time charts for explaining the same. First, FIG. 3a shows an example in which the input pulse signal of the change point detection circuit 30 in FIG. 2 is an NRZ code, and 11
301 is an input signal line, 301 is a delay element that delays the input pulse signal from input signal line 11 by t time, and 302 is an exclusive OR element. As is well known, these delay elements 301,
The exclusive OR element 302 is an existing circuit element, and the circuit shown in FIG. 3a can be easily realized. The input pulse signal from the input signal line 11 is divided into a pulse signal that is delayed by a time t by the delay element 301 and outputted, and the input pulse signal as it is, and by adding both to the exclusive OR element 302, the element is As shown in the time chart from 302 to FIG. 3b, a pulse of time t is output at a significant change point of the input pulse signal. FIG. 4 shows the circuit configuration of an embodiment of the entire digital phase synchronization circuit of the present invention including the change point detection circuit 30, in which 241 is a decoder and 242 is a decoder.
is an OR circuit, 243 is an AND circuit, 261' is an octal counter with a reset terminal (hereinafter simply referred to as a counter) that functions as a frequency divider, 271 is a crystal controlled oscillator (hereinafter simply referred to as an oscillator), and 272 is a crystal oscillator. It is.

Other symbols are the same as those shown in FIG. 2 and FIG. 3a.
In this embodiment, the input pulse signal is an NRZ code, and the following explanation is based on that. When the input pulse signal is inputted from the input signal line 11 to the change point detection circuit 30', the pulse at time t at which the change point of the input pulse signal was detected is output as described above (explanation of FIG. 3). The generated pulse is applied to the AND circuit 243 of the filter 240. On the other hand, the oscillator 2 with the crystal oscillator 272 as the vibration source
A clock pulse CL having a frequency approximately eight times the clock frequency of the input pulse signal generated in step 71 is counted by a counter 26.
1 to the clock pulse input terminal CL of the counter 26.
1 performs octal counting and outputs it as a 3-bit signal Q, , Q2, Q3. Generally, the oscillator 27 (Fig. 2) in a DPLL is approximately N times the clock frequency of the input pulse signal, and the output of the oscillator 27 is basically divided by 1/N by the frequency divider 260 (Fig. 2). In this embodiment, N is set to 8, and the following explanation will be given assuming N=8. Therefore, in this embodiment, the counter 261 serving as the frequency divider 260 (FIG. 2) is an octal counter and outputs 3 bits. In other words, if expressed using the IG Hayabusa method, for example, 0, 1, 2.
・・・・・・・・・・・・・・・ When the number 7 is attached to the pulse, the 3-bit output Q, , Q2, Q3 is 0, QI = Q2:
Q3=.・1 is QI=1・Q2=Q=. .........
7 transitions as Q,=Q2=Q3=1. As is well known, this is a binary output and digital frequency division. This output is repeatedly and continuously generated from the counter 261. When the reset signal is input to the initial setting shell 0 reset terminal R of the counter 261, the IJ set is set to the preset outputs Q, , Q2, and Q, but in this embodiment, the settings are changed to Q, Q2, and Q. =Q2=Q=0. In other words, no matter what state the output of the counter 261 is in, IJ
As soon as the set signal comes, Q, = Q2 = Q3 = 0 Z
It is. Various circuit units of such a counter converter 261 already exist and can be easily obtained and used. Further, if a counter with a load terminal is used, the initial state can be freely selected, but in this embodiment, a counter with only a reset terminal is sufficient, so that is used.
The outputs Q, , Q2, and Q8 of the counter 261 are output signals phase-synchronized with the input pulse signal, and are applied to the filter 240 in this embodiment. In this embodiment, the output Q2,
Two bits of Q are used as synchronization signal output,
An example of this is shown in FIG. Q to Phil evening 240
, , Q2 and Q3 are also given. Phil evening 240
Then, the decoder 241 receives this 3-bit signal, decodes the 3-bit binary input (binary signal input), and supplies it to the OR circuit 242. In this embodiment, 0, 1
, 7, only the output of the decoder 241 corresponding to the OR circuit 24
Give to 2. Therefore, if any of them has an output, the output of the OR circuit 242 is generated and applied to the AND circuit 243. The AND circuit 243 connects this input with the above-mentioned change point detection circuit 3.
An output is made only when the input from 0 is ANDed, and this becomes a reset signal for the counter 261. In other words, in this embodiment, the output Q of the counter 261 = Q2 = Q = 0 is initially set as D. If the number corresponds to the internal clock output from the oscillator 271, the 0th clock pulse is set as the initial setting. The reset signal is generated only when the seventh and first internal clocks are in the state before and after that. This is A in the time chart in Figure 5.
These are areas exemplified by B and C. Generally speaking, this means that the reset signal is generated only near the time when the reset signal is expected to be generated, and at other times, that is, in this embodiment, other than the 0, 1, and 7th clock. At the point in time (areas other than A, B, and C in FIG. 5), malfunction of the phase synchronization circuit due to noise is prevented. Note that an input line for the OR circuit 242 of the filter 240 is shown as an example when the input line is out of synchronization, but this is for stopping the operation of the filter 240 in order to accelerate the synchronization pull-in at the time of non-synchronization, and is not directly related to the present invention. Since there is no such thing, the explanation will be omitted.

Note that if the filter 240 is not provided, the output of the change point detection circuit 30 is directly applied to the reset terminal R of the counter 261, and the input to the decoder 241 is of course unnecessary. This embodiment obtains an output signal phase-synchronized with the input pulse signal through the above-described operation, which will be explained in detail below with reference to the time charts of FIGS. 5 and 6. Figure 5 shows the input pulse signal, reset signal, internal clock, and counter 261.
As mentioned above, in this embodiment, the internal clock CL is 8 times the clock frequency of the input pulse signal, so the number assigned to the internal clock CL is 0. When the pulse of
A pulse that passes through the 0 AND circuit 243, ie, a reset signal, is applied to the counter 261.

It is normal for the reset signal to exist in the B area of the internal clock CL in the figure, that is, the reset signal and the output of the counter 261 are in complete agreement, and in this case, the reset signal has no effect on the operation of the counter 261. No, but the input pulse signal and internal clock CL from oscillator 271
Since these are usually not completely synchronized, if the phase of the input pulse signal is ahead at the output point of the reset signal, it moves to the A area side in FIG. 5, and when it is delayed, it moves to the C area side.
The state at that time is shown in FIGS. 6a and 6b. Figure 6 (a) shows the state when the reset signal appears on the A area side. At this time, the output of the counter 261 is Q. =Q2=Q3=1
When , it is reset by a reset signal, and the state of the 7th pulse disappears and becomes the 0th state. In other words, the state transition is accelerated by one clock 0 minute of the internal clock, producing the same effect as adding one clock pulse. FIG. 6b shows the state when the reset signal appears on the C area side. In this case, the internal clock CL is the first
Since it is reset when the pulse number is in the state (Q,=1, Q2:Q3=0), the state transition is delayed by one clock. In other words, for the outputs Q2 and Q3, this is equivalent to removing one clock pulse. That is, the same effect as the pulse addition/removal (25 in FIG. 1) of the conventional DPLL can be obtained. -
As described above, even if a reset signal is generated in areas other than areas A, B, and C in FIG. 5, the filter 240 prevents the reset operation from being performed. That is, no reset signal is generated due to noise. In the time charts of FIGS. 5 and 6, the outputs Q, , Q2, and Q3 of the counter 261 change with the rising edge of the reset signal and the falling edge of the internal clock CL, but this is important for the operation of this circuit. It is obvious that this is not a particularly necessary condition, and other conditions such as the rising edge of the reset signal and the falling edge of the clock CL may be used. Furthermore, in this embodiment, if the reset signal is not generated while the phase difference error between the input pulse signal and the output of the counter 261 is smaller than the period of the internal clock CL, synchronization will be lost. Generally, the accuracy of 10-4 to 10-5 can be easily achieved with respect to the input pulse signal, and even if you consider a bad condition of 10-Kinseido, N = 8.
When 1/8 x 10-3 = 125, 1 in 125 times
If the input pulse signal changes between 0 and 1 every time, synchronization will not be lost, and there is no problem in practice. Furthermore, when the input pulse signal is an RZ code, as is well known, it is only necessary to generate a reset signal using the rising edge when a 1 appears, so the accuracy required of the oscillator 271 is less strict than for the NRZ code. It's fine. As explained above, according to this embodiment, the circuit configuration is extremely simple, and the circuit unit used in this embodiment can be used in easily available general-purpose logic, so it is an inexpensive and small digital phase synchronization circuit. can be realized.

Therefore, if the present invention is applied to a synchronization device for a digital communication system, it will have a large effect in terms of storage space and economy.Furthermore, it can be combined with a frame synchronization circuit, for example, by taking advantage of the feature that it can be configured with only logic elements. Integrating them into one would be extremely effective in downsizing the device.

[Brief explanation of the drawing]

Figure 1 is an example of the circuit configuration of a conventional DPLL, Figure 2 is the basic circuit configuration of the present invention, Figure 3 is the circuit configuration of an embodiment of the change point detection circuit and its time chart, and Figure 4 is the invention of the present invention. 5 is a time chart of the embodiment of FIG. 4, and FIG. 6 is a time chart for explaining the phase synchronization operation of the embodiment of FIG. 4. 11... Input signal line, 30... Change point detection circuit, 3
01... Delay element, 302... Exclusive OR element, 240... Filter, 241... Decoder, 242... OR circuit, 243... AND circuit, 26
0... Frequency divider with initial setting terminal, 261...
Octal counter with reset terminal, 27... Oscillator, 2
71... Crystal controlled oscillator, 272...
Crystal oscillator. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 In a digital phase synchronized circuit, there is a change point detection circuit that detects a significant change point in the input pulse signal, and a frequency divider with an initial setting terminal (hereinafter referred to as A frequency divider), an oscillator that oscillates at a constant frequency, and a filter that receives the output signal of the frequency divider and generates the reset signal only in a specific state region of the period of the output signal, and The output of the oscillator is frequency-divided by the frequency divider and outputted, and is provided to the filter, while the input pulse signal is input to the change point detection circuit, and the output of the change point detection circuit is input to the filter. A digital device characterized in that the output signal of the frequency divider is outputted in synchronization with the clock frequency of the input pulse signal by generating a reset signal and applying it to the frequency divider only in the region of the specific state. Phase-locked circuit.