JP3144497B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer using a phase-locked loop (PLL) structure having a function of arbitrarily setting an output frequency and enabling a fast frequency switching time. It is about improvement.

[0002]

2. Description of the Related Art Conventionally, as a frequency synthesizer using a phase locked loop (PLL) configuration capable of arbitrarily setting an output frequency, a voltage controlled oscillator (VCO) has been conventionally used.
A feedback signal obtained by dividing the output of the ntrolled oscillator using a variable frequency divider and a reference signal having a constant frequency are input to a phase comparator, and the output of the phase comparator is fed back to a VCO via a loop filter. Is widely applied. FIG. 9 shows this conventional configuration diagram. In the figure, 301 is V
CO, 302 is a frequency divider, 303 is a reference oscillator, 304 is a phase comparator, and 305 is a loop filter.

In the above conventional configuration, the phase comparator 304 is generally configured to perform a multiplication process of a reference signal and a feedback signal, and the low frequency component of the output of the phase comparator 304 includes phase error information. Therefore, the loop filter 305 for largely suppressing and removing unnecessary harmonics is indispensable. However, the frequency switching time of the frequency synthesizer depends on the time constant of the loop filter 305, and it is necessary to set the time constant small in order to set the switching time short. On the other hand, in order to secure the S / N (signal-to-noise power ratio) of the frequency synthesizer output to a certain value or more, it is necessary to set the time constant of the loop filter 305 to a large value.

As described above, in the conventional configuration, the improvement in S / N by removing unnecessary harmonics and the speeding up of the frequency switching time are mutually reciprocal, so that both can be satisfied simultaneously. A problem arises that it cannot be performed.
To remedy this problem, in the configuration of FIG. 9, the time constant of the loop filter 305 is set to a small value (high-speed pull-in) between the pull-in operation at the time of frequency switching and the steady operation after the pull-in.
A method of switching from a high value to a high value (high S / N) has also been devised.

[0005]

However, in this method,
The output value of the phase comparator fluctuates due to the frequency fluctuation caused by the fluctuation of the VCO input voltage generated when the loop filter is switched, and eventually, a long-time transient response occurs. For this reason, at the time of switching the frequency, additional measures such as suppression of the output fluctuation of the loop filter and temporary storage and holding of the output value of the phase comparator are required, and the circuit scale becomes large. SUMMARY OF THE INVENTION It is an object of the present invention to avoid the problem of the reciprocal relationship between the speeding up of the frequency switching time and the high S / N in the conventional configuration, and to reduce the size and I
An object of the present invention is to provide a frequency synthesizer suitable for computerization.

[0006]

A frequency synthesizer according to the present invention compares a phase of a feedback signal obtained by dividing the output of a voltage controlled oscillator with a reference signal from a reference oscillator, and uses the output as a control voltage of the voltage controlled oscillator as an output frequency. in the frequency synthesizer according to the phase-locked loop structure capable of arbitrarily variably set outside based on a reference clock from said reference oscillator
The open loop / closed loop switching signal supplied from the
Divides the reference clock only at the time of the
And the reference phase signal generating means for outputting a signal [psi, the based on the fixed frequency divider, the output of the fixed frequency divider for fixing divide the output frequency of said voltage controlled oscillator to 1 / P (P ≧ 1) Open
Only when the loop / closed loop switching signal is a closed loop signal
Integrates a predetermined phase increase step value input from outside
Digital value of 2π radians of the integrated phase output
Phase signal output means for outputting as a feedback phase signal φ
And the reference phase signal ψ and the feedback phase signal φ , and according to the equation ε = [｛ψ−φ + 3π｝ mod2π] -π (where ｛·｝ mod2π is the remainder when divided by 2π radians) output range is obtained (-π~π) a phase comparator circuit for outputting a phase error signal ε in radians, the phase error signal ε from the phase comparator averaged wishes 1 of Tokoro <br/> constant An averaging circuit that outputs in a time zone, a recursive filter that performs digital filtering on an averaged value outside 1 from the averaging circuit and outputs an output value ε ′, and inputs the ε, outside 1 and ε ′. , by the open-loop / closed-loop switching signal, the during closed loop operation epsilon, the during open-loop operation the outer 1, further predetermined slot in open-loop operation after the number of epsilon ', and switching each output, analog conversion do it
Switching output means for controlling the voltage of the voltage controlled oscillator . Further, generating the reference phase signal
The means receives the reference clock from the reference oscillator at one input.
The open-loop / closed-loop switching signal as the other input
Open loop outputs the reference clock at the time of the closed-loop operation with
During operation, the first AND gate circuit for stopping the reference clock
And a reference clock from the first AND gate circuit.
Counter that generates reference phase signal に よ り by dividing
DOO are provided, the feedback phase signal output means, the fixed
Open loop / closed loop with the output of a frequency divider as one input
When the switch signal is used as the other input, the fixed
Outputs the output clock of the fixed frequency divider and outputs during open loop operation
A second AND gate circuit for stopping a clock;
According to the output clock timing of the AND gate circuit
Integration of a predetermined phase increase step value input from outside
Digital modulo 2π radians of phase integrated output
A numerically controlled oscillator that outputs the value as a feedback phase signal φ
It is characterized by having been provided. In addition, the
The fixed frequency division as one input of one AND gate circuit
Feedback from the counter by giving output from the
A phase signal φ is generated and output, and the second AND gate circuit
The reference clock from the reference oscillator as one input of the
The reference phase from the numerically controlled oscillator
Signal ψ is generated and output.
Things.

[0007]

FIG. 1 is a structural example of a frequency synthesizer according to a first embodiment of the present invention. In the figure, reference numeral 1 denotes a reference oscillator, which outputs a reference clock. 2 is AN
The D gate circuit receives the reference clock and outputs a reference clock during a closed loop operation and stops the reference clock during an open loop operation in response to an open / closed loop switching signal supplied from outside. 3 is a counter,
By dividing the frequency of the reference clock output from the AND gate circuit 2, a reference phase signal ψ is generated. Reference numeral 4 denotes a voltage controlled oscillator (VCO: Voltage Controlled Oscillator), which outputs an oscillation frequency f ₀ according to a control voltage from an LPF 13 described later. 5 is a fixed frequency divider,
The output frequency f ₀ of 4 fixed divider to 1 / P (P ≧ 1) ,
f _CLK (= f ₀ / P) is output. 6 is the same AN as 2
A D gate circuit, enter the f _CLK from the fixed frequency divider 5, by the open-loop / closed-loop switching signal, and outputs the f _CLK during closed loop operation, during open loop operation f _CLK
To stop.

Reference numeral 7 denotes a numerically controlled oscillator (NCO: Numerical)
Controlled Ocillator) a and, in accordance with the timing of the output f _CLK of the AND gate circuit 6 integrates the phase increment step value set from the outside (digital value) [Delta] [phi, the feedback phase signal φ (0 ≦ φ ≦ 2π: φ digital Value). The circuit can be easily constituted by an adder and a register.

Reference numeral 8 denotes a phase comparison circuit, which receives the reference phase signal ψ from the counter 3 as one input (added value),
7 is used as the other input (subtraction value) using the feedback phase signal φ from the control signal 7 to output a phase error signal ε (−π ≦ ε ≦ π) according to the following equation (1). ε = [｛(ψ−φ) + 3π｝ mod2π] -π (1) where ｛·｝ mod2π represents a remainder when divided by 2π radians. The circuit can be easily constituted by an adder.

[0010] 9 is an averaging circuit averages the phase error signal ε from the position phase comparator circuit 8, and outputs a phase error average value out 1 at a predetermined time period after the start of the open-loop operation. The circuit can be easily constituted by an adder and a register. FIG. 3 is a configuration example diagram showing details of the averaging circuit 9. In the figure, 10
1 is an adder, which receives the phase error signal ε as one input,
An addition operation is performed using a value fed back from a register 102 described later as the other input, and the result is output. A register 102 temporarily stores the output of the adder 101 and outputs the output at the timing of an integrated clock supplied from the outside. The output of the circuit is fed back to the adder 101. With the above configuration, the number of integrations of the phase error signal ε by the adder 101 is set to 2 ^m times, and a value obtained by dropping the obtained integrated value by m bits, that is, a value of 2 ^−m times is set to 1 outside the average value. Thus, an average operation of 2 ^m samples can be obtained.

Referring back to FIG. 1, reference numeral 10 denotes a recursive filter, which digitally filters the phase error average value for each slot and outputs the result. The circuit can be easily constituted by an adder and a register. FIG. 4 is a structural example diagram showing the details of the recursive filter. In the figure, reference numeral 201 denotes an adder that uses 1 outside the average value of the phase error as one input (addition value). Reference numeral 202 designates an output of the adder 201 as one input, and a register 2 described later.
This is an adder that performs an addition operation using the value fed back from 03 as the other input and outputs the result. A register 203 temporarily stores the output of the adder 202 and outputs the output at a timing externally supplied. Reference numeral 204 denotes a process for obtaining a value of 2 ⁻ⁿ times the output of the circuit, which can be easily configured by a shift wiring for lower bits of n bits. The output of this circuit 204 is fed back to the other input of the adder 201 and is output as a recursive filter output value ε ′ of the phase error.

Referring back to FIG. 1, reference numeral 11 denotes a switch.
The phase error signal ε from the phase comparison circuit 8 and the phase error average value 1 out of the averaging circuit 9, and the recursive filter 10
And outputs the phase error signal ε during the closed loop operation and outputs 1 out of the phase error average value during the open loop operation in accordance with the open loop / closed loop switching signal.
Further, after the predetermined number of slots, the phase error filtering value ε ′ is output during the open loop operation. 12 is D
/ A converter, which converts a digital output value of the switch 11 into an analog value. 13 is a low-pass filter (LPF: LowP)
ass filter), which removes the quantization noise component included in the output of the D / A converter 12 and feeds it back to the control voltage input of the VCO 4.

FIG. 2 is a structural example showing a second embodiment of the present invention. All the components in the configuration example of FIG. 2 are exactly the same as components 1 to 13 of FIG. 1 except that the inputs of the AND gate circuits 2 and 6 correspond to the fixed frequency divider 5 and the reference oscillator 1 respectively. Only the connection to the output differs from the case of FIG.

[0014]

The operation of the present invention based on the configuration examples shown in FIGS. 1, 3 and 4 will be described below with reference to FIGS. 5, 6, 7 and 8. First, the operation of the synchronization pull-in during the closed loop operation will be described with reference to FIG. 5 (a), 5 (b) and 5 (c)
Shows an operation time chart example of the feedback phase signal φ, the reference phase signal ψ, and the phase error signal ε during the closed loop operation. At time 0, the output of the NCO 7 is set to φ = 0. Thereafter, the NCO 7 outputs 1 of the output signal f _CLK of the fixed frequency divider 5.
The integration of the phase increase step value Δφ is continued for each cycle (1 / f _CLK ), and the output of the NCO 7 by the integration is shown in FIG.
As shown in the figure, the value rises stepwise in steps of Δφ. Next, at time A, when the value of φ reaches 2π or more, the value exceeds 2π, falls to a value obtained by subtracting 2π from the tentative integrated value shown by the broken line, and rises again in steps of Δφ. Time A
Thereafter, the same operation as that after time 0 is repeated to obtain a feedback phase signal φ having a sawtooth waveform.

On the other hand, since the reference phase signal ψ is given as a numerical value obtained by integrating and counting the output of the reference oscillator 1 by the counter 3, it has a saw-tooth waveform similar to φ as shown in FIG. Now, consider the case where the feedback phase signal φ is in a leading phase with respect to the reference phase signal ψ, as shown in FIG. At this time, a simple numerical difference (ψ−φ) between the reference phase signal ψ and the feedback phase signal φ shown by the broken line in FIG. 5C includes −2π every time the reference phase signal is converted from 2π to 0. Phase jump occurs. This phase jump is corrected by the operation based on the equation (1) by the phase comparison circuit 8, and a phase error signal ε as shown by a solid line in FIG. 5C is obtained.

As described above, in the configuration according to the present invention, the above-mentioned reference phase signal ψ and feedback phase signal φ are direct phase information and the true phase error is obtained in the phase error signal ε in the synchronization pull-in by the closed loop operation. Therefore, it can be understood that, in theory, the phase error signal ε does not include a harmonic component, and the loop filter for suppressing the harmonic component, which is required in the conventional configuration, is essentially unnecessary. For this reason, the time constant of the loop filter, which has caused the frequency switching time to be long in the conventional configuration, can be set to a small value in the present invention, so that the frequency can be rapidly switched. The phase error signal ε is converted into an analog value by the D / A converter 12, and after the quantization noise component is removed by the LPF 13,
It is fed back to the control voltage input of VCO4. With the configuration of the negative feedback loop, a desired output frequency f ₀ can be obtained.

Here, the relationship between the output frequency f ₀ and the phase increase step value Δφ of the NCO 7 will be derived. First,
The reference clock is an input of the counter 3 and f _c, the frequency division number of the counter 3 is N, the period T _C in FIG. 5 (b) represented by the following equation (2). The period T _NCO of the _{NCO 7} is given by the following equation (3). The period T _C of the reference phase signal and the period T of the feedback phase signal
_{Since the NCO satisfies} T _C = T _NCO in the phase locked state, the following equation (4) is obtained from the equations (2) and (3). The output clock f _CLK of the fixed frequency divider 5 is given by the following (5)
It is shown by the formula. Therefore, from the expressions (4) and (5), the output frequency f ₀ can be expressed by the following expression (6). (6) from the equation, P, N, When the f _c constant, the output frequency f ₀ is seen to be able to uniquely determine the relationship that is inversely proportional to [Delta] [phi.

Next, FIG. 6 shows a flowchart of the frequency switching operation in the configuration of the present invention. In the figure, after the operation is started (START), first, in step 1,
The output frequency is set by setting Δφ based on the relationship of equation (6), and the operation enters a closed loop operation. By the closed loop operation, after the synchronization is pulled in at step 2, the operation goes to step 3 and the averaging circuit 9 performs the averaging operation of the phase error signal ε.
When the average value 1 is obtained, in step 4, an open loop operation is performed with a control voltage having the outside value 1 as a holding value, and the recursive filter output value ε 'is updated. Finally, in step 5, the open loop operation is continued with the control voltage having the recursive filter output value ε 'as the holding value.

The above series of operations will be further described with reference to FIG. FIG. 7 is a time chart showing a frequency switching operation based on the flowchart shown in FIG.
In the figure, the upper part shows the output frequency of the VCO 4, the middle part shows the open-loop / closed-loop switching signal input to the AND gate circuits 2 and 6, the averaging circuit 9 and the switch 11, and the lower part shows the integrated output of the averaging circuit 9, respectively. ing. In the figure, now, consider the case of switching the output frequency from f ₁ to f _2. At this time, in the process from step 1 to step 2 in FIG. 7, the output frequency of the VCO 4 is changed to f ₁ by the closed loop operation.
To f ₂ . Next, from the time when the synchronization pull-in is completed, in step 3, the output of the averaging circuit 9 is first reset, and the averaging (integration) process is started immediately. In step 4, the operation is switched to the open loop operation and the D / A
1 out of averaging circuit output for converter 12 and LPF 13
Is supplied. Since the outside 1 has a constant value during the open loop operation, a stable output frequency can be obtained.

Further, during open loop operation, the AND gate circuit 2 and 6, by stopping the counter 3 and NCO7 output f _CLK of the reference clock and the fixed frequency divider 5 for supplying each reference phase signal ψ and Holds the feedback phase signal φ to prevent phase slips of ψ and φ. As a result, the phase error signal ε at the start of the next closed loop operation is held at the final value of the previous closed loop operation, and the synchronization pull-in by the next channel switching can be performed at high speed.

The filtering operation by the recursive filter 10 of the phase error average output 1 obtained by the above series of operations will be described with reference to FIG. Here, if the output frequency f ₁ will be described as an example. Within each slot in FIG., A broken line is outside 1, epsilon ', are each a target value of f _1, the solid line is a respective output value. Now, the average value of the phase error in the R-th slot is set to 2 and (R
-1) The filtering value of the slot is ε ′ _R−1 ,
The number of integrations by the adder 202 and the register 203 is 2 ⁿ
far. At this time, the output ε ′ of the recursive filter 10
_R is represented by the following equation (7).

[Outside 2]

(Equation 1) From equation (7), the recursive filter output value ε ′ _R is
The recursive filter output value ε ′ _{R−1 of the} (R−1) th slot is a weighted average of 2 out of the average value of the phase error in the Rth slot. , The filtering value ε ′ of the phase error approaches a constant value, and a more stable output frequency can be obtained. In addition, as the initialization processing of the operation of the recursive filter, only the integration of 1 outside the average value of the phase error is performed in the initial n sections. During the open loop operation after the elapse of the interval n, the recursive filter 1
It is configured to output an output value ε ′ _R of 0.

Next, the operation of the present invention will be described based on the configuration example of the second embodiment shown in FIG. 2, the reference phase signal ψ is obtained by the NCO 7 and the feedback phase signal φ is obtained by the counter 3, contrary to the case of FIG. Therefore, derived in the configuration of FIG.
F _c and f _CLK in equations (2), (3) and (4)
Are exchanged with each other, so that the following equations are obtained.

On the other hand, in the configuration of FIG.
Since the equation holds, this equation (5) and the above (4) ′
According to the equation, the output frequency f ₀ can be eventually expressed by the following equation corresponding to the above-described equation (6). From the above (6) 'formula, P, N, When the f _c constant, the output frequency f _0, in the configuration of FIG 1 while was related inversely proportional to Δφ (6) formula, 2 In the configuration of ψ
It can be understood that it can be uniquely determined by a relationship proportional to.

[0024]

As described in detail above, in the configuration of the frequency synthesizer of the present invention, since the feedback phase signal is directly extracted or the reference phase signal is generated by using the NCO, the digital synthesizer is used. Direct phase comparison by signal processing becomes possible. Therefore, the harmonic component generated in the conventional configuration does not occur, and the time constant of the loop filter can be set to a small value, so that the frequency pull-in time in the closed loop operation can be shortened. Further, after the frequency is pulled in by the closed loop operation, the phase error component is averaged using an averaging circuit, the average value is held and the open loop operation is performed, and the phase error average value is further filtered. A highly stable signal can be obtained.
Furthermore, since most of the circuits are digital signal processing, there are advantages such as miniaturization of the circuits and suitability for IC.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration example of an averaging circuit in FIGS. 1 and 2;

FIG. 4 is a block diagram illustrating a configuration example of a recursive filter circuit in FIGS. 1 and 2;

FIG. 5 is a time chart of a feedback phase signal, a reference phase signal, and a phase error signal according to the present invention.

FIG. 6 is a flowchart of a frequency switching operation according to the present invention.

FIG. 7 is a time chart of frequency switching according to the present invention.

FIG. 8 is a time chart of an output frequency by the recursive filter of the present invention.

FIG. 9 is a block diagram of a conventional PLL frequency synthesizer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reference oscillator 2 AND gate circuit 3 counter 4 voltage controlled oscillator (VCO) 5 fixed frequency divider 6 AND gate circuit 7 numerically controlled oscillator (NCO) 8 phase comparison circuit 9 averaging circuit 10 recursive filter 11 switch 12 D / A Converter 13 low-pass filter 101 adder 102 register 201 adder 202 adder 203 register 204 divider 301 voltage-controlled oscillator (VCO) 302 frequency divider 303 reference oscillator 304 phase comparator 305 loop filter

Continuation of the front page (56) References JP-A-4-248715 (JP, A) JP-A-1-114122 (JP, A) JP-A-3-109818 (JP, A) JP-A-4-137914 (JP) JP-A-2-331818 (JP, A) JP-A-1-97017 (JP, A) JP-A-62-88428 (JP, A) JP-A-61-57122 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/18

Claims (3)

(57) [Claims] 1. A phase-locked loop capable of comparing the phase of a feedback signal obtained by dividing the output of a voltage controlled oscillator with a reference signal from a reference oscillator, and using the output as a control voltage of the voltage controlled oscillator to arbitrarily set an output frequency. In a frequency synthesizer having a configuration , externally supplied based on a reference clock from the reference oscillator.
If the open-loop / closed-loop switching signal is
Only when the reference clock is divided, a reference phase signal ψ is obtained.
A reference phase signal generating means for outputting a fixed frequency divider, a fixed frequency divider for dividing the output frequency of the voltage controlled oscillator to 1 / P (P ≧ 1), and the open loop based on an output of the fixed frequency divider. / Closed loop switching
Where the signal is externally input only when the signal is a closed loop signal
2π of the phase integrated output obtained by integrating the constant phase increment step value
The digital value modulo radians is the feedback phase signal φ.
Feedback phase signal output means for outputting the reference phase signal ψ and the feedback phase signal φ ,
Equation ε = [｛ψ−φ + 3π｝ mod2π] −π (where,
{·} Mod2π includes a phase comparison circuit output range obtained according remainder) when divided by 2π radians to output a phase error signal ε of (-Pai～pai) radian, the phase error signal from the phase comparator circuit an averaging circuit for outputting wishes 1 obtained by averaging epsilon in Jo Tokoro time period, a recursive filter for outputting the averaged wishes 1 output value by performing a digital filtering epsilon 'from the averaging circuit Ε, outside 1 and ε ′ are input, and ε during the closed loop operation, outside 1 during the open loop operation, and further during the open loop operation after a predetermined number of slots, according to the open loop / closed loop switching signal. Switches and outputs ε ', and converts to analog
Switching output means for controlling the voltage of the voltage controlled oscillator
Frequency synthesizer characterized by comprising and. [Outside 1] 2. The reference phase signal generating means according to claim 1 , wherein
The reference clock from the oscillator is used as one input and the open loop
Closed loop operation with the loop / closed loop switching signal as the other input
At times, the reference clock is output and during open loop operation, the reference clock is output.
A first AND gate circuit for stopping the lock, and a first A
By dividing the reference clock from the ND gate circuit,
And a counter for generating a reference phase signal り, wherein the feedback phase signal output means outputs the output of the fixed frequency divider.
One of the inputs is the open loop / closed loop switching signal
The output of the fixed frequency divider during closed loop operation
Output clock and stop output clock during open loop operation
A second AND gate circuit, and a second AND gate
External input according to the output clock timing of the circuit
Product calculation by integrating the specified phase increment step value
Returns the digital value modulo 2π radians
A numerically controlled oscillator that outputs the signal φ
The frequency synthesizer according to claim 1, wherein: 3. The one input of said first AND gate circuit.
By giving the output from the fixed divider as a force
Generating and outputting a feedback phase signal φ from the counter;
The reference output is provided as one input of a second AND gate circuit.
By giving a reference clock from a shaker,
The control oscillator is configured to generate and output the reference phase signal ψ.
The frequency synthesizer according to claim 2, wherein:
Isa.