JPH0659030B2 - Frequency synthesizer - Google Patents
Frequency synthesizerInfo
- Publication number
- JPH0659030B2 JPH0659030B2 JP60194093A JP19409385A JPH0659030B2 JP H0659030 B2 JPH0659030 B2 JP H0659030B2 JP 60194093 A JP60194093 A JP 60194093A JP 19409385 A JP19409385 A JP 19409385A JP H0659030 B2 JPH0659030 B2 JP H0659030B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output signal
- output
- voltage controlled
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】 本発明は、間接式周波数シンセサイザの構成に関するも
ので、特に小さな周波数可変ステップで周波数切替えが
可能であり、出力位相雑音特性が良好な周波数シンセサ
イザを実現する技術に関する。The present invention relates to a configuration of an indirect frequency synthesizer, and more particularly to a technique for realizing a frequency synthesizer capable of frequency switching with a small frequency variable step and having a good output phase noise characteristic.
（従来の技術） 従来、間接式周波数シンセサイザの構成としては第２図
に示す回路形式のものが良く知られている。第２図に周
波数シンセサイザは基準信号発生器１の出力信号ｆ
Ｒ（周波数がｆＲであることをも示す）を固定分周器４
でＭ分周し、一方電圧制御発振器３の出力信号ｆＯ（周
波数がｆＯであることをも示す）をその分周数Ｎを可変
しうる可変分周器５で分周し、両者の周波数および位相
を位相周波数検出器２で比較し、得られた誤差信号を電
圧制御発振器３の周波数制御端子へ負帰還し、可変分周
器５の分周数Ｎを制御する事により電圧制御発振器の出
力周波数を に従って周波数ステップｆＲ／Ｍで発生するものであ
る。(Prior Art) Conventionally, as a configuration of an indirect frequency synthesizer, a circuit type shown in FIG. 2 is well known. In FIG. 2, the frequency synthesizer is the output signal f of the reference signal generator 1.
R (also indicating that the frequency is f R ) is a fixed frequency divider 4
, And the output signal f O of the voltage controlled oscillator 3 (which also indicates that the frequency is f O ) is divided by a variable frequency divider 5 whose frequency division number N can be varied. The frequency and phase are compared by the phase frequency detector 2, the obtained error signal is negatively fed back to the frequency control terminal of the voltage controlled oscillator 3, and the frequency division number N of the variable frequency divider 5 is controlled to control the voltage controlled oscillator. Output frequency of According to the frequency step f R / M.
（発明が解決しようとする問題点） 上記従来の周波数シンセサイザでは小さい周波数ステッ
プで出力周波数を設定しようとすると位相周波数比較周
波数が低くなり、比較周波数成分で電圧制御発振器が周
波数変調される事を防ぐ為に位相周波数比較周波数に比
して位相同期ループのループ帯域幅はさらに小さくしな
ければならないが、その結果として電圧制御発振器の位
相雑音を位相同期ループで十分圧縮できないという欠点
を有していた。(Problems to be Solved by the Invention) In the above-described conventional frequency synthesizer, when the output frequency is set in small frequency steps, the phase frequency comparison frequency becomes low, and the voltage controlled oscillator is prevented from being frequency-modulated by the comparison frequency component. Therefore, the loop bandwidth of the phase-locked loop must be made smaller than that of the phase-frequency comparison frequency, but as a result, the phase noise of the voltage-controlled oscillator cannot be sufficiently compressed by the phase-locked loop. .
また、従来のシンセサイザでは電圧制御発振器の出力信
号をＮ分周後位相周波数比較しているが、これは位相比
較周波数の信号をＮ逓倍する事と等価であり逓倍により
位相変調の指数が大きくなる為結果として周波数シンセ
サイザの出力信号位相雑音特性が劣化するという欠点を
有していた。Further, in the conventional synthesizer, the output signal of the voltage controlled oscillator is compared with the phase frequency after being divided by N. This is equivalent to multiplying the signal of the phase comparison frequency by N, and the index of phase modulation increases by the multiplication. As a result, the output signal phase noise characteristic of the frequency synthesizer is deteriorated.
これらの欠点を解決する為、直接式周波数シンセサイザ
と組み合わせる等種々の工夫がなされているが、どれも
回路形式が非常に複雑で高価であるという問題がある。In order to solve these drawbacks, various measures have been taken, such as combination with a direct frequency synthesizer, but all have a problem that the circuit form is very complicated and expensive.
本発明の目的は、上記従来の周波数シンセサイザが有し
ている問題点を解決し、小さな周波数可変ステップと良
好な位相雑音特性を有する周波数シンセサイザを簡単な
回路で実現しようとするものである。An object of the present invention is to solve the problems of the conventional frequency synthesizer and to realize a frequency synthesizer having a small frequency variable step and a good phase noise characteristic with a simple circuit.
（問題点を解決するための手段） 本発明は上記の目的を達成するために次の構成を有す
る。即ち、本発明の周波数シンセサイザは、制御電圧に
よって発振周波数が制御される電圧制御発振器と；基準
周波数信号を発生する基準信号発生器と；前記電圧制御
発振器の出力信号を前記基準信号発生器の出力信号でサ
ンプリングするサンプラーと；前記基準信号発生器の出
力信号を分周する分周器であって、その分周数が制御信
号により２値以上に切り替えられる切替式分周器と；前
記電圧制御発振器の出力周波数がｆＯ、前記基準信号発
生器の出力周波数がｆＲであるとき式｜ｆＯ−ｍｆＲ｜
≦ｆＲ／２を満足する正の整数ｍが定まったときに、ｆ
Ｒ／｜ｆＯ−ｍｆＲ｜で表される数の直近上位の整数を
ｐとしたとき、前記サンプラーの出力信号の周期がｐ／
ｆＲのときにはｐを、同出力信号の周期が（ｐ−１）／
ｆＲのときにはｐ−１をそれぞれ分周器の分周数とする
ための制御信号を前記切替式分周器へ供給する制御器
と；前記サンプラーからのサンプリング出力信号と前記
切替式分周器の分周出力とを受けて両者を比較し、その
誤差出力信号を周波数制御電圧として前記電圧制御発振
器へ負帰還を形成するように供給する位相周波数検出器
又は位相検出器と；を有することを特徴とする。(Means for Solving Problems) The present invention has the following configuration in order to achieve the above object. That is, the frequency synthesizer of the present invention includes: a voltage-controlled oscillator whose oscillation frequency is controlled by a control voltage; a reference signal generator that generates a reference frequency signal; and an output signal of the voltage-controlled oscillator that is output from the reference signal generator. A sampler for sampling with a signal; a frequency divider for frequency-dividing the output signal of the reference signal generator, and a switching frequency divider whose frequency division number can be switched to two or more values by a control signal; the voltage control When the output frequency of the oscillator is f O and the output frequency of the reference signal generator is f R , the formula | f O −mf R |
When a positive integer m that satisfies ≦ f R / 2 is determined, f
R / | f O -mf R | in when the integer immediately above the number and p represented, the period of the output signal of the sampler p /
In the case of f R , p is set, and the cycle of the output signal is (p-1) /
a controller for supplying a control signal to the switch-type frequency divider for making p-1 the frequency division number of the frequency divider when f R ; a sampling output signal from the sampler and the switch-type frequency divider A phase frequency detector or a phase detector for supplying the error output signal as a frequency control voltage so as to form a negative feedback to the voltage controlled oscillator. Characterize.
（作 用） 以下、本発明の周波数シンセサイザの作用を図面に基づ
いて説明する。第１図は本発明の周波数シンセサイザの
構成を示すブロック図である。(Operation) The operation of the frequency synthesizer of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the frequency synthesizer of the present invention.
まず、周波数ｆＲの基準信号発生器１の出力信号で電圧
制御発振器３の出力信号ｆＯをサンプラー８を使用して
サンプルする。サンプラー８としては種々の形式のもの
が考えられるが最も簡単なものとしてＤ型フリップフロ
ップが考えられる。First, the output signal f O of the voltage controlled oscillator 3 is sampled by using the sampler 8 with the output signal of the reference signal generator 1 having the frequency f R. As the sampler 8, various types can be considered, but the simplest one is a D-type flip-flop.
サンプラーとしてＤ型フリップフロップを使用した場合
Ｄ入力に電圧制御発振器の出力信号ｆＯを、クロック入
力に基準信号発生器の出力信号ｆＲを供給すると、Ｄ型
フリップフロップの出力端子ＱにはｆＯ＞ｆＲの時 を満足する周波数の信号ｆＱが得られる。しかし、この
出力信号ｆＱは本質的にｆＲでサンプリングされている
為、その周期は1/fRの倍数となり、ｆＲ＝ｐｆＱ（ｐは
正の整数）が成立する周波数以外では、任意の１周期の
時間が必ず1/fQというのではなく長時間平均における周
期が1/fQになるだけである。もう少し詳しく説明すると
ｆＱのＡ回周期において上記等式が成立している時、出
力信号ｆＱは次のように考えられる。When a D-type flip-flop is used as the sampler, when the output signal f O of the voltage controlled oscillator is supplied to the D input and the output signal f R of the reference signal generator is supplied to the clock input, the output terminal Q of the D-type flip-flop is f When O > f R A signal f Q having a frequency that satisfies However, since this output signal f Q is essentially sampled at f R , its period is a multiple of 1 / f R , and at frequencies other than the frequency at which f R = pf Q (p is a positive integer) holds, The time of any one cycle is not always 1 / f Q , but the cycle in long-term average is only 1 / f Q. When the above equation is satisfied in A times the period of f Q With a little more detail, the output signal f Q is considered as follows.
ある長時間周期Ａサイクル中、 の周期がｎサイクル、p/fRの周期が（Ａ−ｎ）サイクル
現われる事となり、従ってｆＱは とfR/pの２つの周波数の合成で構成されその現出する確
率によりｆＱのＡサイクルにおける平均周波数が上記等
式（１）を満足する。Ａサイクルの周期は と表わされる。これより平均周波数として が得られる。During a certain long period A cycle, The cycle of n is n cycles and the cycle of p / f R is (A−n) cycles, so f Q is The average frequency in the A cycle of f Q satisfies the above equation (1), which is composed of a combination of two frequencies of f R / p and f R / p. The cycle of A cycle is Is represented. From this, the average frequency Is obtained.
fR／ｐの現出する順番はｆＯとｆＲが決定すると一義的
に定まり計数で求める事が出来る。またｐは で計算される。 The order in which f R / p appears is uniquely determined when f O and f R are determined, and can be obtained by counting. Also p is Calculated by
一方基準信号発生器１の出力信号ｆＲは切替式分周器６
に供給される。切替式分周器６はその分周数をｐ−１と
ｐに制御器７よりの制御信号に従って切替える動作を行
なうものである。ｐ−１，ｐの現出順位は所要の電圧制
御発振器３の出力周波数と基準信号発生器１の出力周波
数に対して制御器７で計算決定される。つまり先に述べ
た電圧制御発振器３の出力信号ｆＯが所要周波数の時サ
ンプラー８の出力信号ｆＱに現われる fR/pの現出順位に一致させるものとする。On the other hand, the output signal f R of the reference signal generator 1 is the switching type frequency divider 6
Is supplied to. The switching frequency divider 6 performs an operation of switching the frequency division number between p-1 and p according to a control signal from the controller 7. The appearance order of p-1, p is calculated and determined by the controller 7 for the required output frequency of the voltage controlled oscillator 3 and the output frequency of the reference signal generator 1. That is, the output signal f O of the voltage controlled oscillator 3 described above appears in the output signal f Q of the sampler 8 when the required frequency is reached. It should match the appearance order of f R / p.
次に切替式分周器６の出力信号とサンプラー８の出力信
号を位相周波数検出器２に供給し両者の位相および周波
数を比較する。比較に際しては、サンプラー８の出力信
号および切替式分周器６の出力信号に必要に応じてリタ
イミングを施こし基準信号発生器１の基準信号のタイミ
ングに両信号の位相を正確に一致させる。Next, the output signal of the switching frequency divider 6 and the output signal of the sampler 8 are supplied to the phase frequency detector 2, and the phases and frequencies of both are compared. At the time of comparison, the output signal of the sampler 8 and the output signal of the switchable frequency divider 6 are re-timed as necessary to accurately match the phases of both signals with the timing of the reference signal of the reference signal generator 1.
位相周波数比較器２の出力検出誤差信号は電圧制御発振
器３の周波数制御端子へ負帰還され電圧制御発振器３の
出力周波数を所要の周波数に安定化する。周波数ｆＯは
（１），（４），（５）より のいづれかの周波数に安定化される。The output detection error signal of the phase frequency comparator 2 is negatively fed back to the frequency control terminal of the voltage controlled oscillator 3 to stabilize the output frequency of the voltage controlled oscillator 3 to a required frequency. The frequency f O is from (1), (4), (5) It is stabilized at either frequency.
具体的数字を与えてみる。Give a specific number.
ｍ＝2,Ａ＝127,ｎ=81，ｆＲ＝ 300ＭＨｚとするとｐ＝
3,ｆＯ＝ 727ＭＨｚとなる。If m = 2, A = 127, n = 81, f R = 300 MHz, p =
3, f O = 727 MHz.
ｍ＝2, ｆＲ＝ 300ＭＨｚとするとｐ＝3,ｆＯ＝ 728ＭＨｚとな
り、この例ではｐ＝3 であるからＡを１ずつ増加又は減
少させた時ｎを３ずつ増加又は減少させると１ＭＨｚス
テップで周波数を変更できる事が解る。m = 2, When f R = 300 MHz, p = 3, f O = 728 MHz, and in this example, p = 3. Therefore, when A is increased or decreased by 1, n is increased or decreased by 3 and the frequency is changed in 1 MHz steps. I know what I can do.
次にｆＯの初期値は電圧制御発振器の発振可能周波数域
を適当に選ぶ事により固定するかあるいは電圧制御発振
器の周波数制御端子に位相周波数検出器の出力信号に重
畳して、別に用意した電圧を供給するかにより固定する
事ができる。Next, the initial value of f O is fixed by appropriately selecting the oscillating frequency range of the voltage controlled oscillator, or by superimposing the output signal of the phase frequency detector on the frequency control terminal of the voltage controlled oscillator, a separately prepared voltage is prepared. It can be fixed by supplying
電圧制御発振器の出力信号ｆＯが安定化された状態では
位相周波数検出器２へ供給されるサンプラー８の出力信
号および切替式分周器６の出力信号には両入力信号が非
常に低い周波数成分を有しているにもかかわらず常に両
信号間に位相差がなく位相周波数検出器２の出力検出誤
差信号に低周波成分が現われず出力検出誤差信号は完全
に零となる。但し位相周波数検出器の位相検出精度はサ
ンプラー８のサンプリング周期で決定され大略 単位である為、十分な検出精度を得るにはｆＲ》ｆＱで
ある必要がある。When the output signal f O of the voltage controlled oscillator is stabilized, the output signal of the sampler 8 and the output signal of the switchable frequency divider 6 supplied to the phase frequency detector 2 have a very low frequency component of both input signals. However, there is always no phase difference between the two signals, no low frequency component appears in the output detection error signal of the phase frequency detector 2, and the output detection error signal becomes completely zero. However, the phase detection accuracy of the phase frequency detector is generally determined by the sampling period of the sampler 8. Since it is a unit, it is necessary that f R >> f Q in order to obtain sufficient detection accuracy.
出力周波数の設定は電圧制御発振器３の出力周波数ｆＯ
の初期値によりｍを、制御器７により切替式分周器６の
分周数ｐ，ｐ−１切替を行なうフレーム長Ａ、変更回数
ｎを設定する事により行なう。The output frequency is set by the output frequency f O of the voltage controlled oscillator 3.
Is set by the controller 7, and the controller 7 sets the frequency division number p, p-1 of the switching frequency divider 6 and the frame length A at which the switching is performed, and the number of changes n.
（発明の効果） 本発明の周波数シンセサイザは以上述べたような構成と
作用を有することにより次のような効果を有する。第１
に構成が簡単であり、第２に、本発明による周波数シン
セサイザは位相周波数比較周波数がfR/pより小さくなら
ない為、ｐを適当に選べば位相比較周波数を高く設定で
きる。(Effects of the Invention) The frequency synthesizer of the present invention has the following effects by having the configuration and operation as described above. First
Second, the frequency synthesizer according to the present invention does not have a phase frequency comparison frequency smaller than f R / p. Therefore, the phase comparison frequency can be set high by appropriately selecting p.
従って位相同期ループのループ帯域幅をfR/pを越えない
範囲で広くする事が可能で結果として電圧制御発振器の
位相雑音を十分圧縮する事が可能となる。第３に、本発
明による周波数シンセサイザはサンプラーを使用し電圧
制御発振器の出力信号周波数を低い周波数に分周ではな
く周波数変換により置換している為、従来の周波数シン
セサイザのように分周により位相雑音特性が劣化する事
が無く、小さな周波数可変ステップの周波数シンセサイ
ザを構成しても良好な位相雑音特性が得られるという利
点がある。Therefore, the loop bandwidth of the phase locked loop can be widened within a range not exceeding f R / p, and as a result, the phase noise of the voltage controlled oscillator can be sufficiently compressed. Thirdly, since the frequency synthesizer according to the present invention uses a sampler to replace the output signal frequency of the voltage controlled oscillator with a low frequency by frequency conversion instead of frequency division, phase noise is generated by frequency division like a conventional frequency synthesizer. The characteristics are not deteriorated, and there is an advantage that a good phase noise characteristic can be obtained even if a frequency synthesizer having a small frequency variable step is configured.
第１図は本発明の周波数シンセサイザの構成を示すブロ
ック図、第２図は従来の周波数シンセサイザの構成を示
すブロック図である。 １……基準信号発生器、２……位相周波数検出器、３…
…電圧制御発振器、４……固定分周器、５……可変分周
器、６……切替式分周器、７……制御器、８……サンプ
ラー。FIG. 1 is a block diagram showing the configuration of a frequency synthesizer of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional frequency synthesizer. 1 ... Reference signal generator, 2 ... Phase frequency detector, 3 ...
… Voltage controlled oscillator, 4 …… Fixed divider, 5 …… Variable divider, 6 …… Switchable divider, 7 …… Controller, 8 …… Sampler.
Claims (1)
電圧制御発振器と；基準周波数信号を発生する基準信号
発生器と；前記電圧制御発振器の出力信号を前記基準信
号発生器の出力信号でサンプリングするサンプラーと；
前記基準信号発生器の出力信号を分周する分周器であっ
て、その分周数が制御信号により２値以上に切り替えら
れる切替式分周器と；前記電圧制御発振器の出力周波数
がｆＯ、前記基準信号発生器の出力周波数がｆＲである
とき式｜ｆＯ−ｍｆＲ｜≦ｆＲ／２を満足する正の整数
ｍが定まったときに、ｆＲ／｜ｆＯ−ｍｆＲ｜で表され
る数の直近上位の整数をｐとしたとき、前記サンプラー
の出力信号の周期がｐ／ｆＲのときにはｐを、同出力信
号の周期が（ｐ−１）／ｆＲのときにはｐ−１をそれぞ
れ分周器の分周数とするための制御信号を前記切替式分
周器へ供給する制御器と；前記サンプラーからのサンプ
リング出力信号と前記切替式分周器の分周出力とを受け
て両者を比較し、その誤差出力信号を周波数制御電圧と
して前記電圧制御発振器へ負帰還を形成するように供給
する位相周波数検出器又は位相検出器と；を有すること
を特徴とする周波数シンセサイザ。1. A voltage controlled oscillator whose oscillation frequency is controlled by a control voltage; a reference signal generator for generating a reference frequency signal; and an output signal of the voltage controlled oscillator sampled by an output signal of the reference signal generator. With sampler;
A frequency divider for dividing the output signal of the reference signal generator, wherein the frequency division number is switched to a binary value or more by a control signal; and an output frequency of the voltage controlled oscillator is f O When the output frequency of the reference signal generator is f R , when a positive integer m that satisfies the expression | f O −mf R | ≦ f R / 2 is determined, f R / | f O −mf R When the nearest upper integer of the number represented by | is p, when the period of the output signal of the sampler is p / f R , p is obtained, and when the period of the output signal is (p−1) / f R , a controller that supplies a control signal to the switchable frequency divider for making p-1 the frequency division number of each frequency divider; a sampling output signal from the sampler and a frequency division output of the switchable frequency divider Then, the two are compared and the error output signal is used as the frequency control voltage. Frequency synthesizer, characterized in that it comprises a; serial and voltage controlled phase frequency detector for supplying as an oscillator to form a negative feedback or phase detector.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60194093A JPH0659030B2 (en) | 1985-09-03 | 1985-09-03 | Frequency synthesizer |
| CA000517270A CA1260563A (en) | 1985-09-03 | 1986-09-02 | Frequency synthesizer of a phase-locked type with a sampling circuit |
| US06/903,212 US4679004A (en) | 1985-09-03 | 1986-09-02 | Frequency synthesizer of a phase-locked type with a sampling circuit |
| EP86112180A EP0213636B1 (en) | 1985-09-03 | 1986-09-03 | Frequency synthesizer of a phase-locked type with a sampling circuit |
| AU62193/86A AU583775B2 (en) | 1985-09-03 | 1986-09-03 | Frequency synthesizer of a phase-locked type with a sampling circuit |
| DE8686112180T DE3684839D1 (en) | 1985-09-03 | 1986-09-03 | FREQUENCY SYNTHESISER TYPE OF A PHASE CONTROL LOOP WITH A SAMPLE CIRCUIT. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60194093A JPH0659030B2 (en) | 1985-09-03 | 1985-09-03 | Frequency synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6253520A JPS6253520A (en) | 1987-03-09 |
| JPH0659030B2 true JPH0659030B2 (en) | 1994-08-03 |
Family
ID=16318829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60194093A Expired - Lifetime JPH0659030B2 (en) | 1985-09-03 | 1985-09-03 | Frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0659030B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0485259U (en) * | 1990-11-30 | 1992-07-24 | ||
| JP5202631B2 (en) * | 2007-07-23 | 2013-06-05 | テラダイン、 インコーポレイテッド | Phase lock on spurious signal frequency |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS509360A (en) * | 1973-05-23 | 1975-01-30 | ||
| JPS5846586Y2 (en) * | 1976-07-01 | 1983-10-24 | 株式会社東芝 | Circuit with phase locked loop |
-
1985
- 1985-09-03 JP JP60194093A patent/JPH0659030B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6253520A (en) | 1987-03-09 |
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