JP5202631B2 - Phase lock on spurious signal frequency - Google Patents

Description

  The present invention relates generally to automated test equipment for electronics, and more particularly to techniques for generating periodic signals for testing electronic devices.

Electronics manufacturers typically use automated test equipment (ATE) to test semiconductor components and electronic assemblies. ATE reduces costs to manufacturers by allowing products to be tested early in the manufacturing process. The initial test is
Allow defective units to be identified and discarded before incurring significant additional costs. In addition, ATE allows manufacturers to rate different units according to their tested performance levels. A better performing unit can generally be sold at a higher price.

  One of the basic functions of ATE is to generate a signal having a predetermined frequency. These signals can include, for example, digital clocks, analog waveforms, and RF waveforms. Often, certain test scenarios require the test system to create multiple signals of different frequencies. In general, the frequency and phase differences between different signals must be accurately controlled. Phase-locked loops are commonly used in ATE systems to create signals with precisely controlled frequency and phase.

FIG. 1 shows a block diagram of a conventional phase locked loop (PLL) 100. PLL100 receives an input signal _{F IN,} and generates an output signal _{F OUT.} The PLL 100 includes a phase detector 110, a loop filter 112, and a voltage controlled oscillator (VCO) 114. It also includes an output frequency divider 118 and a feedback frequency divider 116. Input signal F _IN may be supplied by any suitable source, such as a crystal oscillator.

The conventional PLL 100 is a closed loop feedback system that operates essentially as follows. The phase detector 110 generates an error signal that varies in relation to the difference in phase between the by comparing the input signal _{F IN} and feedback signal _{F FB F IN} and _{F FB.} The loop filter 112 smoothes the error signal and generally helps stabilize the feedback loop. The VCO 114 converts the output signal of the filter into a vibration signal F _VCO having a frequency that varies in relation to the output signal of the filter. The feedback divider 116 (generally a counter) divides the frequency of the F _VCO by an integer M to create a feedback signal F _FB . Outside the loop, output divider 118 divides the F _VCO frequency by an integer N to create F _OUT . Since feedback tends to drive the difference between F _IN and F _FB to zero, it therefore drives the frequency of the F _VCO to a value equal to the frequency of F _IN * M, and thus the frequency of the output signal F _OUT is F _IN *. There is a tendency to drive to a value equal to the frequency of M / N.

The conventional PLL 100 provides many benefits. For example, the output frequency F _OUT can be varied over a wide range of values through appropriate selection of N and M. In addition, phase noise during PPL can generally be reduced by setting the bandwidth of the loop filter 112 to any low value.

  Nevertheless, we are aware of several shortcomings of PLL 100 that limit its usefulness in many ATE applications. High frequency applications such as RF signal generation require high frequency VCOs. The speed of the VCO in these applications is often much higher than the speed of the phase detector. This problem is conventionally addressed by making the value of M in the feedback divider 116 very large.

However, increasing the value of M involves several drawbacks. For example, the larger the value of M, the greater the reduction in the open loop gain of the PLL 100. As is known, reducing open loop gain increases loop tracking error. It also impairs the ability to reject loop noise. To portray this effect, not only does the feedback divider 116 divide the frequency of the F _VCO by M, but also considers any deformation (ie, phase noise, or equivalently timing jitter) to divide by the same value of M. . Sensitivity is therefore reduced.

  The frequency divider 16 also adds noise directly. A frequency divider is generally implemented as a counter, which is known to produce spurious noise at its output. Although this noise can be attenuated by the loop filter 112, attenuation is generally achieved without setting the loop filter bandwidth to a frequency well below the harmful noise component of the divider 116. I can't. Reducing bandwidth to this extent, however, has the effect of reducing the programming speed of PLL 100, which can have a negative impact on ATE system performance and throughput.

  What is desired is a phase lock circuit that can create high frequency signals with low phase noise without sacrificing programming speed.

  In accordance with the present invention, the phase lock circuit employs a sampler that produces a false signal (aliased) feedback signal, and the circuit is adapted to lock thereon.

  The following description will be better understood with reference to the following drawings.

FIG. 1 is a block diagram of a conventional phase locked loop operable to create a wide range of frequencies. FIG. 2 is a block diagram of a phase lock circuit according to an illustrative embodiment of the invention. FIG. 3 is a frequency plot showing how a higher frequency than the Nyquist rate can be spurious into a lower frequency than the Nyquist rate in the circuit of FIG. FIG. 4 is a frequency plot showing how a higher frequency band than the Nyquist rate can be spurious into a lower frequency band than the Nyquist rate in the circuit of FIG. FIG. 5 is a simplified overview of a descriptive embodiment of a phase lock circuit in which harmonics of the VCO output signal are employed to improve accuracy. FIG. 6 is a frequency plot showing how the various harmonic bands are created in the circuit of FIG. 5, where one or more harmonic bands are spurious to a lower frequency than the Nyquist rate. Yes. FIG. 7 is a block diagram illustrating an illustrative embodiment of a phase lock circuit employing a digital phase detector and a digital loop filter. FIG. 8 is a simplified block diagram of an automated test facility that includes a phase lock circuit in accordance with one or more embodiments of the invention. FIG. 9 is a block diagram of a digital phase detector suitable for use with the phase lock circuit of FIG. FIG. 10 is a block diagram of another digital phase detector suitable for use with the phase lock circuit of FIG.

FIG. 2 shows an illustrative embodiment of a phase lock circuit 200. Phase lock circuit 200 receives an input signal _{F IN,} to produce an output signal _{F OUT.} The circuit 200 includes a controllable oscillator such as a sampler 202, a phase detector 210, a loop filter 212, and a VCO (voltage controlled oscillator) 214. Sampler 202 receives feedback signal F _FB as its input and provides sample feedback signal SF _FB as its output. Phase detector 210 has two inputs and one output. The first input receives the input signal F _IN, the second input receives a sample feedback signal SF _FB. Loop filter 212 and VCO 214 each have one input and one output.

Circuit 200 also includes a circuit path 220 that provides a feedback signal F _FB coupled from the output of VCO 214 to the input of sampler 202. Bandpass filters 230 a-230 n are preferably provided in the circuit path 220. These bandpass filters are preferably individually selectable via switches 240a-240n. Each filter preferably has a different center frequency.

During operation, the sampler 202 is adapted to sample the feedback signal F _FB at the sampling rate F _S. The phase detector 210 receives the sample feedback signal SF _FB and outputs an error signal Φ-Err. Error signal varies according to the difference between the _{SF FB} and _{F IN.} Loop filter 212 filters the error signal and helps stabilize the loop. The VCO 214 converts the filtered error signal into a vibration waveform F _VCO . The frequency of the F _VCO varies with the level of the filtered error signal.

One of the bandpass filters 230a-230n is selected to filter noise from the F _VCO . The selected filter preferably has a center frequency that is closest to the expected frequency of the F _VCO . The desired filter is selected by closing its associated switch (one of 240a-240n) and opening the remaining switches.

Circuit _200, the frequency of _{F VCO} behave in an essentially normal manner when less than the Nyquist rate of the sampler _(F S / 2). However, significant differences occur when the F _VCO frequency is greater than the Nyquist rate.

As is known, when a signal sampled at a rate F _S contains frequency components greater than F _S / 2, a phenomenon called “false signalization” occurs in a discrete time system. False signaling causes out-of-band frequencies, such as those above the Nyquist rate, to appear as images within the system bandwidth. These images are usually considered as errors. However, we have recognized that these false signaled images can be used to improve performance.

FIG. 3 shows a frequency plot of a discrete time system sampled at a rate F _S. The horizontal line represents the frequency, with zero frequency (DC) appearing to the left and increasing frequency extending to the right. The frequency is expressed as a multiple of Nyquist rate F _S / 2. As shown, frequencies above the Nyquist rate create false signaled images within the system bandwidth (ie, below the Nyquist rate). In particular, any component that is greater than any multiple of Nyquistrate by an increment δ creates a false signaled image at frequency δ within the system bandwidth.

The creation of a false signaled image has significant consequences in the phase lock circuit of FIG. When the frequency of the F _VCO exceeds F _S / 2, a spurious signal image of that frequency appears within the sampler bandwidth and the circuit is allowed to lock onto the image. This means that the phase lock circuit 200 can operate with substantial gain without requiring a frequency divider in its feedback path. The circuit 200 can be made to create any high frequency, limited only by its analog characteristics.

If the VCO 214 operates over a frequency range that is too large, ambiguity in the output frequency can occur. For example, if the output range (maximum frequency minus minimum frequency) exceeds F _S / 2, the phase lock circuit may be able to satisfy its feedback condition at two or more different VCO frequencies. Preferably, this condition is avoided by limiting the bandwidth of each of the bandpass filters 230a-230n to less than F _S / 2. Alternatively, it may be avoided by selecting a VCO 214 having an output range that is less than F _S / 2.

  Significant performance benefits arise from using spurious signals in the phase lock circuit 200. These are best understood with reference to FIG.

FIG. 4 is a frequency plot showing the effect of pseudo-signaling on the frequency band. As shown, the frequency band or range 410 above the Nyquist rate is false signaled to create a mirror image 412 within the system bandwidth. Importantly, the bands 410 and 412 have the same width. If band 410 is 1 kHz wide, band 412 will be 1 kHz wide. Assuming that band 410 represents the frequency created by VCO 214, the width of band 410 can be viewed as phase noise (or equivalently timing jitter) in the F _VCO . In the conventional phase-locked loop of FIG. 1, the feedback divider would have reduced the width of band 410, effectively reducing loop gain and sensitivity. In the phase lock circuit of FIG. 2, however, the loop gain and sensitivity are retained. Phase noise around the F _VCO returns spuriously back into the system bandwidth without compression or attenuation.

The use of the spurious signal thus allows the phase lock circuit 200 to be operated at high gain (where F _OUT is much greater than F _IN ) without the need for a feedback divider. It allows the open loop gain and hence accuracy to be kept high. Since no feedback divider is required, the noise spurs normally introduced by these devices are avoided. Thus, the need to slow down the loop filter and consequently suffer from reduced programming speed is also avoided.

  FIG. 5 shows another illustrative embodiment of a phase lock circuit. The phase lock circuit 500 includes a sampler 502, a phase detector 510, a loop filter 512, a controllable oscillator such as a VCO 514, and a bank of bandpass filters 530. These are similar to the sampler 202, phase detector 210, loop filter 212, VCO 214, and bandpass bank of FIG. However, circuit 500 also includes a harmonic generator 540.

Harmonic generator 540 receives the filtered version of the F _VCO and generates one or more harmonics of the signal. These harmonics or harmonics have a frequency that is an integral multiple of the frequency of the F _VCO , ie the fundamental frequency.

  A second bandpass bank 550 is optionally coupled to the output of the harmonic generator 540. The second bandpass bank 550 may be used to select one or more specific harmonics to be presented to the sampler 502. However, the selection of specific harmonics is not required.

  The harmonic generator 540 effectively multiplies the width of the noise band fed back to the sampler 502. It therefore further increases the open loop gain and sensitivity of the phase loop circuit 500.

FIG. 6 is a frequency plot showing the mechanism by which phase noise is multiplied. As shown, the F _VCO and its harmonics produce false signaled images within the system bandwidth. Importantly, it can be seen that the width of the phase noise band around each harmonic of the F _VCO varies in proportion to the harmonic order. For example, the noise band around the 3F _VCO is three times wider than the band around the F _VCO . Each of these bands is spurious back to the system bandwidth. Without the bandpass bank 550, all these spurious signal bands appear simultaneously at the input of the sampler 502.

  The elements of the phase lock circuit 200/500 can be implemented in a wide variety of ways. Phase detector 210/510 can be an analog phase detector or a digital phase detector. Similarly, the loop filter 212/512 can be an analog loop filter or a digital loop filter. Analog and digital phase detectors and loop filters are well known in the art.

If an analog phase detector is used, the sampler 202/502 is implemented as an analog sampling circuit such as a sample and hold circuit or a track and hold circuit. These devices are well known and are readily available from inventory. In this arrangement, the input signal _FIN is preferably an analog signal, such as the output of a crystal oscillator.

If a digital phase detector is used, the sampler 202/502 preferably includes an analog sampling circuit (described above) coupled to an analog-to-digital converter (ADC). Both analog sampling circuit and ADC is clocked at _{F S.} Preferably, a sampling ADC is used, i.e. both the analog sampling circuit and the ADC are contained in a single device package. The digital value is thus provided to the phase detector at the rate F _S. In this arrangement, _FIN is preferably a digital signal.

  VCO 214/514 is preferably conventional. VCOs are well known and are commercially available from inventory.

  Harmonic generator 540 is preferably implemented as a non-linear analog circuit such as a clip circuit or a commercially available RF comb generator. As is known, the clipping circuit flattens the positive and negative peaks of the sine wave, thus introducing harmonics of the fundamental frequency of the sine wave. Optionally, the harmonic generator 540 may comprise an amplifier for boosting low amplitude harmonics.

  FIG. 7 shows a primarily digital embodiment of a phase lock circuit 700 with a particular arrangement of elements. The circuit includes a digital phase detector 710 and a sampling ADC 712.

The digital phase detector 710 receives input data F _REF and Φ _REF indicating a reference frequency and a reference phase. Digital phase detector 710 compares this reference frequency and phase with the sample feedback signal from sampling ADC 712 to create a digital phase error. The digital loop filter 714 filters the digital phase error, and the digital-to-analog converter (DAC) converts the filtered phase error into an analog signal. An analog filter smoothes the output of the DAC 716, and the VCO 720 converts the smoothed DAC output into a vibration signal. The first bandpass filter bank 722, the harmonic generator 730, and the optional second bandpass bank 740 are the first bandpass bank 530, the harmonic generator 540, and the optional second bandpass bank 740 of FIG. It operates essentially the same as described above in connection with the bandpass bank 550.

Digital loop filter 714 provides certain advantages in circuit 700. If any circuit element such as ADC 712 or DAC 716 is found to generate noise repeatably at a known frequency, or noise at a known frequency is injected into the circuit from its environment. For example, the digital loop filter 714 can be programmed to have a low gain or “zero” at each harmful noise frequency. Designing the loop filter 714 in this manner reduces noise in the output signal F _OUT and contributes to the overall accuracy of the circuit.

FIG. 9 shows an example of a digital phase detector that is particularly suitable for the phase lock circuit 700. As shown in FIG. The first input of the digital phase detector is coupled to the digital oscillator 914 and the second input of the digital phase detector is coupled to the down converter 910. Based on the input data (F _REF , φ _REF ), the digital oscillator 914 synthesizes a digital reference signal having a frequency F _OSC and a phase φ _OSC . F _OSC is preferably equal to F _REF and φ _OSC is preferably equal to φ _REF .

The digital reference signal is preferably a quadrature reference signal, ie it is provided in two parts representing two sine waves separated by a 90 degree phase difference. Conventionally, the first part of the quadrature reference signal is called cosine and the second part is called sine. Thus, the first portion of the orthogonal phase reference signal has the form Cos (2πF _OSC t + φ _OSC ) and the second portion has the form Sin (2πF _OSC t + φ _OSC ).

The direct phase reference signal is provided to the downconverter 910 where it is mixed with the feedback signal. Taking the digital phase detector out of the context of the phase lock circuit 700, the feedback signal can be more generally regarded as a sample period signal having the form Cos (2πF _IN t + φ _IN ).

The down converter 910 creates a difference signal according to the sample period signal and the quadrature reference signal. The differential signal is preferably a quadrature signal having two parts, one part having substantially the form Cos [2π (F _IN −F _OSC ) t + φ _IN −φ _OSC ], the other part being substantially In particular, it has the form Sin [2π (F _IN −F _OSC ) t + φ _IN −φ _OSC ] Accordingly, the frequency of the quadrature difference signal is equal to the difference F _IN −F _OSC between the input and the oscillator frequency, and the phase of the quadrature difference signal is equal to the difference φ _IN −φ _OSC between the input and the oscillator phase.

The quadrature difference signal is provided to a phase extractor 916. Phase extractor 916 generates a cumulative phase difference represented by the quadrature phase difference signal. In the preferred embodiment, the phase extractor 916 performs an ATAN2 function. As is known, ATRAN2 generates a four-quadrant inverse tangent of the quotient of two inputs. When the two inputs to ATRAN2 are the sine and cosine of the same angle θ, ATAN2 [sin (θ), cos (θ)] is simply the angle θ. Therefore, ATAN2 of the two parts of the quadrature difference signal is evaluated as [2π (F _IN −F _OSC ) t + φ _IN −φ _OSC ]. This value corresponds to the cumulative phase difference between the digital oscillator 914 and the sample period signal. If F _IN , F _OSC , φ _IN and φ _OSC are constants, the value described by the cumulative phase difference takes the form of a straight line over time.

In the context of phase lock circuit 700, the accumulated phase difference created by phase extractor 916 provides a digital phase error. Optionally, phase φ _ADJ is added to or subtracted from the accumulated phase difference via adder 920 to adjust the phase error passed to other components of phase lock circuit 700. Adding or subtracting the phase via the adder 920 has the effect of shifting the phase of the output signal F _OUT of the synthesizer.

In order for the digital phase detector of FIG. 9 to perform properly, the digital oscillator 914 should be able to generate an accurate quadrature reference signal. For example, F _OSC should be substantially equal to the frequency specified by F _REF (nominally F _OSC and F _REF are equal) and φ _OSC must be substantially equal to the phase specified by φ _REF . (Nominally φ _OSC and φ _REF are equal). This requirement places considerable demands on the digital oscillator 914 as it requires that the exact value of the quadrature reference signal be created quickly and at the required sampling rate.

This requirement can be achieved relatively easily if F _OSC and F _S are related such that K / F _OSC = L / F _S , where K and L are both integers. In this case, the digital oscillator 914 can employ a lookup table for generating a quadrature reference signal. The look-up table associates prestored values of the quadrature reference signal with successive cycles of the sample clock. The digital oscillator can thus generate a quadrature reference signal simply by cycling through the values stored in its lookup table.

However, if _{K / F OSC} is not equal to L / _{F S,} the situation is more complicated. Under this circumstance, a simple lookup table cannot be used because the appropriate value for one iteration of the lookup table becomes inappropriate for the other iterations. Different solutions are required. One solution is to provide the digital oscillator 914 with a calculation engine to quickly and quickly calculate the value of the quadrature reference signal. However, this solution is complicated.

  Another solution is shown in FIG. 10, which shows another example of a suitable digital phase detector 710. The down converter 1010, the phase extractor 1016, and the adder 1020 in FIG. 10 are substantially the same as the down converter 910, the phase extractor 916, and the adder 920 in FIG. However, FIG. 10 also includes a calculation unit 1012, an accumulator 1018, and a second adder 1022.

The calculation unit 1012 divides the input data (F _REF , φ _REF ) into two parts, a primary part and a secondary part. The primary part (F _OSC , φ _OSC ) represents an approximation of the reference signal (F _REF , φ _REF ) that can be easily generated as the digital oscillator 1014 uses a look-up table. The secondary part (φ _RES ) represents the residual phase value, that is, the error in the approximation. The primary part preferably satisfies the requirement of K / F _OSC = L / F _S. If F _OSC is not equal to F _REF , the _convention is that K and L are preferably selected such that F _OSC is slightly greater than F _REF . Therefore, the secondary part φ _RES represents the phase difference between F _OSC and F _REF that occurs on each cycle of F _S.

Accumulator 1018 accumulates φ _RES on each cycle of F _S (ie, appends to its own content). The value held by accumulator 1018 thus takes the form of a straight line when viewed over time.

The output of the phase extractor 1016 does not take into account the secondary part of the input data. Adder 1022 modifies this output by subtracting the output of accumulator 1018 from the output of phase extractor 1016. The output of adder 1022 thus takes into account both the primary and secondary parts of the input data and creates an accurate representation of the phase error between the sample period signal and the reference (ie, F _REF , φ _REF ). .

  Some elements of the digital phase detector of FIGS. 9 and 10, such as the ATAN2 function and accumulator 1020, have commercially available logic definitions. These definitions can be purchased, downloaded, or embedded in an FPGA or ASIC with little or no proprietary design work.

The reference data (F _REF , φ _REF ) is preferably variable. When the digital phase detector of FIGS. 9 and 10 is used in a synthesizer, the reference data is preferably programmable to establish different output frequencies. The values of the integers K and L are preferably updated each time a new value of reference data is programmed. In order to minimize the size of the remainder, K is preferably made as large as practicable. K and L may be calculated manually or generated by software, firmware, or hardware based on the desired output frequency and sampling rate.

Although they are not required, the digital phase detectors of FIGS. 9 and 10 provide many advantages in the phase lock circuit 700. For example, the phase error is updated as frequently as once every cycle of the sample clock. In addition, the phase error has a very high resolution. Since the phase remainder φ _RES is managed independently of the primary part of the reference frequency, a number of bits with numerical accuracy can be applied to φ _RES . Also, the contribution of φ _{RES to} the overall phase error is to increase the number of F _OSC cycles (ie, the value of K) stored in the look-up table used to implement the digital oscillator 1014. Therefore, it can be made very small.

  FIG. 8 shows an application of a phase lock circuit of the type shown in FIGS. As shown in FIG. 8, the automated test system 812 is controlled by a host computer 810 for testing a UUT (Under Test Unit) 840. The UUT may be any type of device or assembly to be tested. Automated test system 812 includes devices such as analog device 820, digitizer 822, and arbitrary waveform generator (AWG) 824. The automated test system 812 also includes a plurality of digital electronic channels, indicated generally as digital PINs 826, 828, and 830. The digital electronic channel is arranged for supplying and sensing digital signals.

Notably, automatic test system 812 includes a plurality of phase lock circuits 816a-g. These phase lock circuits are of the same general type shown in any of FIGS. Each phase lock circuit 816a-g receive a clock signal _{F S} from the system clock 814. They also each receive a respective input signal (or data) from the host computer 810 that specifies the desired output frequency and phase. In response to the clock and the respective inputs, each of the phase lock circuits 816a-g generates a respective periodic output signal. Output signals are provided to instruments 820, 822 and 824, which can use a frequency reference or clock for their normal operation. The output signal also provides a clock for controlling the digital PINs 826, 828 and 830. They may also be used to provide a frequency reference for the pattern generator 818. The pattern generator 818 operates in conjunction with a phase lock circuit to cause the digital PIN to be supplied and / or sensed at a precisely controlled instant in a specified format.

  While several embodiments of the invention herein have been described, numerous alternative embodiments or variations can be made. For example, the phase lock circuit shown and described preferably includes a bank of bandpass filters (230, 530, and 722) coupled to the output of the VCO, although these filters are not strictly required. In addition, the bandpass filter is preferably implemented as an analog filter preceding the sampler (202, 502) or sampling ADC (712), which is alternatively a digital filter provided at the output of the sampler or sampling ADC. Can be implemented as:

A particular advantage of the disclosed phase lock circuits is that they provide closed loop frequency gain without requiring a frequency divider (such as a counter) in their feedback path. However, this should not be taken to mean that the feedback divider is prohibited. There may be several cases where a feedback divider may be desirable in the context of the disclosed circuit. _Spoofing is greater than the overall frequency gain (output frequency divided by the input frequency) of the circuit path between the VCO and the sampler is F _S / 2F _MIN , where F _MIN represents the lowest frequency provided by the VCO. This will happen even if there is a feedback divider.

The sampling rate F _S at which the sampler (202, 502) or sampling ADC (712) is operated is preferably fixed. However, this is not required. It may be variable. According to one variant, F _S may be derived from the output of the VCO.

As shown and described. VCO is being adapted to operate at frequencies higher than the Nyquist rate (F S _{/ 2),} which demand is not. Spurious signaling will also occur at VCO frequencies below the Nyquist rate if the harmonic generator (540, 730) creates harmonics above the Nyquist rate.

  Those skilled in the art will therefore appreciate that various changes in form and detail may be made to the embodiments disclosed herein without departing from the scope of the invention.

Claims (25)

A sampler having an input and an output and constructed and arranged to operate at a sampling rate FS;
A phase detector having an input and an output, the input coupled to the output of the sampler;
A controllable oscillator having an input and an output, the input coupled to the output of the phase detector;
A circuit path that is coupled from the output of the controllable oscillator to the input of the sampler and is constructed and arranged to deliver a feedback signal having a frequency greater than FS / 2 to the sampler ;
The circuit path includes a bank of bandpass filters;
A phase lock circuit, wherein the bank of bandpass filters includes a plurality of bandpass filters, each having a different center frequency and each having a bandwidth less than FS / 2.   The phase lock circuit of claim 1, wherein the controllable oscillator is operable to generate an output signal having a frequency greater than FS / 2.   The phase lock circuit of claim 1, wherein the input of the phase detector is a first input and the phase detector further has a second input arranged to receive the oscillating analog signal.   The phase lock circuit of claim 1, wherein the input of the phase detector is a first input and the phase detector further has a second input arranged to receive a digital value indicative of the desired output frequency.   The phase locked circuit of claim 1, wherein the circuit path includes a non-linear element constructed and arranged to generate at least one harmonic of a signal generated by the controllable oscillator.   6. The phase lock circuit according to claim 5, wherein the nonlinear element is one of a clip circuit and a frequency comb generator.   The phase-locked circuit of claim 5, wherein the circuit path further comprises a bank of selectable bandpass filters coupled between the output of the controllable oscillator and the nonlinear element.   The phase lock circuit of claim 1, further comprising a loop filter coupled between the output of the phase detector and the input of the controllable oscillator.   The phase lock circuit of claim 8, wherein the loop filter comprises a digital loop filter. A sampler having an input and an output;
A phase detector having an input and an output, the input coupled to the output of the sampler;
A controllable oscillator having an input and an output, the input coupled to the output of the phase detector;
A harmonic generator coupled between the output of a controllable oscillator that outputs a signal having a frequency greater than FS / 2 and the input of a sampler sampled at FS ;
A bank of bandpass filters coupled between the controllable oscillator and the harmonic generator;
A phase lock circuit, wherein the bank of bandpass filters includes a plurality of bandpass filters, each having a different center frequency and each having a bandwidth less than FS / 2.   The phase locked circuit of claim 10 further comprising a bank of selectable bandpass filters coupled between the harmonic generator and the sampler.   The phase locked circuit of claim 10 further comprising a bank of selectable bandpass filters coupled between the harmonic generator and the sampler.   The phase-locked circuit of claim 10, wherein the harmonic generator includes a non-linear element.   The phase lock circuit of claim 10, wherein the sampler is operable at a sampling rate FS and the harmonic generator is constructed and arranged to generate at least one harmonic having a frequency greater than FS / 2. Generating a vibration signal having a fundamental frequency and having at least one component having a frequency greater than FS / 2;
Sampling the vibration signal at a sampling rate FS to generate a sample signal having at least one false signal component;
Generate a phase error according to the difference between the sample signal and the reference signal,
Varying the fundamental frequency of the vibration signal in response to the phase error,
Generating the vibration signal comprises:
Including bandpass filtering the vibration signal;
A phase-locking method wherein a bank of bandpass filters used for the bandpass filtering includes a plurality of bandpass filters, each having a different center frequency and each having a bandwidth smaller than FS / 2. The method of claim 15 , wherein generating the vibration signal further comprises generating at least one harmonic of the bandpass filtered vibration signal. The step of generating the vibration signal is
16. The method of claim 15 , comprising generating at least one harmonic of the vibration signal. The method of claim 17 , further comprising bandpass filtering at least one harmonic of the vibration signal. The method of claim 15 , comprising filtering phase errors. The method of claim 19 , wherein filtering the phase error comprises digitally filtering the phase error. A host computer adapted to execute the test program;
A plurality of phase lock circuits that operate according to data from the host computer and generate a plurality of reference frequencies;
Coupled to a plurality of phase lock circuits, the stimulus signal is generated, and / or an automatic test system comprising, a plurality of devices configured to receive a signal that corresponds to the plurality of the reference frequency ,
Each of the plurality of phase lock circuits
A sampler having an input and an output and constructed and arranged to operate at a sampling rate FS;
A phase detector having an input and an output, the input coupled to the output of the sampler;
A controllable oscillator having an input and an output, the input coupled to the output of the phase detector;
A circuit path that is coupled from the output of the controllable oscillator to the input of the sampler and is constructed and arranged to deliver a feedback signal having a frequency greater than FS / 2 to the sampler ;
The circuit path includes a bank of bandpass filters;
The bank of bandpass filters includes a plurality of bandpass filters each having a different center frequency and each having a bandwidth less than FS / 2. The automatic test system of claim 21 , wherein the input of the phase detector is a first input and the phase detector further has a second input arranged to receive data indicative of the desired output frequency. The automated test system of claim 21 , wherein the plurality of devices includes digital drive circuits. The automated test system of claim 21 , wherein the plurality of instruments include analog sources. The automated test system of claim 21 , wherein the plurality of instruments includes an RF source.

Images