JP2853595B2 - PLL frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer.

[0002]

2. Description of the Related Art A PLL frequency synthesizer is used to generate a desired frequency in a radio or the like. Hereinafter, a conventional PLL frequency synthesizer will be described with reference to the drawings.

FIG. 4 is a block diagram of a basic form of a PLL frequency synthesizer.

This PLL frequency synthesizer comprises a voltage controlled oscillator 1 capable of changing an output frequency by a control voltage, a microcomputer 10 for instructing a frequency division number, and a voltage controlled oscillator 1 for a frequency division number designated by the microcomputer 10. , A reference signal oscillator 4 for generating a reference frequency, and a reference signal oscillator 4
Divides the output of the programmable counter 3 and the output of the reference divider 5
And a low-pass filter 7 for smoothing the output of the phase comparator 6 to provide a stable control voltage by generating a voltage corresponding to the phase difference.

This PLL frequency synthesizer is for automatically controlling the frequency generated by controlling the frequency division number in the programmable counter 3 by the microcomputer 10. However, in the PLL frequency synthesizer shown in FIG. 4, when it is desired to generate a high frequency by the voltage controlled oscillator 1, the operation of the programmable counter 3 becomes
There is a problem that it cannot follow the output signal of the voltage controlled oscillator 1 which is the input signal.

Therefore, a conventional PLL frequency synthesizer employs a prescaler method or a mixer method as a measure against this problem.

FIG. 5 shows a conventional prescaler type PLL.
FIG. 2 is a block diagram of a frequency synthesizer. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals.

The PLL frequency synthesizer of the prescaler system includes a prescaler (fixed frequency divider) 11 having a relatively simple structure and operating at a high speed in front of the programmable counter 3, and the frequency of a signal input to the programmable counter 3 is adjusted. I try to lower it.

FIG. 6 shows a conventional mixer type PLL.
FIG. 2 is a block diagram of a frequency synthesizer. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals.

This mixer-type PLL frequency synthesizer includes a mixer 12 and a local oscillator 13, and the mixer 1
2 and the output signal of the voltage controlled oscillator 1 and the local oscillator 1
The output signal of the programmable counter 3 is mixed to lower the frequency of the signal input to the programmable counter 3.

[0011]

One of the performances required for a PLL frequency synthesizer is a carrier-to-noise ratio (hereinafter referred to as "C / N ratio"). This is the ratio between the carrier, which is the main oscillation signal of the voltage controlled oscillator 1, and the noise, which is an unnecessary signal such as a sideband component.
A PLL frequency synthesizer with higher performance as the C / N ratio increases.

The PLL frequency synthesizer is a kind of negative feedback, and is always corrected by the output signal of the phase comparator 6 so that the two input signals of the phase comparator 6 have the same phase. This correction is always performed even when the output frequency of the PLL frequency synthesizer, that is, the output frequency of the voltage-controlled oscillator 1 is stable at a desired frequency, and the period of the correction is determined by the output signal of the reference divider 5. Every cycle.

From the viewpoint of improving the C / N ratio, it is better that the effect of this correction does not affect the output signal of the low-pass filter 7. Assuming that the characteristics of the low-pass filter 7 are constant,
The more frequently the correction is performed, that is, the higher the output frequency of the reference divider 5 is, the less the ripple of the effect of the correction is generated in the output signal of the low-pass filter 7, and the C / N ratio is improved.

However, the output frequency of the reference divider 5 is limited as described below.

In the basic PLL frequency synthesizer shown in FIG.
_VCO is represented by _Equation 1. In Equation 1, f _r is the output frequency of the reference divider 5, N is the division number of the programmable counter 3.

[0016]

[Number 1] may be changed frequency division number N of the programmable counter 3 to vary the output frequency of f _VCO = N × f _r voltage controlled oscillator 1, since N is generally a natural number, f _VCO is the f _r integer multiple becomes, therefore, the minimum step change in the output frequency of the voltage controlled oscillator 1 becomes f _r.

Here, a case where the PLL frequency synthesizer is a circuit for generating a reception frequency in a receiver for receiving a broadcast will be described as an example.

Considering the broadcasting station of the broadcast received by the receiver, this broadcasting station transmits a broadcast wave at a frequency of an interval determined for each predetermined band by the law of each country. Therefore, in order to receive these broadcasts, the output frequency of the reference divider 5 must be a divisor of each transmission frequency of all the broadcasts to be received. That is, as shown in Equation 2, the maximum value of the output frequency f _r of the reference divider 5 is limited so that the greatest common divisor f _GCM transmission frequency of the broadcast station.

[0019]

[Number 2] On the other hand f _r ≦ f _GCM, in the PLL frequency synthesizer of the prescaler system shown in FIG. 5, the output frequency f _VCO of the voltage controlled oscillator 1 is represented by the number 3. In Equation 3, f _r is the output frequency of the reference divider 5, N is the frequency division number of the programmable counter 3, M is the division number of the prescaler 11.

[0020]

Equation 3] where _{f VCO = M × N × f} r, the frequency variation steps Δf of the voltage controlled oscillator 1 when the dividing number N of the programmable counter 3 has 1 changed
_VCO is represented by _Equation 4.

[0021]

Equation 4] _{Δf VCO = (M × (N} + 1) × f r) - (M × N × f r) = M × f r The frequency change step Delta] f _VCO of the voltage controlled oscillator 1
Since limited to less than the greatest common divisor f _GCM transmission frequency of the broadcast station, as shown in Equation 5, the maximum value of the output frequency f _r of the reference divider 5, the transmission frequency of the broadcast station greatest common divisor f _GCM Is divided by the dividing number M of the prescaler 11.

[0022]

Equation 5 can be seen by comparing the f _r ≦ f _GCM / M number 5 and number 2, the PLL frequency synthesizer of the prescaler system from the PLL frequency synthesizer maximum value of the basic form of the output frequency f _r of the reference divider 5 Also becomes a small value, and as described above, the C / N ratio decreases.

On the other hand, in the mixer-type PLL frequency synthesizer shown in FIG. 6, the output frequency f _VCO of the voltage controlled oscillator 1 is expressed by the following equation (6). In Equation 6, f _r is the output frequency of the reference divider 5, N is the frequency division number of the programmable counter 3, f'is the output frequency of the local oscillator 13.

[0024]

[6] _{f VCO = f'+ N × f} r where frequency change step Δf of the voltage controlled oscillator 1 when the dividing number N of the programmable counter 3 has 1 changed
_VCO is represented by _Equation 7.

[0025]

Equation 7] _{Δf VCO = (f'+ (N} + 1) × f r) - (f'+ N × f r) = f r The frequency change step Delta] f _VCO of the voltage controlled oscillator 1
Since limited to less than the greatest common divisor f _GCM transmission frequency of the broadcast station, as shown in Equation 8, the maximum value of the output frequency f _r of the reference divider 5, the transmission frequency of the broadcast station greatest common divisor f _GCM Is limited to

[0026]

F _r ≦ f _GCM As can be seen by comparing _Equations 8 and 2, the mixer scheme P
For LL frequency synthesizer, the maximum value of the output frequency f _r of the reference divider 5 can be the same as the PLL frequency synthesizer of the basic form, and does not lead to a decrease in C / N ratio.

Next, a description will be given of a comparison between a prescaler type PLL frequency synthesizer and a mixer type frequency synthesizer in terms of circuit configuration, particularly, suitability for IC.

In the PLL frequency synthesizer of the prescaler system shown in FIG. 5, the voltage controlled oscillator 1, the reference signal oscillator 4, and the low-pass filter 7 are analog circuits, and these circuits include discrete components from the viewpoint of characteristics and cost. Used. Other PLs such as a programmable counter 3, a reference divider 5, a phase comparator 6, a microcomputer 10 and a prescaler 11
Most of the circuits constituting the L frequency synthesizer are digital circuits, which can be integrated into one chip on an IC.
It can be said that it is suitable for IC.

On the other hand, in the case of the PLL frequency synthesizer of the mixer system shown in FIG.
Since the reference divider 5, the phase comparator 6, and the microcomputer 10 are digital circuits, they can be integrated into one chip on an IC. However, in addition to the voltage control oscillator 1, the reference signal oscillator 4, and the low-pass filter 7, the mixer 12 and the local oscillator 13 Since they are circuits, they are composed of discrete components, and therefore, there are many circuits that cannot be formed into one chip on an IC as compared with the prescaler method, and it can be said that their suitability for IC formation is inferior.

As described above, the PLL frequency synthesizer of the prescaler type is excellent in the suitability for IC, but is inferior in the C / N ratio. On the other hand, the PLL frequency synthesizer of the mixer type has the C / N ratio. Is superior, but the suitability for IC is inferior, and both methods have advantages and disadvantages.

The present invention has been made in view of the above points, and has a P / N ratio excellent in both the C / N ratio and the suitability for IC formation.
An object of the present invention is to provide an LL frequency synthesizer.

[0032]

In order to achieve the above object, the present invention provides a voltage controlled oscillator for outputting a signal having a frequency corresponding to an input control voltage, and samples an output signal of the voltage controlled oscillator. A sampling means, a programmable counter that divides the frequency of the output signal of the sampling means by the input frequency division number, a microcomputer that instructs the frequency division number to the programmable counter, and a reference signal oscillator that generates a predetermined frequency. A reference divider that divides the frequency of the output signal of the reference signal oscillator by a predetermined number of divisions, and compares the phase of the output signal of the programmable counter with the output signal of the reference divider to generate a voltage corresponding to the phase difference. A phase comparator,
And a low pass filter to smooth and stable the control voltage output of the phase comparator, said sampling means
A sample to which the output signal of the voltage controlled oscillator is input.
Switched capacitor sampling at ring frequency
Circuit for controlling the switched capacitor circuit
A ring control circuit and the sampling controller
The switched capacitor circuit is connected to the
Sampling frequency indicator to input sampling frequency
And a PLL frequency synthesizer.

In the present invention, the sampling frequency of the sampling means is set to be lower than the Nyquist frequency of the output signal of the voltage controlled oscillator.

[0034]

[0035]

[0036]

[0037]

[0038]

In the present invention, the sampling frequency indicating means is realized by the microcomputer.

[0040]

According to the present invention, the sampling means samples the output signal of the voltage controlled oscillator and outputs the same, whereby the frequency of the signal input to the programmable counter is lower than the frequency of the output signal of the voltage controlled oscillator. And a configuration suitable for IC integration without deteriorating the C / N ratio.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a PLL frequency synthesizer according to the present invention.

This PLL frequency synthesizer has a voltage-controlled oscillator 1 capable of changing an output frequency f _VCO by a control voltage, and an output frequency f of the voltage-controlled oscillator 1.
Switched capacitor circuit 2 for sampling _VCO
A sampling control circuit 9 for controlling the switched capacitor circuit 2, a microcomputer 8 for supplying a sampling signal to the switched capacitor circuit 2 via the sampling control circuit 9 and instructing the programmable counter 3 to divide the frequency, and a microcomputer 8. A programmable counter 3 for dividing the output of the switched capacitor circuit 2 by the designated division number, a reference signal oscillator 4 for generating a reference frequency, a reference divider 5 for dividing the output of the reference signal oscillator 4, A phase comparator 6 that compares the phase of the output of the programmable counter 3 with the output of the reference divider 5 and generates a voltage corresponding to the phase difference; and a low-pass filter 7 that smoothes the output of the phase comparator 6 to provide a stable control voltage. Consists of

Next, the operation of the PLL frequency synthesizer shown in FIG. 1 will be described.

A feature of the PLL frequency synthesizer according to the present invention is that it has a sampling means comprising a microcomputer 8 and a switched capacitor circuit 2 controlled by a sampling control circuit 9, and after sampling the output of the voltage controlled oscillator 1 by this sampling means. That is, the sampling frequency at this time is set to be lower than the Nyquist frequency of the output frequency of the voltage controlled oscillator 1.

[0046] Figure 2 is a diagram illustrating the Nyquist frequency, and a predetermined input frequency _f'm, relative to the sampling frequency f _S for sampling the input frequency _f'm, (a) is f _S> 2 × shows the case of _f'm, (b) is a diagram showing a case of f _S = 2 × _f'm,
(C) is a diagram showing a case where f _S <2 × f ′ _m , and (d) is a diagram showing a case where the input frequency f ′ _m is a sine wave and f _S = 2 × f ′ _m .

[0047] In general, the input frequency _f'm can be sampled without impairing the information the original signal sampled at the frequency higher than twice are known by the sampling theorem (see FIG. 2 (a), (b)) , This 2x
that the Nyquist frequency of the input frequency _f'm that of the frequency of _f'm.

When sampling is performed at a frequency lower than the Nyquist frequency (see FIG. 2C), aliasing occurs.
The information in the hatched portion in FIG. 2C is lost. Further, _f'm when the input frequency _f'm is a sine wave because a single frequency is as shown in Figure 2 (d).

In the present invention, unlike the process of A / D conversion or D / A conversion, the purpose is not to convert and restore information. Therefore, the input frequency f ′ _m , the output frequency f _VCO of the voltage controlled oscillator 1 in FIG.
Since there are only three frequency components and the frequency variable range of the input frequency f _VCO can be specified at the time of designing a system such as a receiver, the output signal (signal after sampling) corresponding to the frequency of f _VCO under limited conditions ) Should be obtained.

The fact that the sampling frequency in the switched capacitor circuit 2 of FIG. 1 is higher than the Nyquist frequency of the output frequency of the voltage controlled oscillator 1 is one of the features of the present invention, which is that high speed operation is realized when the integrated circuit is implemented. An operation circuit is required, which is not desirable in terms of current consumption, fine processing, and cost. Conversely, by setting the sampling frequency to be lower than the Nyquist frequency, the present invention does not require such a high-speed operation, so that the present invention is advantageous in terms of current consumption, fine processing, and cost.

[0051] Figure 3 is a diagram for explaining the sampling frequency in the present invention, a predetermined input frequency _f'm
When a sampling frequency f _S for sampling the input frequency _f'm, shows the relationship between the output frequency f _OUT of the results obtained by sampling the input frequency _f'm at a sampling frequency f _S, (a) is f _S <f 'shows the case of _m in the time variable area, (b) drawing showing the frequency variable area in the case of _{f S <f'm, (c} ) the frequency in the case of f _S <2 × _f'm It is the figure shown in the domain.

As can be seen from FIG. 3A, the output frequency f _{OUT obtained} as a result of sampling is the beat frequency of the input frequency f ′ _m and the sampling frequency f _S. FIG. 3B shows this in the frequency domain.

FIG. 3C is a diagram showing a case where a frequency of 1/2 of f _S in FIGS. 3A and 3B is newly set to f _S. At this time, the input frequency f ′ _m (F ′ _m −f _s ) and (f
_'M a -2f _S), it can be selected _(f'm -2f _S) as output frequency f _OUT if sufficient frequency difference.

[0054] In the present invention, the input frequency _f'm is a sinusoidal wave signal output from the voltage controlled oscillator 1. Therefore, the variable region of the input frequency f ′ _m is determined, for example, in relation to the reception band of the receiver using the PLL frequency synthesizer according to the present invention, and only needs to be variable in a frequency range of only a specific region. That is, the input frequency f
' _M , the variable range of the output frequency f _{OUT is} the range of the arrows shown in FIGS. 3 (b) and (c).

[0055] That is, it is possible to capture the variation in the input frequency _f'm as the fluctuation of the output frequency f _OUT, in the present embodiment, the output frequency f _OUT corresponds to the output of the switched capacitor circuit 2.

In the PLL frequency synthesizer shown in FIG. 1, the switched capacitor circuit 2
Is the output frequency f _OUT of (f _VCO -2f _S ), the output frequency f _VCO of the voltage controlled oscillator 1 is expressed by Expression 9.
In Equation 9, f _r is the output frequency of the reference divider 5, N is the division number of the programmable counter 3.

[0057]

Equation 9] where _{f VCO = 2f S + N ×} f r, the frequency variation steps Δf of the voltage controlled oscillator 1 when the dividing number N of the programmable counter 3 has 1 changed
_{The VCO} is represented by _Expression 10.

[0058]

Equation 10] _{Δf VCO = (2f S + (} N + 1) × f r) - (2f S + N × f r) = f r The frequency change step Delta] f _VCO of the voltage controlled oscillator 1
Since limited to less than the greatest common divisor f _GCM transmission frequency of the broadcast station, as shown in Equation 11, the maximum value of the output frequency f _r of the reference divider 5, the transmission frequency of the broadcast station greatest common divisor f _GCM Is limited to

[0059]

F _r ≦ f _GCM As can be seen by comparing _Equation 11 and _Equation 2, P
For LL frequency synthesizer, the maximum value of the output frequency f _r of the reference divider 5 can be the same as the PLL frequency synthesizer of the basic form, and does not lead to a decrease in C / N ratio.

Further, since the switched capacitor circuit 2 and the sampling control circuit 9 in the present embodiment are digital circuits, they can be integrated into one chip on an IC together with the other programmable counter 3, reference divider 5, phase comparator 6, and microcomputer 8. It can be said that the PLL frequency synthesizer according to the present invention is suitable for IC.

[0061]

As described above, according to the present invention, the sampling means such as the switched capacitor circuit 2 is provided before the program counter 3, and the sampling is performed at a frequency lower than the input frequency by the sampling means. Since aliasing is performed and the low-frequency converted signal is input to the program counter 3, the aliasing is involved in the C / N ratio under the above-described conditions of the configuration of the PLL frequency synthesizer and the use frequency range. Reference frequency, that is, the output frequency of the reference divider 5 can be set relatively high ( _fr ≦ f
_GCM ) and most of the circuits constituting the PLL frequency synthesizer can be constituted by digital circuits, so that they have an advantage that they are suitable for IC implementation.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a PLL frequency synthesizer according to the present invention.

FIG. 2 is a diagram illustrating a Nyquist frequency,
A predetermined input frequency _f'm, relative to the sampling frequency f _S for sampling the input frequency _f'm, (a) is a diagram showing a case of f _S> 2 × _f'm,
(B) is a diagram illustrating a case where f _S = 2 × f ′ _m , (c) is a diagram illustrating a case where f _S <2 × f ′ _m , and (d) is a diagram in which the input frequency f ′ _m is a sine wave FIG. 4 is a diagram showing a case where f _S = 2 × f ′ _m .

FIG. 3 is a diagram illustrating a sampling frequency according to the present invention; a predetermined input frequency f ′ _m and a sampling frequency f at which the input frequency f ′ _m is sampled;
_S shows the relationship between _S and the output frequency f _{OUT obtained} by sampling the input frequency f ′ _m at the sampling frequency f _S , and (a) shows the case where f _S <f ′ _{m in} the time domain, (b) is a diagram showing the case where f _S <f ' _{m in} the frequency domain, and (c) is a diagram showing the case where f _S <2 × f' _{m in} the frequency domain.

FIG. 4 is a block diagram of a basic form of a PLL frequency synthesizer.

FIG. 5 is a block diagram of a conventional prescaler-type PLL frequency synthesizer.

FIG. 6 is a block diagram of a conventional mixer-type PLL frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage controlled oscillator 2 Switched capacitor circuit 3 Programmable counter 4 Reference signal oscillator 5 Reference divider 6 Phase comparator 7 Low pass filter 8 Microcomputer 9 Sampling control circuit 10 Microcomputer 11 Prescaler 12 Mixer 13 Local oscillator

Claims (3)

(57) [Claims] A voltage-controlled oscillator for outputting a signal having a frequency corresponding to the input control voltage; a sampling means for sampling an output signal of the voltage-controlled oscillator; and a frequency of an output signal of the sampling means. A programmable counter that divides the frequency by a frequency division number, a microcomputer that instructs the programmable counter to divide the frequency, a reference signal oscillator that generates a predetermined frequency, and a frequency that the output signal of the reference signal oscillator divides by a predetermined frequency A phase divider for dividing the output signal of the programmable counter and the output signal of the reference divider to generate a voltage corresponding to the phase difference; and smoothing and stabilizing the output of the phase comparator. and a low pass filter to the control voltage, said sampling means, output of the voltage controlled oscillator Power signal
Signal at the input sampling frequency
Switched capacitor circuit and switched capacitor
A sampling control circuit for controlling the circuit;
The switch key is set via the sampling control circuit.
A sampler for inputting the sampling frequency to a capacitor circuit.
P which comprises pulling frequency indicating means.
LL frequency synthesizer. 2. The PLL frequency synthesizer according to claim 1, wherein a sampling frequency of said sampling means is equal to or lower than a Nyquist frequency of an output signal of said voltage controlled oscillator. 3. The apparatus according to claim 2, wherein
The PL according to claim 1, wherein the PL is a microcomputer.
L frequency synthesizer.