JPH08223035A - Pll frequency synthesizer - Google Patents

Abstract

PURPOSE: To provide a PLL frequency synthesizer which excells in both the C/N and the aptitude to transformation into an IC. CONSTITUTION: The sampling frequency is inputted to a switched capacitor circuit 2 from a microcomputer 8 via a sampling control circuit 9. Then the circuit 2 samples and outputs the output signal of a voltage controlled oscillator 1. Thereby, the frequency of the signal that is inputted to a programmable counter 3 can be set lower than the frequency of the output signal of the oscillator 1. Furthermore, it is possible to have a constitution that is suitable for transformation into an IC with no deterioration of the C/N.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a PLL frequency synthesizer.

[0002]

2. Description of the Related Art A PLL frequency synthesizer is used to generate a desired frequency in a radio or the like. A conventional PLL frequency synthesizer will be described below with reference to the drawings.

FIG. 4 is a block diagram of a basic form of a PLL frequency synthesizer.

This PLL frequency synthesizer includes a voltage controlled oscillator 1 capable of changing an output frequency according to a control voltage, a microcomputer 10 instructing a frequency division number, and a voltage controlled oscillator 1 at a frequency division instructed by the microcomputer 10. Programmable counter 3 for dividing the output of the reference signal, reference signal oscillator 4 for generating a reference frequency, and reference signal oscillator 4
Reference divider 5 for dividing the output of, and the output of programmable counter 3 and reference divider 5
And a low-pass filter 7 for smoothing the output of the phase comparator 6 to obtain a stable control voltage.

This PLL frequency synthesizer automatically controls the frequency generated by controlling the frequency division number in the programmable counter 3 by the microcomputer 10. However, in the PLL frequency synthesizer shown in FIG. 4, when it is desired to generate a high frequency by the voltage controlled oscillator 1, the operation of the programmable counter 3 is
There is a problem that the output signal of the voltage controlled oscillator 1 which is the input signal cannot be followed.

Therefore, the conventional PLL frequency synthesizer adopts a prescaler system or a mixer system as a measure against this problem.

FIG. 5 shows a conventional prescaler type PLL.
It is a block diagram of a frequency synthesizer. In the figure, the same components as those in FIG. 4 are designated by the same reference numerals.

This prescaler type PLL frequency synthesizer is provided with a prescaler (fixed frequency dividing circuit) 11 having a relatively simple structure and operating at a high speed in the preceding stage of the programmable counter 3, and the frequency of the signal input to the programmable counter 3 is set. I am trying to lower it.

On the other hand, FIG. 6 shows a conventional mixer type PLL.
It is a block diagram of a frequency synthesizer. In the figure, the same components as those in FIG. 4 are designated by the same reference numerals.

This mixer type PLL frequency synthesizer comprises a mixer 12 and a local oscillator 13, and the mixer 1
2 the output signal of the voltage controlled oscillator 1 and the local oscillator 1
3 is mixed with the output signal of 3 and the frequency of the signal input to the programmable counter 3 is lowered.

[0011]

By the way, one of the performances required for a PLL frequency synthesizer is a carrier noise ratio (hereinafter referred to as "C / N ratio"). This is the ratio of the carrier that is the oscillation main signal of the voltage controlled oscillator 1 to the noise that is an unnecessary signal such as a sideband component,
It is a PLL frequency synthesizer with better performance as the C / N ratio is larger.

The PLL frequency synthesizer is a kind of negative feedback, and is always corrected by the output signal of the phase comparator 6 so that the two input signals of the phase comparator 6 are in phase with each other. Even when the output frequency of the PLL frequency synthesizer, that is, the output frequency of the voltage controlled oscillator 1 is in a stable state at a desired frequency, this correction is always performed, and its cycle is equal to that of the output signal of the reference divider 5. It becomes every cycle.

From the viewpoint of improving the C / N ratio, it is better that the effect of this correction does not affect the output signal of the low-pass filter 7. If the characteristics of the low-pass filter 7 are constant,
The more frequently the correction is made, that is, the higher the output frequency of the reference divider 5 is, the less the ripple due to the correction is generated in the output signal of the low-pass filter 7, and the C / N ratio is improved.

However, the output frequency of the reference divider 5 is limited as described below.

In the basic PLL frequency synthesizer shown in FIG. 4, the output frequency f of the voltage controlled oscillator 1 is
_{The VCO} is expressed by _equation 1. In Expression 1, f _r is the output frequency of the reference divider 5, and N is the frequency division number of the programmable counter 3.

[0016]

[Number 1] may be changed frequency division number N of the programmable counter 3 to vary the output frequency of f _VCO = N × f _r voltage controlled oscillator 1, since N is generally a natural number, f _VCO is the f _r Therefore, the minimum step of the change in the output frequency of the voltage controlled oscillator 1 is f _r .

Here, a case where the PLL frequency synthesizer is a circuit for generating a reception frequency in a receiver for receiving broadcast will be described as an example.

Considering a broadcasting station for broadcasting received by this receiver, this broadcasting station transmits broadcasting radio waves at a frequency of an interval determined for each predetermined band by the law of each country. Therefore, in order to receive these broadcasts, the output frequency of the reference divider 5 must be a divisor of each transmission frequency of all broadcasts to be received. That is, as shown in Expression 2, the maximum value of the output frequency f _r of the reference divider 5 is limited to be the greatest common divisor f _GCM of the transmission frequency of the broadcasting station.

[0019]

[Number 2] On the other hand f _r ≦ f _GCM, in the PLL frequency synthesizer of the prescaler system shown in FIG. 5, the output frequency f _VCO of the voltage controlled oscillator 1 is represented by the number 3. In Expression 3, f _r is the output frequency of the reference divider 5, N is the frequency division number of the programmable counter 3, and M is the frequency division number of the prescaler 11.

[0020]

Equation 3] where _{f VCO = M × N × f} r, the frequency variation steps Δf of the voltage controlled oscillator 1 when the dividing number N of the programmable counter 3 has 1 changed
_{The VCO} is expressed by _equation 4.

[0021]

Equation 4] _{Δf VCO = (M × (N} + 1) × f r) - (M × N × f r) = M × f r The frequency change step Delta] f _VCO of the voltage controlled oscillator 1
Is limited to the greatest common divisor f _GCM or less of the transmission frequency of the broadcasting station, the maximum value of the output frequency f _r of the reference divider 5 is the greatest common divisor f _GCM of the broadcasting frequency of the broadcasting station, as shown in Equation 5. Is divided by the frequency division number M of the prescaler 11 to be a value.

[0022]

[Mathematical formula-see original _document ] f _r ≤f _GCM / M As can be seen by comparing equation 5 and equation 2, in the prescaler type PLL frequency synthesizer, the maximum value of the output frequency f _r of the reference divider 5 is larger than that of the basic PLL frequency synthesizer. Also becomes a small value, and the C / N ratio decreases as described above.

On the other hand, in the mixer-type PLL frequency synthesizer shown in FIG. 6, the output frequency f _VCO of the voltage controlled oscillator 1 is expressed by the equation 6. In Equation 6, f _r is the output frequency of the reference divider 5, N is the frequency division number of the programmable counter 3, and f ′ is the output frequency of the local oscillator 13.

[0024]

[6] _{f VCO = f'+ N × f} r where frequency change step Δf of the voltage controlled oscillator 1 when the dividing number N of the programmable counter 3 has 1 changed
_VCO is expressed by the _equation 7.

[0025]

Equation 7] _{Δf VCO = (f'+ (N} + 1) × f r) - (f'+ N × f r) = f r The frequency change step Delta] f _VCO of the voltage controlled oscillator 1
Is limited to the maximum common divisor f _GCM or less of the transmission frequency of the broadcasting station, the maximum value of the output frequency f _r of the reference divider 5 is the maximum common divisor f _GCM of the broadcasting frequency of the broadcasting station, as shown in _{Expression 8.} Is limited to.

[0026]

F _r ≤f _GCM As can be seen by comparing Eq. 8 and Eq.
For LL frequency synthesizer, the maximum value of the output frequency f _r of the reference divider 5 can be the same as the PLL frequency synthesizer of the basic form, and does not lead to a decrease in C / N ratio.

Next, the prescaler type PLL frequency synthesizer and the mixer type frequency synthesizer will be described in comparison with respect to their circuit configurations, especially suitability for IC implementation.

In the PLL frequency synthesizer of the prescaler type shown in FIG. 5, the voltage controlled oscillator 1, the reference signal oscillator 4 and the low pass filter 7 are analog circuits, and discrete components are included in these circuits in terms of characteristics and cost. Used. Other programmable counters 3, reference divider 5, phase comparator 6, microcomputer 10, prescaler 11, and other PLs
Most of the circuits that make up the L frequency synthesizer are digital circuits, and these can be integrated into one chip on an IC.
It can be said that it is suitable for IC.

On the other hand, in the case of the mixer type PLL frequency synthesizer shown in FIG. 6, the programmable counter 3,
Since the reference divider 5, the phase comparator 6 and the microcomputer 10 are digital circuits, they can be integrated into one chip on an IC. However, in addition to the voltage controlled oscillator 1, the reference signal oscillator 4 and the low pass filter 7, the mixer 12 and the local oscillator 13 are analog. Since they are circuits, they are composed of discrete components, and therefore, many circuits cannot be integrated into one chip on the IC as compared with the prescaler method, and it can be said that the suitability for IC integration is inferior.

As described above, the PLL frequency synthesizer of the prescaler system is excellent in suitability for IC, but inferior in the C / N ratio, while the PLL frequency synthesizer of the mixer system is inferior to the C / N ratio. Is excellent, but the suitability for IC is poor, and both types have advantages and disadvantages.

The present invention has been made in view of the above points, and has a superior C / N ratio and suitability for IC conversion.
It is an object to provide an LL frequency synthesizer.

[0032]

In order to achieve the above object, the present invention samples a voltage controlled oscillator that outputs a signal having a frequency corresponding to an input control voltage, and an output signal of this voltage controlled oscillator. Sampling means, a programmable counter that divides the frequency of the output signal of the sampling means by an input dividing number, a microcomputer that instructs the programmable counter on the dividing number, and a reference signal oscillator that generates a predetermined frequency. , A reference divider that divides the frequency of the output signal of the reference signal oscillator by a predetermined dividing number, and the output signal of the programmable counter and the output signal of the reference divider are compared in phase to generate a voltage according to the phase difference. Phase comparator to
A PLL frequency synthesizer is provided with a low-pass filter that smoothes the output of this phase comparator and makes the control voltage stable.

Further, in the present invention, the sampling frequency in the sampling means is set to be equal to or lower than the Nyquist frequency of the output signal of the voltage controlled oscillator.

Further, according to the present invention, the relationship between the sampling frequency f _S in the sampling means and the frequency f _VCO of the output signal of the voltage controlled oscillator is f _VCO > 2f _S.

Further, according to the present invention, the frequency of the output signal of the sampling means is set to | f _VCO -f _S |.

Further, according to the present invention, the frequency of the output signal of the sampling means is | f _VCO- L × f _S |
Is a predetermined natural number).

Further, according to the present invention, the frequency of the output signal of the sampling means is set to | f _VCO −2f _S |.

The present invention also provides a switched capacitor circuit for sampling the output means of the voltage controlled oscillator at the input sampling frequency, a sampling control circuit for controlling the switched capacitor circuit, and the sampling control. And a sampling frequency instruction means for inputting the sampling frequency to the switched capacitor circuit via a circuit.

Further, according to the present invention, the sampling frequency indicating means is realized by the microcomputer.

[0040]

According to the present invention, the sampling means samples and outputs the output signal of the voltage controlled oscillator so that the frequency of the signal input to the programmable counter is lower than the frequency of the output signal of the voltage controlled oscillator. In addition, the structure is suitable for IC without deteriorating the C / N ratio.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a PLL frequency synthesizer according to the present invention.

This PLL frequency synthesizer comprises a voltage controlled oscillator 1 capable of changing the output frequency f _VCO by a control voltage, and an output frequency f of the voltage controlled oscillator 1.
Switched capacitor circuit 2 for sampling _VCO
A sampling control circuit 9 for controlling the switched capacitor circuit 2; a microcomputer 8 for supplying a sampling signal to the switched capacitor circuit 2 via the sampling control circuit 9; A programmable counter 3 for dividing the output of the switched capacitor circuit 2 by a designated division number; a reference signal oscillator 4 for generating a reference frequency; and a reference divider 5 for dividing the output of the reference signal oscillator 4. A phase comparator 6 that compares the output of the programmable counter 3 and the output of the reference divider 5 to generate a voltage according to the phase difference; and a low-pass filter 7 that smoothes the output of the phase comparator 6 to a stable control voltage. Consists of.

Next, the operation of the PLL frequency synthesizer shown in FIG. 1 will be described.

The feature of the PLL frequency synthesizer according to the present invention is that it has a sampling means composed of a microcomputer 8 and a switched capacitor circuit 2 controlled by a sampling control circuit 9, and after sampling the output of the voltage controlled oscillator 1 by this sampling means. The program frequency is input to the program counter 3, and the sampling frequency at this time is set to be equal to or lower than the Nyquist frequency of the output frequency of the voltage controlled oscillator 1.

[0046] Figure 2 is a diagram illustrating the Nyquist frequency, and a predetermined input frequency _f'm, relative to the sampling frequency f _S for sampling the input frequency _f'm, (a) is f _S> 2 The figure showing the case of × f ′ _m , (b) the figure showing the case of f _S = 2 × f ′ _m ,
(C) is a diagram showing a case where f _S <2 × f ′ _m , and (d) is a diagram showing a case where the input frequency f ′ _m is a sine wave and f _S = 2 × f ′ _m .

[0047] In general, the input frequency _f'm can be sampled without impairing the information the original signal sampled at the frequency higher than twice are known by the sampling theorem (see FIG. 2 (a), (b)) , This 2x
that the Nyquist frequency of the input frequency _f'm that of the frequency of _f'm.

When sampling is performed at a frequency equal to or lower than the Nyquist frequency (see FIG. 2C), aliasing occurs,
The information in the shaded portion in FIG. 2C is lost. Further, _f'm when the input frequency _f'm is a sine wave because a single frequency is as shown in Figure 2 (d).

In the present invention, unlike the process of A / D conversion or D / A conversion, the purpose is not to convert or restore information. Therefore, the input frequency _f'm, the output frequency f _VCO of the voltage controlled oscillator 1 in terms of the FIG. 1 is a sine wave 1
Since there is only one frequency component and the variable frequency range of the input frequency f _VCO can be specified when designing a system such as a receiver, the output signal corresponding to the frequency of f _VCO (the signal after sampling can be specified under limited conditions. ) Should be obtained.

Setting the sampling frequency in the switched-capacitor circuit 2 of FIG. 1 higher than the Nyquist frequency of the output frequency of the voltage controlled oscillator 1 is high speed when integrated into an IC, which is one of the features of the present invention. An operating circuit is required, which is not very desirable in terms of current consumption, fine process and cost. Conversely, according to the present invention, by setting the sampling frequency to be equal to or lower than the Nyquist frequency, a high speed operation is not required so much, and it is advantageous in terms of current consumption, fine process and cost.

[0051] Figure 3 is a diagram for explaining the sampling frequency in the present invention, a predetermined input frequency _f'm
When a sampling frequency f _S for sampling the input frequency _f'm, shows the relationship between the output frequency f _OUT of the results obtained by sampling the input frequency _f'm at a sampling frequency f _S, (a) is f _S <f 'shows the case of _m in the time variable area, (b) drawing showing the frequency variable area in the case of _{f S <f'm, (c} ) the frequency in the case of f _S <2 × _f'm It is the figure shown by the domain.

[0052] The output frequency f _OUT of the sampled results as can be seen from FIG. 3 (a), the beat frequency of the input frequency _f'm and the sampling frequency f _S. This is shown in the frequency domain as shown in FIG.

[0053] FIG. 3 (c) is a diagram showing a case where the newly set to f _S a frequency of 1/2 of the f _S in FIG. 3 (a) and 3 (b), this time, the input frequency _f'm the obtained at lower frequency than is the _(f'm -f _S) (f
_'M a -2f _S), it can be selected _(f'm -2f _S) as output frequency f _OUT if sufficient frequency difference.

[0054] In the present invention, the input frequency _f'm is a sinusoidal wave signal output from the voltage controlled oscillator 1. Accordingly, the variable region of the input frequency _f'm, for example, Sadamari in relation to the reception band of a receiver using a PLL frequency synthesizer according to the present invention, may be a variable in the frequency range of only a specific area. That is, the input frequency f
′ _M , the variable range of the output frequency f _{OUT is} the range of the arrows shown in FIGS. 3B and 3C.

[0055] That is, it is possible to capture the variation in the input frequency _f'm as the fluctuation of the output frequency f _OUT, in the present embodiment, the output frequency f _OUT corresponds to the output of the switched capacitor circuit 2.

In the PLL frequency synthesizer shown in FIG. 1, the switched capacitor circuit 2 is used as described above.
When the output frequency f _OUT and (f _VCO -2f _S), the output frequency f _VCO of the voltage controlled oscillator 1 is represented by the number 9.
In Expression 9, f _r is the output frequency of the reference divider 5, and N is the frequency division number of the programmable counter 3.

[0057]

Equation 9] where _{f VCO = 2f S + N ×} f r, the frequency variation steps Δf of the voltage controlled oscillator 1 when the dividing number N of the programmable counter 3 has 1 changed
_{The VCO} is expressed by _equation 10.

[0058]

Equation 10] _{Δf VCO = (2f S + (} N + 1) × f r) - (2f S + N × f r) = f r The frequency change step Delta] f _VCO of the voltage controlled oscillator 1
Is limited to the greatest common divisor f _GCM or less of the transmission frequency of the broadcasting station, the maximum value of the output frequency f _r of the reference divider 5 is the greatest common divisor f _GCM of the broadcasting station's transmission frequency, as shown in Eq. Is limited to.

[0059]

[ _Mathematical formula-see original _document ] f _r ≤f _GCM As can be seen by comparing equation 11 and equation 2, P of the present embodiment
For LL frequency synthesizer, the maximum value of the output frequency f _r of the reference divider 5 can be the same as the PLL frequency synthesizer of the basic form, and does not lead to a decrease in C / N ratio.

Further, since the switched capacitor circuit 2 and the sampling control circuit 9 in this embodiment are digital circuits, they can be integrated into one chip together with other programmable counter 3, reference divider 5, phase comparator 6 and microcomputer 8 on the IC. It can be said that the PLL frequency synthesizer according to the present invention is suitable for IC implementation.

[0061]

As described above, according to the present invention, the sampling means such as the switched capacitor circuit 2 is provided in front of the program counter 3, and the sampling means performs sampling at a frequency lower than the input frequency. Since aliasing is performed and the low-frequency converted signal is input to the program counter 3, the C / N ratio is concerned under the configuration of the PLL frequency synthesizer described above and the limiting condition of the frequency range used. The reference frequency of the reference divider 5, that is, the output frequency of the reference divider 5 can be made relatively high (f _r ≤f
_GCM ) and most of the circuits that compose the PLL frequency synthesizer can be configured by digital circuits, and thus have an advantage that they are suitable for IC implementation.

[Brief description of drawings]

1 is a block diagram of one embodiment of a PLL frequency synthesizer according to the present invention.

FIG. 2 is a diagram for explaining a Nyquist frequency,
In the relationship between the predetermined input frequency f ′ _m and the sampling frequency f _S for sampling this input frequency f ′ _m , (a) is a diagram showing a case where f _S > 2 × f ′ _m ,
(B) is a diagram showing a case of f _S = 2 × f ′ _m , (c) is a diagram showing a case of f _S <2 × f ′ _m , (d) is a sine wave with an input frequency f ′ _m 3 is a diagram showing a case where f _S = 2 × f ′ _m .

FIG. 3 is a diagram for explaining a sampling frequency in the present invention, in which a predetermined input frequency f ′ _m and a sampling frequency f for sampling the input frequency f ′ _m
S and shows the relationship between the output frequency f _OUT of the results obtained by sampling the input frequency _f'm at a sampling frequency f _S, (a) is a diagram showing a case of f _{S <f'm} in the time variable area, ( (b) is a diagram showing the frequency domain when f _S <f ′ _m , and (c) is a diagram showing the frequency domain when f _S <2 × f ′ _m .

FIG. 4 is a block diagram of a basic form of a PLL frequency synthesizer.

FIG. 5 is a block diagram of a conventional prescaler PLL frequency synthesizer.

FIG. 6 is a block diagram of a conventional mixer-type PLL frequency synthesizer.

[Explanation of symbols]

 1 Voltage Controlled Oscillator 2 Switched Capacitor Circuit 3 Programmable Counter 4 Reference Signal Oscillator 5 Reference Divider 6 Phase Comparator 7 Low Pass Filter 8 Microcomputer 9 Sampling Control Circuit 10 Microcomputer 11 Prescaler 12 Mixer 13 Local Oscillator

Claims (8)

[Claims] 1. A voltage-controlled oscillator that outputs a signal having a frequency according to an input control voltage, sampling means that samples the output signal of the voltage-controlled oscillator, and the frequency of the output signal of the sampling means. A programmable counter that divides by a dividing number, a microcomputer that instructs the dividing number to the programmable counter, a reference signal oscillator that generates a predetermined frequency, and a frequency of an output signal of the reference signal oscillator that is a predetermined dividing number. A reference divider that divides the frequency with a phase comparator that compares the output signal of the programmable counter with the output signal of the reference divider to generate a voltage according to the phase difference, and smoothes and stabilizes the output of the phase comparator. And a low-pass filter for setting the control voltage as described above. 2. The PLL frequency synthesizer according to claim 1, wherein a sampling frequency in the sampling means is equal to or lower than a Nyquist frequency of an output signal of the voltage controlled oscillator. 3. The PLL frequency synthesizer according to claim 1, wherein the relationship between the sampling frequency f _S in the sampling means and the frequency f _VCO of the output signal of the voltage controlled oscillator is f _VCO > 2f _S. . 4. The PLL frequency synthesizer according to claim 3, wherein the frequency of the output signal of the sampling means is | f _VCO −f _S |. 5. The PLL frequency synthesizer according to claim 3, wherein the frequency of the output signal of the sampling means is | f _VCO −L × f _S | (where L is a predetermined natural number). 6. The PLL frequency synthesizer according to claim 3, wherein the frequency of the output signal of the sampling means is | f _VCO −2f _S |. 7. The sampling means includes a switched capacitor circuit for sampling the output signal of the voltage controlled oscillator at an input sampling frequency, a sampling control circuit for controlling the switched capacitor circuit, and the sampling control circuit. 7. The PLL frequency synthesizer according to claim 1, further comprising a sampling frequency instructing means for inputting the sampling frequency to the switched capacitor circuit. 8. The PL according to claim 7, wherein the sampling frequency instruction means is the microcomputer.
L frequency synthesizer.