JPH0420123A - Pll frequency synthesizer oscillator - Google Patents

Abstract

PURPOSE:To relieve the adverse effect given from a spurious output in the vicinity of a carrier by selecting a local oscillating output of a local oscillator to an integral number of multiple of a reference frequency being an input to a phase comparator of a PLL. CONSTITUTION:Part of an output f0 of a voltage controlled oscillator 11 is mixed by a mixer 12, and a local oscillating frequency fL of an output of a local oscillator 2 for mixing-down to frequency-divide the frequency into 1/N is selected to an integral number of multiple of a reference frequency f0 being an input of a phase comparator 15. Thus, a spurious output level due to a harmonic of the reference frequency fC being the input of the phase comparator 15 is minimized. Thus, the adverse effect given from a spurious output in the vicinity of a carrier is reduced without losing the output carrier spectrum characteristic and its stability.

Description

[Detailed Description of the Invention] [Summary] Voltage controlled oscillator V that controls oscillation frequency with control voltage Vc
CO, a mixer that converts a part of its output fo to a lower frequency, a variable frequency divider that divides the frequency of the output of the mixer to 1/N, and a signal fr from the reference signal source to 1/N. /H
and a phase comparator that uses the output fc of the frequency divider as a reference power and compares the phases of the output of the variable frequency divider. A mixing down type PLL frequency synthesizer oscillator having a PLL that controls an oscillator and a local oscillator that supplies a local oscillator signal fL for frequency conversion to the mixer, without impairing the spectral characteristics and stability of the output carrier. , the purpose is to provide a PLL frequency synthesizer oscillator that reduces the adverse effects of spurious output near the carrier, and the local oscillator frequency fL of the output of the local oscillator supplied to the mixer of the PLL is the input of the phase comparator of the PLL. The reference frequency fc is selected to be an integral multiple of the reference frequency fc.

[Industrial Application Field] The present invention relates to a PLL frequency synthesizer oscillator used in devices such as mobile radios, satellite communication transceivers, satellite broadcast tuners, and radios.

As the performance of the above devices increases, PLL frequency synthesizer oscillators also achieve fine frequency steps (intervals of frequencies that can be output) over a wide band while maintaining high output spectrum purity and low spurious levels. These contradictory performances are required.

[Conventional technology]

As a conventional PLL frequency synthesizer oscillator.

There is a so-called mixing down method as shown in FIG. 5(A). This type of PLL frequency synthesizer oscillator uses the output fo of a voltage controlled oscillator (hereinafter referred to as VCO) 11.
In the mixer 12, a part of the output f of the local oscillator 2,
mixed with the lower frequency f.

After converting the frequency to fL, the variable frequency divider 13 divides the frequency into l/N and inputs it to the phase comparator 15. - On the other hand, the reference signal of frequency fr from the reference signal source 3 is.

The frequency is divided into 1/H by the frequency divider 14 and the reference frequency fc is 8.
The signal is input to the phase comparator 15 and compared in phase with the signal from the variable frequency divider 13. The output of the phase comparator 15 is
It is supplied to the VCO 11 as the control signal Vc.

Control its oscillation frequency. In this configuration, VCOl
The output frequency fo of l is as follows: fo = fc x N + f L -・-■ By increasing/decreasing the frequency division number N by 1.

The frequency step fc of the output carrier is obtained.

In this method, by designing the local frequency fL of the output of one local oscillator 2 to a value close to the output frequency fo of the output of the VCO 11, it is possible to reduce the value of the frequency division number N.

Since the phase noise that quantifies the purity of the carrier spectrum of the output of the PLL frequency synthesizer oscillator is 20 Log N dB higher than the internal noise of the 1-phase comparator 15, it becomes the value of the frequency division number N of the variable frequency divider 13. By making it as small as possible, the phase noise can be reduced.

The purity of the output carrier spectrum can be increased.

[Problem to be solved by the invention]

However, in such a mixing down method, a spurious output peculiar to the method may occur in the vicinity of a desired frequency (hereinafter referred to as a carrier frequency) fo. This appears at a remarkable level when an integer multiple of the input reference frequency fc of the nine-phase comparator 15 approaches the carrier frequency fo, and appears on both sides of the output spectrum fo, separated by one frequency Δfs. Here Δfs = fo
−n x fc −■.

The spurious output level largely depends on this Δfs.1 For example, the so-called D/U ratio of a 700 MHz band frequency synthesizer is as shown in Figure 5 (B) "Example of spurious position and level". It has become.

It is impossible to deal with such spurious output near the desired carrier by inserting a so-called filter. The reason is that if a narrowband filter that is effective against such spurious output is inserted into the PLL loop, it will have a negative effect on the spectrum characteristics and stability of the carrier of the PLL output, making it impossible to obtain the desired performance. That's because there isn't. An object of the present invention is to provide a PLL frequency synthesizer oscillator that reduces the adverse effects of spurious signals near the carrier without impairing the spectral characteristics or stability of the output carrier.

[Means for solving the problem] This problem is solved by using a voltage controlled oscillator V as shown in the principle diagram in Fig.
The local oscillator frequency f of the output of the local oscillator 2 for mixing down, which mixes a part of the output fo of the CO 11 with the mixer 12 and divides the frequency into 1/N, is the reference frequency of the input of the phase comparator I5. This is achieved by the PLL frequency synthesizer oscillator of the present invention configured to select an integer multiple of fc.

[Effect]

The operation of the PLL frequency synthesizer oscillator of the present invention will be explained with reference to the frequency relationship diagrams of the spectra shown in FIGS. 2(a) and 2(b).

(a) in Figure 2 shows the local oscillation frequency f of the output of the four local oscillators 2.
The frequency relationship between the output frequency fo of the VCO 11 and the harmonics of the reference frequency fc of the input of the phase comparator 15 when L is selected to be an integral multiple of the reference frequency fc of the input of the phase comparator 15 is shown. As shown in equation (■) above.

The output frequency fo of the VCO 11 is fo = fc x N + f t - ■ (reappearance)
It is expressed as If the local frequency fL is selected to be an integer multiple of the reference frequency fc of the input of the phase comparator, that is, fL=fcxn - ■, the output frequency fo of the VCO 11 will also be.

fo = fc x N + fc x n = fc
(N+n) = fc x N, (■), which corresponds to an integral multiple of the reference frequency fc of the input of the nine phase comparator 15.

Therefore, the harmonic of the reference frequency at the input of the phase comparator closest to the output frequency fO is separated from the output frequency fo of the VCO 11 by the frequency fc. That is, Δfs =
fc -...■. This can be done by changing the frequency division number N of the variable frequency divider 13.
This also holds true when the output frequency fO of is switched.

On the other hand, (b) in FIG. 2 shows the output frequency fo of the VCO 11 when the local frequency f of the output of the nine local oscillators 2 is selected not to be an integral multiple of the reference frequency fc of the input of the eight phase comparator 15. and the reference frequency of the input of the phase comparator 15.

The frequency relationship of several fc harmonics is shown. in this case.

f L= fc x n + f', (f
'< fc) ■The output frequency fo of VCO11 is.

fo = fc x N + fc x n + f'
= fc(N+n) + f'= fc x N,
+ f', (f'< fc) ■.

As can be seen from FIG. 2(b), Δfs = f'.

Compared to (a) in Figure 2, the spurious output is VCO1
It appears at a frequency close to the output frequency fo of 1. As shown in the conventional example in FIG. 5A, as Δfs increases, the level of the spurious output decreases due to the effect of the one-phase locked loop PLL.

By selecting the local frequency fL for mixing down to be an integral multiple of the reference frequency fc at the input of the phase comparator 15, the output level of spurious signals due to harmonics of the reference frequency fc at the input of the phase comparator 15 can be reduced. The task can be achieved by minimizing it.

〔Example〕

FIG. 3 is a block diagram showing the configuration of a PLL frequency synthesizer oscillator according to an embodiment of the present invention, and FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, the first
Components that are the same as those shown in the figures are indicated by the same symbols.

In the embodiment shown in FIG. 3, the local oscillator 2 for mixing down includes the VCO 21 and the output f of the νC021.
The 1/NZ frequency divider 23 that divides L into 1/N* and the output frequency fr of the reference signal source 3 are 17M! The frequency is divided into 1/M!
A phase comparator 25 comprising a frequency divider 24 and a phase comparator 25 that compares the phase of the output of the 1/N* frequency divider 23 using the output frequency fcz of the 1/'t'Vz frequency divider 24 as a reference input. Using a synchronous loop. In this case, the local oscillator frequency fL of the output of local oscillator 2 is as follows.

f L = fcz x Nz = fr/M2x N
,.

The reference frequency fc of the input of the phase comparator 15 is f
c, ・fr/M+, so the output of 1 local oscillator 2 is 2
f L-Ml/M2 fc+ x Nz.

This can be realized by selecting the ratio h+/Mz of the same number of 9 minutes to be an integer.

In another embodiment of the present invention shown in FIG. 4, a multiplier 26 is used as a local oscillator 2 for mixing down, which multiplies the output frequency fr of the reference signal source 3 and sends out an output frequency fL.
are using. In this case, the local oscillator frequency f of the output of local oscillator 2 is:

Since f L = fc+ x L x L+, this local oscillation frequency "," is an integral multiple of the reference frequency fc of the input of the 1-phase comparator 15, and the same effect as the embodiment shown in FIG. 3 described above can be obtained. .

〔Effect of the invention〕

As explained above, according to the present invention, 1
Since the level of spurious output caused by harmonics of the reference frequency of the phase comparison input can be minimized, the performance of PLL frequency synthesizer oscillators used in various types of transmitters and receivers can be improved.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram showing the basic configuration of the PLL frequency synthesizer oscillator of the present invention, Fig. 2 is a frequency relationship diagram of each spectrum to explain the operation of the PLL frequency synthesizer oscillator of the present invention, and Fig. 3 is a diagram of the frequency relationship of each spectrum. FIG. 4 is a block diagram showing the configuration of a PLL frequency synthesizer oscillator according to another embodiment of the present invention, and FIG. 5 is a block diagram showing the configuration of a conventional PLL frequency synthesizer oscillator. and examples of spurious positions and levels. In the figure, 1 is a PLL, 2 is a local oscillator, 3 is a reference signal source, 11 is a voltage controlled oscillator VC0, 12 is a mixer, 1
3 is a 1/N variable frequency divider, 14 is a 1/M frequency divider, 15 is a phase comparator, 21 is a voltage controlled oscillator VC0, 23 is 17N2
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Claims (1)

[Claims] A voltage controlled oscillator (11) that controls the oscillation frequency with a control voltage (Vc), a mixer (12) that converts a part of its output (fo) to a lower frequency, and a mixer that converts the frequency of the output of the mixer to 1/1. A variable frequency divider (13) that divides the frequency by N, a frequency divider (14) that divides the signal (fr) from the reference signal source (3) by 1/M, and an output (fc) of the frequency divider. ) as a reference input and a phase comparator (15) that compares the phase of the output of the variable frequency divider.
A PLL (1) that controls the voltage controlled oscillator (11) using the output of the phase comparator as a control voltage (Vc), and a local oscillator (1) for frequency conversion to the mixer (12).
f_L), wherein the PLL frequency synthesizer oscillator has a local oscillator (2) supplying the local oscillator (2)
A PLL frequency synthesizer oscillator characterized in that the local oscillator frequency (f_L) of the output of the PLL (1) is selected to be an integral multiple of the reference frequency (fc) of the input of the phase comparator (15) of the PLL (1).