JPH0818443A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To eliminate the generation of spuriousness due to the leakage of a reference frequency without extremely aggravating noise near signals, to miniaturize circuit constitution and to lower a cost in the phase locked loop circuit of a frequency synthesizer. CONSTITUTION:In this phase locked loop circuit of the frequency synthesizer, a control voltage 17 is prepared from the fundamental frequency F-REF 5 component of a 1/F-REF 12 by a one-shot multivibrator 10, a phase locked loop is turned off only during a period t13 when the F-REF 5 leaks by an S/H circuit 9 inserted between a VCO 1 and a phase detector 3 and a loop filter 4, a voltage immediately before turning it off is held during the period, it is turned on in a sample state in the other periods and a VCO 1 circuit is operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase lock loop circuit used for spectrum analyzers, signal generators and the like in the field of electronic measurement technology.

[0002]

2. Description of the Related Art FIGS. 3 and 4 show a block diagram of a basic circuit configuration of a frequency synthesizer according to the prior art, and show that a spurious due to leakage occurs in synchronization with each reference frequency. It is a conceptual diagram. The frequency synthesizer is composed of a voltage controlled oscillator (VC
O) 1, a programmable divider 2, a phase detector (phase comparator circuit) 3, a loop filter (low-pass filter) 4, and a reference frequency (F REF) 5. In other words, the output from VCO1 is divided by N by programmable divider 2, then the phase divider
The detector 3 makes a phase comparison with the reference frequency F.REF5, and its output becomes a DC voltage through the loop filter 4, controls the frequency of the VCO 1 and operates as a phase lock loop (PLL).

Here, the output (F · OUT) 6 is F · OUT =
The frequency of N × F · REF7 is output, but as shown in FIG. 4, a leak that appears in synchronization with the cycle of the reference frequency F · REF · 5 appears as a spurious 8. For example, in the case of a 10KHz step synthesizer, the reference frequency F · REF = 10KHz, so 10KHz
A spurious 8 is generated every Hz. Then, in order to remove it, the cutoff frequency of the loop filter 4, which is a low-pass filter, is reduced to deal with it. However, this causes a problem that the neighborhood noise of the signal deteriorates. I will end up. Therefore, in the phase-locked loop circuit of the frequency synthesizer, there is a drawback that the circuit configuration must be complicated and large in order to completely eliminate the problem. In addition, the programmable divider 2 and the phase detector (phase comparator circuit) 3 in one package, which is a multifunctional mass-produced product and low-priced PLL / IC, is extremely effective for downsizing the circuit configuration. However, the reality is that the spurious 8 will increase.

[0004]

In the phase lock loop circuit, it has been a problem to suppress the noise in the vicinity of the signal and to eliminate the spurious emission. However, in order to realize it with the conventional technology, the circuit configuration must be complicated and large-scale,
Further, even if the improvement of the characteristics is realized, there is a problem that it is difficult to meet the strong demand from users such as miniaturization and price reduction.

Therefore, the cutoff frequency of the loop filter as the phase lock loop is extremely low, that is, without narrowing the bandwidth, that is, without deteriorating the noise in the vicinity of the signal, the F. The primary purpose is to reduce spurious due to leakage. Furthermore, a programmable divider and a phase detector are incorporated and mass-produced. The purpose is to realize the miniaturization of the circuit scale and the reduction of the price by using the ().

[0006]

In order to achieve the above object, the phase-locked loop circuit system of the present invention has a structure as shown in FIG. In the circuit of this system, in addition to the circuit configuration of the conventional technology, S / H (sample,
And hold) circuit 9 and one-shot multivibrator circuit 10 are provided.

That is, as shown in FIGS. 1 and 2, for example, when the phase lock loop is driven by F · REF having a frequency of 10 KHz, the one-shot multivibrator causes 100 μs (1 / F・ REF = 1 / 10,000
S / H inserted between the phase detector and the VCO by creating the control voltage at point c from the F / REF component of sec.).
Drive the circuit. As a result, during the period t when the F / REF component leaks, it is possible to hold at the voltage immediately before that and to drive in the sampling state in other periods, so that there is a spurious response that is a leakage of the reference frequency F / REF component. Could be removed.

Therefore, it is not necessary to make the cutoff frequency of the loop filter extremely low, noise in the vicinity can be reduced, and the reference frequency F.REF
It is now possible to configure a phase lock loop circuit that can eliminate spurious noise caused by.

[0009]

[Operation] As shown in FIG. 2, the lock voltage output from the phase detector has a F / RE ratio of 1 / F / REF.
The F component leaks out, which causes spurious F.REF. However, in the present invention, the phase lock loop is S / H only during the period t during which the F.REF component leaks out. Turned off by the circuit. And during that time, the lock voltage just before turning off the phase lock loop is held by the S / H circuit, and the VCO is operated by the voltage, so that the spurious by F.REF is removed. Made possible.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment according to the present invention is shown in FIGS.
FIG. 1 is a block diagram showing a circuit configuration of the present invention. Further, FIG. 2 is an enlarged view of 1 / F · REF (for example, a lock voltage is generated every 100 μs in the case of F / REF of 10 KHz) and an enlarged view of its output waveform (F / REF component only). A point, b point,
The conceptual diagram of a period and a waveform of a signal and a control voltage at each point c is shown. (1) In the circuit configuration shown in FIG. 1, the spurious 8 due to the reference frequency F, REF, 5 does not make the cutoff frequency of the loop filter 4 extremely low, that is, the noise near the signal is deteriorated. FIG. 6 is a block diagram of a phase lock loop circuit capable of removing spurious 8 without a signal.

That is, (2) the S / H (sample and hold) circuit 9 and the one-shot multivibrator circuit 10 are provided in addition to the conventional circuit configuration. That is, for example, at 10KHz F ・ REF5, phase lock ・
When driving the loop, the one-shot multivibrator 10 creates the control voltage at point c from the 100 μs F / REF5 component at point a 15 and inserts S / between the phase detector 3 and VCO1. H circuit 9
Drive. As a result, it is possible to hold the voltage immediately before that during the period t13 when the F.REF5 component leaks and to drive in the sampling state during the other periods.

(3) As shown in FIG. 2, the lock voltage 11, which is the output from the phase detector 3 divided by N by the programmable divider 2, is F. The REF5 component leaks out, which causes FR
Spurious 8 occurs at EF distance. Therefore, in the present invention,
C point 17 created by the one-shot multivibrator 10 only during the period t13 when the component of F / REF5 leaks.
The S / H circuit 9 is held at the voltage immediately before the period t13 in which the FREF component leaks by the control voltage in the above condition, and the VCO 1 is operated.

As shown at (4) point b 16, for example, 1
In the case of FKREF5 of 0 KHz, the sampling state is set to 95 μs in a cycle of 100 μs, and the remaining t13 is sufficiently large to turn on and off, so that no frequency shift occurs. Also, instead of making the control voltage at point c 17 by the one-shot multivibrator 10,
It is also possible to adopt a method of controlling using a CPU.

(5) Spurs 8 are periodically generated in synchronization with the reference frequency F.REF5. And that waveform,
Time, etc. is one of the components of the circuit
It depends on the performance of the detector 3. Therefore, various countermeasures exist. Therefore, in the present invention, the lock voltage 11 is sampled by the S / H circuit 9 at a voltage that does not include the leakage immediately before the spurious 8 occurs, and the phase lock loop circuit is turned on to operate. The spurious 8 is generated and only the part of the voltage that it contains is held and turned off, and only the spurious 8 removed is applied to the VCO 1 circuit. Therefore, by using a circuit configuration based on such an extremely simple principle, the output F
・ OUT6 does not deteriorate the noise near the signal,
Does not include spurious 8 due to leakage of reference frequency 5, F
・ OUT = N × F ・ REF7 can be output.

[0015]

Since the present invention is configured as described above, it has the following effects. (1) Using the F / REF signal, the control voltage of the S / H circuit is created by the one-shot multivibrator circuit, and the S / H circuit is held only during the period when the F / REF component of the lock voltage leaks. , It was possible to suppress the spurious due to the F / REF component by the simple principle that the F / REF leakage component is not transmitted to the VCO. (2) Since the circuit configuration of the present invention improves, it is mass-produced by incorporating a programmable divider and a phase detector that divide by N, and it is a low-priced, multifunctional PLL.
・ IC (for example, SOP / 24PIN configuration) can be applied to the circuit, and downsizing and cost reduction of the circuit have been realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a phase lock loop according to the present invention.

FIG. 2 shows a lock voltage waveform for each 1 / F · REF and its enlarged view, and a conceptual diagram of a cycle and a waveform of a control voltage in the circuit configuration of the present invention.

FIG. 3 is a block diagram showing a circuit configuration of a conventional phase lock loop.

FIG. 4 is a conceptual diagram showing that spurious due to leakage occurs in synchronization with each basic frequency F · REF.

[Description of sign]

 1 Voltage controlled oscillator 2 Programmable divider 3 Phase detector 4 Loop filter 5 Reference frequency F / REF 6, 7 Output F / OUT 8 Spurious 9 Sample and hold (S / H) circuit 10 One-shot multivibrator Circuit 11 Lock voltage waveform 12 1 / F · REF 13 Period t 15 a point 16 b point 17 c point

Claims (2)

[Claims] 1. A phase detector (3) and a VCO (1)
A phase-lock loop circuit, characterized in that a sample-and-hold circuit (9) is provided between and. 2. The phase lock loop circuit according to claim 1, wherein a period t from which the reference frequency F.REF (5) component leaks is t.
The phase lock loop is turned off only during (13), and the control voltage (17) that holds the voltage immediately before turning off in other periods is generated, and its output is output to the sample and hold circuit. A phase-locked loop circuit provided with a one-shot multivibrator (10) to be provided to the drive terminal of (9), characterized by the above.