JP2929925B2 - Quadrature demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature demodulator for demodulating a four-phase modulated signal, in which a clock recovery circuit is digitized and an all-digital digital demodulator.

[0002]

2. Description of the Related Art The configuration of a conventional quadrature demodulator is shown in FIG.

In FIG. 1, a conventional quadrature demodulator is provided with a distributor 1 which inputs a modulated wave to a terminal 30 and divides the modulated wave into two, and which has two oscillation outputs and outputs a first oscillation output and a second oscillation output. Characterized in that there is a phase difference of 90 degrees in the oscillator 4.
A first frequency converter 2 that outputs a difference component between a first output frequency of the divider 1 and a frequency component of the first oscillation output; a second output frequency of the divider; A second frequency converter 3 for outputting a difference component from the frequency component of the oscillation output of the second 2, and a first analog-to-digital converter 5 for performing an analog-to-digital conversion on the output of the first frequency converter 2.
A second analog-to-digital converter 6 for converting the output of the second frequency converter 3 from analog to digital; an output of the first analog-to-digital converter 5 and an output of the second analog-to-digital converter 6 And a demodulator 7 for performing quadrature demodulation on the reproduced carrier wave applied from the digital carrier regenerator 8 and outputting first and second digital data strings (P and Q) orthogonal to each other. A digital carrier regenerator 8 for outputting the reproduced carrier by the second digital data sequence, and a clock for extracting a clock component of the digital data by the first digital data sequence and the second digital data sequence A clock phase error detector 9 for detecting a phase error of
A digital-to-analog converter 22 that performs digital-to-analog conversion on the output of the clock phase error detector 9, and a variable reference signal generator 23 (for example, a VCXO (voltage control crystal) that is frequency-controlled by the output signal of the digital-to-analog converter 22. And a DDS 10 (Direct Digital) controlled by inputting the output of the variable reference signal generator 23 to a reference clock input 51.
Synthesizer), a fixed data generator 25 for providing fixed digital data to the frequency control data input 52 of the DDS 10, and converting the output frequency of the DDS 10 to M / N (M and N are integers of 1 or more) times. A clock frequency converter 12 for supplying a sampling frequency signal of the first and second analog-to-digital converters and a clock signal of the demodulator 7, the digital carrier regenerator 8, and the clock phase error detector 9. And consisted of To recover the clock of the demodulator, the output of the clock phase error detector 9 is converted into an analog signal by the digital / analog converter 22 and the digital / analog converter 2
2 by controlling the output frequency of the variable reference signal generator 23 by the analog signal output of the DDS 10
Had control.

The prior art is disclosed in Japanese Patent Laid-Open No. 4-309.
No. 014, the V.V.
Since a highly stable reference signal generator 23 such as CXO is used, an analog circuit is required.

[0005]

The presence of an analog circuit in the clock recovery operation of the quadrature demodulator has the disadvantage that the circuit configuration is complicated, the scale becomes large, and the circuit needs to be adjusted.

[0006]

SUMMARY OF THE INVENTION A quadrature demodulator according to the present invention comprises:
In a quadrature demodulator for receiving and demodulating a four-phase modulated wave, a distributor for inputting and dividing a modulated signal into two, and a second oscillator having a phase difference of 90 ° between the first oscillation output and the first oscillation output. An oscillator for transmitting an output, a first frequency converter for performing frequency conversion between a first output signal of the distributor and the first oscillation output, a second output signal of the distributor and the second
A second frequency converter that performs frequency conversion with the oscillation output of the first, a first analog-to-digital converter that converts the output of the first frequency converter from analog to digital, and an output of the second frequency converter. A second analog-to-digital converter for performing analog-to-digital conversion, and quadrature demodulation of an output of the first analog-to-digital converter and an output of the second analog-to-digital converter with a reproduced carrier provided from a digital carrier regenerator. A demodulator for outputting first and second digital data streams orthogonal to each other, a digital carrier regenerator for outputting the reproduced carrier wave using the first digital data stream and the second digital data stream,
A clock phase error detector for detecting a clock phase error of the digital data based on the digital data sequence and the second digital data sequence, and a digital output of a plurality of bits of the clock phase error detector input to a frequency control input terminal. A direct digital synthesizer (hereinafter, referred to as DDS) for inputting a reference frequency signal having a fixed frequency to a reference clock input terminal and outputting a reproduced clock; and converting the output frequency of the DDS to the first digital synthesizer.
And a clock frequency converter for supplying a clock signal to the second analog-to-digital converter, a sampling signal, the demodulator, the digital carrier regenerator, and the clock phase error detector. .

[0007]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The input modulated wave is distributed to a first frequency converter 2 and a second frequency converter 3 by a distributor 1, and two oscillator outputs having a phase difference of 90 degrees from an oscillator 4 generate a first frequency converter. The frequency converter 2 and the second frequency converter 3 are the distributor 1
And the difference component of the frequency of the oscillation output from the oscillator 4 is output. First frequency converter 2 and second frequency converter 3
The conversion output of the first analog-to-digital converter 5 and the second
Is converted into a digital signal by the analog-to-digital converter 6. The digital signal outputs of the first analog-to-digital converter 5 and the second analog-to-digital converter 6 are demodulated by the demodulator 7 with the reproduced carrier of the digital carrier regenerator 8. The digital data string of the demodulated output of the demodulator 7 becomes a P output and a Q output. The two orthogonal digital data strings are sent to a digital carrier regenerator 8 and a clock phase error detector 9. The digital carrier regenerator 8 outputs a reproduced carrier using a digital data sequence. Clock phase error detector 9
Detects a phase error of a clock from a digital data string, inputs the detected error to a frequency control input 52 of the DDS 10 using a digital signal of a plurality of bits, and outputs a reproduced clock. The reference signal generator 11 inputs a reference clock input 51 of the DDS 10 and provides a fixed reference signal. As a result, the DDS 10 can be operated without using the digital-to-analog converter of the output of the clock phase error detector and the reference signal generator, which have been required conventionally. The output of the DDS 10 is converted to M / N (M and N are integers equal to or greater than 1) by a clock frequency converter 12, and converted into a first analog-to-digital converter 5, a second analog-to-digital converter 6, a demodulator 7, and a digital carrier. It is supplied to a regenerator 8 and a clock phase error detector 9.

[0009]

As described above, the following effects can be obtained by the present invention.

(1) Since a large-scale and complicated analog circuit replaces a digital circuit, the circuit can be simplified and the device can be downsized.

(2) The adjustment required for the analog circuit is eliminated, and the cost during manufacturing can be reduced. 3 clock
Modulation clock frequency because DDS is used for reproduction circuit
Automatically resets the clock without any adjustment
I can live.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Divider 2 1st frequency converter 3 2nd frequency converter 4 Oscillator 5 1st analog-digital converter 6 2nd analog-digital converter 7 Demodulator 8 Digital carrier regenerator 9 Clock phase error detector 10 DDS 11 Fixed reference signal generator 12 Clock frequency converter 22 Digital-to-analog converter 23 Variable reference signal generator 25 Fixed digital data output unit

Claims (1)

(57) [Claims] 1. A quadrature demodulator for receiving and demodulating a four-phase modulated wave, comprising: a distributor for inputting and dividing a modulated signal into two parts; and a first oscillation output and a phase difference of 90 ° between the first oscillation output and the first oscillation output. An oscillator for transmitting a second oscillation output, a first frequency converter for performing frequency conversion between a first output signal of the distributor and the first oscillation output, and a second output of the distributor. A second frequency converter that performs frequency conversion between a signal and the second oscillation output; a first analog-to-digital converter that performs analog-to-digital conversion on an output of the first frequency converter; and the second frequency A second analog-to-digital converter for converting the output of the converter from analog to digital, and a reproduced carrier wave provided from a digital carrier wave regenerator with the output of the first analog-to-digital converter and the output of the second analog-to-digital converter A demodulator that performs quadrature demodulation and outputs first and second digital data sequences orthogonal to each other, and a digital carrier regenerator that outputs the reproduced carrier using the first digital data sequence and the second digital data sequence A clock phase error detector for detecting a clock phase error of the digital data based on the first digital data stream and the second digital data stream; and a clock phase error detector connected to a frequency control input terminal.
Input the multi-bit digital output of the
Input a fixed frequency reference frequency signal to the
Direct digital synthesizer that outputs raw clock
And converting the output frequency of the DDS to the first and second signals.
Sampled signal to the analog-to-digital converter, the demodulator,
A quadrature demodulator comprising: the digital carrier regenerator; and a clock frequency converter that supplies a clock signal to the clock phase error detector.