JP3359927B2 - Demodulator for quadrature amplitude modulation digital radio equipment. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to 2 ²ⁿ (n = 1,2,3,3)
...) The present invention relates to a demodulation device for a value quadrature amplitude modulation digital radio device, and more particularly to an improvement of an abnormal synchronization prevention circuit in the demodulation device.

[0002]

2. Description of the Related Art In recent years, various communication systems have been developed with an increase in communication needs and development of communication technology, and among them, there is a digital microwave radio communication system. This type of system uses, for example, a quadrature phase modulation (QPSK; Quadrature Phase Shift Keyin)
g) method and multi-level quadrature amplitude modulation (multi-level QAM; Quadrature
Digital data is wirelessly transmitted by modulation using the Amplitude Modulation (Amplitude Modulation) method. Compared to analog wireless transmission systems and wired digital transmission systems, low-cost and high-quality data transmission is possible.

Here, Q which is a typical example of quadrature modulation is used.
Considering AM, this is a method in which both the amplitude and phase of a carrier are changed, and by thus simultaneously converting two parameters, more efficient modulation can be realized. . In principle, this is realized by combining two orthogonal AM (amplitude modulation) waves, and the resulting signal is called a QAM wave.

[0004] This QAM wave is the simplest and easy-to-handle AM.
It plays an important role in multi-level transmission because it can be made based on waves and any point on the phase plane can be selected as a code point, so that an ideal code arrangement can be realized. The quantization value of each of the two orthogonal AM waves is divided into a binary value and a multivalued value that is larger than the binary value. The latter is called multi-valued QAM.

Here, the basic principle of QAM will be briefly described. Although the characteristics of QAM are actually utilized in multi-level transmission of 16 levels or more, for the sake of simplicity, we will take up 4-level transmission. As with the analog modulation method, there are three basic modulation methods for modulating a sine carrier with a digital signal: amplitude modulation, phase modulation, and frequency modulation. In the case of digital modulation, these are ASK (Amplitude Shift Keying). , PSK (Phase Shift Keying; phase modulation), FS
Also called K (Frequency Shift Keying).
In general, equal intervals (2π /
A method of performing signal transmission using n code points arranged at (n intervals) is called n-phase PSK, but n-phase PSK is actually used.
= 2 ^m (Where m is a natural number), where 2
Transmission of the value pulse m sequence becomes possible.

Now, two two-phase PSK (Phase Shift Keyi)
ng; phase modulation) wave is synthesized at a right angle to obtain a four-phase PSK wave. However, since a two-phase PSK wave can be realized by a binary ASK wave, a four-phase PSK signal is expressed by E (t) and two two-phase PSK signals.
The K signal is e ₁ (t) and e ₂ (t), and the angular frequency is ω _c
In other words, it can be expressed as in equation (1).

[0007]

(Equation 1) Here, ψ ₁ (t) and ψ ₂ (t) both indicate the waveforms of independent binary baseband signals (modulated signals), and are set as follows.

[0008]

(Equation 2) E (t) can also be written as follows using the combined amplitude (envelope) and phase angle:

[0009]

(Equation 3)

The bandwidths of ψ ₁ (t) and ψ ₂ (t) are not unlimited, and are generally band-limited, so that they are smaller than “1” at times other than the center point (sample time) of the pulse. Therefore, the absolute value of E (t) is also smaller than "1". Considering the vector diagram of FIG. 5, this indicates that the trajectory of E (t) transitions on the square ABCD and its diagonal lines AC and BD. Although E (t) is different from a pure PM wave, Since only the sample time satisfies the condition of constant amplitude, it can be regarded as a PSK wave. A signal obtained by combining two orthogonal AM waves like E (t) is a QAM wave. FIG. 6A shows a code arrangement on a two-dimensional phase plane in the case of 16 values, which is a lattice arrangement QAM. FIG. 6B shows PSK.

[0011] A grid-like arrangement QAM as shown in Fig. 6 (a) has a relatively good SN characteristic, and an orthogonal modulation / demodulation technique for applying information to a sin component and a cos component of a carrier can be applied. The grid QAM has two orthogonal n values (usually n = 2 ^m ) Is obtained by combining two AM signal waves, n ² Have code points.

Now, let ψ ₁ (t) and ψ ₂ (t) be baseband pulses (modulated signals) having n-valued amplitudes, respectively.
_{If the} maximum value of each of the absolute values of ₁ (t) and ψ ₂ (t) is “1”, the general formula of the waveform E (t) of the QAM wave of unit amplitude is the same as the formula (1). Become. And E (t) is 2 ^2m
If m = 1, 4
The two code points are all equidistant from the origin, and the four-phase PS
It matches the code arrangement of K. The case of m = 2 is called 16QAM, the case of m = 3 is called 64QAM, and the case of m = 4 is called 256QAM. For a QAM wave, one that satisfies the condition that information is contained in both the amplitude and the phase is 1
6 or more. Therefore, for QAM waves, 16QA
M is used, but the modulation method widely used in recent digital radio systems is 16QAM.

When reproducing a digital radio signal modulated by multi-level QAM in this way, demodulation must be synchronous detection because information is included in both the amplitude and the phase. Taking a 16QAM wave as an example, a received carrier is branched into two, and two reference carriers having phases different from each other by 90 ° (QAM is a combination of two orthogonal AM waves, so one of two orthogonal axes is used. Are used as the I-axis and the other as the Q-axis, two types of reference carriers having a phase of the I-axis and a reference carrier having a phase of the Q-axis are used). And, by the detection output of each of the I axis and the Q axis,
Of the 16 codes, which code is received is determined by a classifier that performs the identification, and four series of binary pulses are reproduced according to the type.

By the way, a typical method for producing a reference carrier for providing a phase reference at the time of synchronous detection is as follows. One is to provide an independent carrier oscillator (usually using a voltage controlled oscillator VCO) in the receiver, and to obtain a reference carrier by controlling the phase of this carrier oscillator to be constant. In this method, a part of a received signal is branched, a delay of one time slot is given thereto, and the resultant signal is used as a reference carrier for a subsequent pulse. The latter method is used for differential detection, and therefore, the former method is generally used.

In the PSK synchronous detection method, the phase reference must be obtained from the received wave transmitted. However, since the phase of the PSK received wave changes every moment due to modulation, a constant control signal canceling this modulation is used. The signal is fed back to the voltage controlled oscillator to obtain a reference phase. One of the methods for eliminating the influence of the modulation is a frequency multiplication method or an inverse modulation method.

The frequency multiplication method is called a baseband processing type because it multiplies a demodulated signal in a baseband, and a carrier recovery circuit of the baseband processing executes a logical operation of the demodulated signal in the baseband. There is a type in which the phase is multiplied in an equalizing manner, and the phase of the reference oscillator is controlled by the output, and this is also called a Costas type carrier recovery circuit.

In general, when the carrier recovery circuit is of the Costas type, the circuit can be made cheaper and simpler than the inverse modulation system, and is advantageous in terms of economy and low power consumption. Is done. However, while having such advantages, the Costas-type carrier recovery circuit has a problem in that in the case of low-speed transmission, abnormal synchronization occurs in which the carrier frequency is stabilized at a frequency different from the normal carrier frequency.

[0018]

SUMMARY OF THE INVENTION As described above, multi-value QA
When reproducing a digital radio signal modulated by M,
Synchronous detection is performed, and this synchronous detection requires a reference carrier that provides a phase reference. In order to obtain a reference carrier, a carrier recovery circuit is used. In this case, an independent carrier oscillator (usually using a voltage controlled oscillator VCO) is provided in the receiver, and the phase of the carrier oscillator is controlled to be constant. Thus, a method called a Costas type for obtaining a reference carrier is used. The phase reference must be obtained from the received wave. However, since the phase of the PSK received wave changes every moment due to the modulation, a constant control signal that cancels out the modulation is fed back to the voltage controlled oscillator. As one of economical methods for eliminating the influence of the modulation, there is a method of multiplying the frequency.

The frequency multiplication method is called a baseband processing type. As a carrier recovery circuit of the baseband processing type, a logic operation of a demodulated signal is executed in a baseband band to multiply the phase in an equal manner. There is a type that performs phase control of a reference oscillator by its output, and this is also called a Costas-type carrier recovery circuit.

In general, when the carrier recovery circuit is of the Costas type, the circuit can be made cheaper and simpler than the inverse modulation system, and is advantageous in terms of economy and low power consumption. Is done.

On the other hand, if the carrier recovery circuit is of the Costas type, there is a problem that abnormal synchronization occurs in which carrier synchronization becomes abnormal at a frequency different from the normal carrier frequency during low-speed transmission. If the carrier recovery loop characteristic is changed in order to solve the above-mentioned problem in a form, there arises a problem that the pull-in frequency and the composite modulation characteristic deteriorate.

Therefore, an object of the present invention is as follows.
It is an object of the present invention to provide a digital radio apparatus capable of preventing abnormal synchronization at low cost and without deteriorating transmission characteristics in the Costas system.

[0023]

In order to achieve the above object, the present invention is configured as follows. That is, it is used for demodulation of a quadrature amplitude modulation type digital radio apparatus, and identifies a demodulated baseband signal to obtain a phase error signal therefrom, and oscillates at an oscillation frequency according to a control signal to obtain a reproduced carrier. The phase error signal is supplied to the oscillating means as a control signal to control oscillation, and the reproduced carrier wave
In a demodulation device that obtains a demodulated baseband signal by mixing each of the received signals with a 0 ° phase difference,

Monitoring means for monitoring carrier out-of-synchronization based on the demodulated baseband signal and outputting a carrier out-of-synchronization alarm signal when carrier out-of-synchronization occurs; and reception data demodulated based on the demodulated baseband signal. Abnormal synchronization detection means for sampling the demodulated eye pattern at twice the transmission speed of the received data, detecting torsional data from the detection area of the sampled data to detect abnormal synchronization, and the carrier out-of-sync alarm signal. Absence, abnormal synchronization prevention means for generating a signal for a predetermined time when abnormal synchronization is detected, and a reference signal for oscillating a signal having a reference carrier frequency close to the frequency of the carrier and the phase error signal, Normally, the phase error signal is selected as the control signal, and the reference signal is controlled while receiving the signal generated by the abnormal synchronization prevention means. Select a signal configured by including a selection means for applying to said oscillating means.

[0025]

In such a configuration, a demodulated baseband signal is identified, a phase error signal is obtained from the demodulated baseband signal, and this is supplied to an oscillating means as a control signal. A carrier is obtained, and the reproduced carrier is mixed with a received signal with a phase difference of 90 ° to obtain a demodulated baseband signal. The received data is reproduced based on the demodulated baseband signal. If the reproduced carrier does not match the carrier frequency of the received signal, the received data that has been reproduced will not be correct due to loss of carrier synchronization, and the data will not be reproduced correctly.
However, in the case of a signal having a low transmission rate, abnormal synchronization may occur in which synchronization with a reproduced carrier wave in synchronous detection is stabilized at a frequency different from the original carrier frequency,
In this case, the data cannot be correctly reproduced.

Therefore, in the present apparatus, the monitoring means monitors the carrier out-of-synchronization based on the demodulated baseband signal,
Also, the demodulated eye pattern of the received data demodulated based on the demodulated baseband signal by the abnormal synchronization detection means is sampled at twice the transmission speed of the received data, and the torsion of the data is detected from the detection area of the sampled data. Then, abnormal synchronization is detected, and when the abnormal synchronization is detected, the abnormal synchronization preventing means generates a signal for a predetermined time under the condition that there is no loss of carrier wave synchronization.
The selection means receives the phase error signal and a reference signal for oscillating a signal having a reference carrier frequency close to the frequency of the carrier, and normally selects the phase error signal as the control signal. While receiving the generated signal, the reference signal is selected as the control signal and supplied to the oscillating means.

As a result, when abnormal synchronization, which is a synchronous detection state by a reproduced carrier having a frequency different from the original carrier frequency, occurs, the oscillation of the oscillation means is controlled based on the reference signal for a predetermined time, and thereafter, the demodulation base is controlled. The oscillation control of the oscillating means is performed by the phase error signal based on the band signal, but the oscillation control of the oscillating means based on the reference signal is a frequency approximate to the carrier frequency of the received signal. As a result, the demodulation system is in a state very close to the correct phase, and from this state, synchronization is started by the phase error signal, so that correct synchronization can be obtained.

In particular, in the present invention, the demodulated eye pattern of the received data demodulated based on the demodulated baseband signal by the abnormal synchronization detecting means is sampled at a speed twice as high as the transmission speed of the received data. By checking the state of the signal at the point, normal synchronization and abnormal synchronization are determined based on the state of the demodulated eye pattern,
Since abnormal synchronization is determined, abnormal synchronization can be detected by a simple method, and when the out-of-synchronization alarm is determined to be normal synchronization, the carrier wave recovery loop is temporarily cut off and a frequency very close to normal synchronization is generated. Since the normal synchronization is performed by returning to, the demodulation device of the quadrature amplitude modulation type digital radio apparatus which can prevent the abnormal synchronization with the simple configuration and thus can prevent the abnormal synchronization can be provided. can get.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an IF modulation wave input terminal for inputting a modulation IF (intermediate frequency) signal, and reference numerals 2a and 2b denote mixers, which respectively receive the modulation IF signals input from the IF modulation wave input terminal 1 and have a 90 ° angle. The output is mixed with the output of the power distributor 10.

3 is a clock recovery circuit, 4 is a discriminator, 5 is a demodulation logic circuit, 6 is a digital logic operation unit, 7 is a data selector, 8 is an amplifier with a loop filter, 9 is a voltage controlled oscillator, and 11 is a reproduced carrier wave synchronization. A departure monitoring circuit, 12 is a phase error signal generation circuit, and 13 is an abnormal synchronization prevention circuit.

The discriminator 4 is constituted by an analog-digital converter (A / D converter), which converts signals input from the mixers 2a and 2b into digital signals and outputs the digital signals. The 90 ° power divider 10 converts the carrier wave to 90
The phase difference is given to output signals of two systems having different phases.
, And the other is input to the mixer 2b, and the mixers 2a and 2b output the difference signal obtained by mixing these signals with the modulated IF signal supplied through the input terminal 1. Output. Here, mixer 2
The output of a will be referred to as the Ich output, and the output of the mixer 2b will be referred to as the Qch output.

The clock recovery circuit 3 outputs the Ich output,
In response to the Qch output, the transmission clock signal is reproduced and output from these outputs.
The D converter operates in synchronization with a clock signal (double clock signal) twice as large as the clock signal output from the clock recovery circuit 3 to convert the Ich output into digital data. The other A / D converter operates in synchronization with a clock signal twice as high as the clock signal output from the clock recovery circuit 3 (doubled clock signal) to convert the Qch output into digital data.

One A / D converter of the discriminator 4 has Ich
A demodulated baseband signal of a sequence is supplied to the other A / D converter, and a demodulated baseband signal of a Qch sequence is supplied to the other A / D converter. The demodulated baseband signal is synchronized with the A / D converter in synchronization with the clock signal. Is converted into a digital signal, and each of Ich and Qch is, for example, three series of identification data.
The configuration is such that SI1, SI2, SI3, SQ1, SQ2, and SQ3 are separately output (example of 4PSK).

Now, assuming that Ich is the horizontal axis of the orthogonal axes and Qch is the vertical axis of the orthogonal axes in FIG. 7, the identification data SI1 is the first of the data phase planes indicated by the orthogonal axes I and Q.
Alternatively, depending on whether there is data in the second quadrant or data in the third or fourth quadrant, the former outputs data as, for example, "1" and the latter outputs "0", and SI2 is the first and second data. Data is output as "1" in the former and "0" in the latter depending on whether there is data in the upper half or lower half of the quadrant or the third and fourth quadrants,
SI3 indicates “1” on the upper side and “0” on the lower side in that section depending on which half of the area has data. If SQ1 has data in the first or fourth quadrant, "1", if there is data in the second or third quadrant, output data as "0". In SQ2, is there data in the right half in the first and fourth quadrants or the second and third quadrants? For the former, data is output as "1" depending on whether there is data in the left half, and as "0" in the latter, data is output as "0". 1 "and" 0 "on the left, it is possible to identify in which region the signal appears. This is because the signal levels of the I-axis and the Q-axis correspond to the respective resolutions corresponding to the respective categories. A / D conversion A / D obtained by performing
Since it is possible to correspond to the output for each resolution of the converter (output at each bit position), data obtained by converting each channel component of I and Q by the A / D converter is used as identification data.

The demodulation logic circuit 5 outputs these identification data SI1,
It receives SI2, SI3, SQ1, SQ2, and SQ3 and operates on the data to obtain demodulated data for each of the I and Q channel components. The demodulated data is output to the digital logic operation unit 6. The identification data SI1, SI2, SI3, SQ1, SQ2,
For SQ3, SI1 and SQ1 will be referred to as first path identification data, SI2 and SQ2 will be referred to as second path identification data, and SI3 and SI3 will be referred to as third path identification data, as required.

Further, the data selector 7 outputs a phase error signal at the time of normal synchronization in synchronous detection (when synchronous detection is synchronized with a reproduced carrier having a frequency matching the original carrier frequency), At the time of abnormal synchronization (when synchronous detection is synchronized with a reproduced carrier having a frequency different from the original carrier frequency), a predetermined reference bias signal is output. This switching is performed by the abnormal synchronization detection signal to be performed, and the output is switched.

Accordingly, the data selector 7 receives the phase error signal and the reference bias signal, selects the reference bias signal while receiving the abnormal synchronization detection signal, and selects and outputs the phase error signal when the abnormal synchronization detection signal disappears. Configuration.

The phase error signal is obtained by calculating the identification data SI 1, SI 2, SI 3, SQ 1, SQ 2, and SQ 3 output from the discriminator 4 to obtain carrier phase information. From this, a voltage signal of a level corresponding to the carrier phase information is obtained. The phase error signal generation circuit 12 realizes such a function.

The reference bias signal is a signal output from the reference voltage generator 9a, and its level is set so that the VCO (voltage controlled oscillator) 9 can oscillate at a predetermined reference carrier frequency. The DC amplifier 8 with a loop filter amplifies the level of the signal output from the data selector 7.

The VCO 9 generates a signal of a frequency corresponding to the level of the carrier phase information corresponding to the level of the carrier wave phase information obtained from the DC amplifier 8 with a loop filter, and uses the signal as a reproduced carrier wave signal at 90 ° power. This is given to the distributor 10. The 90 ° power splitter 10 applies a 90 ° phase difference to the recovered carrier signal, and outputs the two recovered carrier signals having the 90 ° phase difference to one of the mixers 2.
a and the other is input to the mixer 2b as a local signal. By inputting the reproduced carrier signal having the 90 ° phase difference as described above as a local signal to the mixers 2a and 2b and mixing it with the signal from the input terminal 1, the carrier can be removed and the data can be demodulated.

The reproduced carrier out-of-synchronization monitoring circuit 11 monitors the carrier out-of-synchronization, and outputs an alarm signal (out-of-synchronization alarm signal) when the out-of-synchronization occurs. Monitor for detachment.

The phase error signal generating circuit 12 is a circuit for generating a phase error signal which is a signal indicating a phase difference between the frequency of the reproduced carrier and the frequency of the original carrier. As described above, this phase error signal is discriminated. This is obtained by calculating the identification data SI1, SI2, SI3, SQ1, SQ2, and SQ3 output from the detector 4 to obtain carrier wave phase information, and converting it into a voltage signal having a level corresponding to the carrier wave phase information. The reference bias signal is supplied to the reference voltage generation circuit 8.
You are getting more.

Further, the abnormal synchronization prevention circuit 13 receives the out-of-synchronization alarm signal and the abnormal synchronization detection signal. A detection signal is output and given to the data selector 7.

Reference numeral 7a denotes a phase error signal input terminal of the data selector 7 for inputting a phase error signal.
Reference numeral b denotes a reference bias signal input terminal for inputting a reference bias signal, and reference numeral 7c denotes a carrier recovery circuit control signal output terminal for outputting a carrier recovery circuit control signal to be supplied to the VCO.

Next, the operation of the demodulation system having the above configuration will be described.
The IF modulated wave input from the IF modulated wave input terminal 1 is detected by the mixers 2a and 2b to obtain a demodulated baseband signal. On the other hand, a clock signal is generated by the clock reproducing circuit 3, and the discriminator 4 discriminates the demodulated baseband signal at the synchronization timing while synchronizing the demodulated baseband signal with the clock signal, and converts it into identification data.

The identification data is supplied to the demodulation logic circuit 5, and the demodulation logic circuit 5 performs a logical operation on the identification data to obtain demodulated data. The obtained demodulated data is output after being synchronized with the frame by the digital logic operation unit 6.

The phase error signal generation circuit 12 of the carrier wave recovery system detects carrier wave phase error information from the identification data output from the discriminator 4, and outputs the data selector 7 from the phase error signal input terminal 7a as a carrier wave phase error signal. Give to. The data selector 7 sends this carrier wave phase error signal to the amplifier 8 with the loop filter during normal synchronization. The amplifier 8 with the loop filter amplifies the error information signal and supplies it to the voltage controlled oscillator 9.
In this case, the oscillator oscillates at an oscillation frequency corresponding to the error information signal, thereby generating a reproduced carrier wave synchronized with the carrier clock.

The regenerated carrier wave from the voltage controlled oscillator 9 is supplied to a 90 ° power splitter 10 where the 90 ° power splitter 1
At 0, the reproduced carrier is given a phase difference of 90 ° and the carrier is used as a local input to the mixers 2a and 2b. Then, the mixers 2a and 2b mix the local input and the received signal from the input terminal 1 and detect it. Further, the reproduction carrier out-of-synchronization monitoring circuit 11 monitors the carrier out-of-synchronization, and outputs an alarm signal when out-of-synchronization.

On the other hand, the abnormal-synchronization preventing circuit 13 is configured to generate an output only when abnormal synchronization is detected without an out-of-synchronization alarm signal (carrier out-of-synchronization alarm signal) from the reproduced carrier out-of-synchronization monitoring circuit 11. To prevent erroneous determination of carrier synchronization loss and abnormal synchronization.

As described above, when there is no out-of-synchronization alarm signal, that is, when abnormal synchronization is detected while the carrier waves are synchronized, an abnormal synchronization detection signal is output from the abnormal synchronization prevention circuit 13 for a certain period of time. The data is supplied to a select signal input terminal of the data selector 7.

As described above, the data selector 7 applies the phase error signal input from the phase error signal input terminal 7a to the carrier recovery circuit control signal output terminal 7c during normal synchronization (that is, when abnormal synchronization is detected). Output,
This phase error signal is applied to a voltage-controlled oscillator (VCO) 9 at a subsequent stage through a DC amplifier 8 with a loop filter,
The reference carrier is reproduced from CO9.

Here, abnormal synchronization, which is a phenomenon in which synchronization occurs due to a reproduced carrier having a frequency different from the original carrier frequency (carrier clock), occurs, and an abnormal synchronization detection signal is output from the abnormal synchronization prevention circuit 13 to the select terminal of the data selector 7. , The data selector 7 switches the selection of the input to the reference bias signal input terminal 7b side, and converts the predetermined reference bias signal input from the reference bias signal input terminal 7b to the carrier wave reproduction circuit control signal output terminal. 7c. Then, the reference bias signal is amplified by the DC amplifier 8 with a loop filter and then applied to the VCO 9 as a reference voltage, so that the VCO 9 oscillates at a frequency corresponding to the reference bias signal.

The reference bias signal is supplied to a reference voltage generator 9.
Since the level of the signal is such that the VCO (voltage controlled oscillator) 9 can oscillate at the reference carrier frequency, the voltage controlled oscillator 9 oscillates at the reference carrier frequency. However, since there is no phase error information, carrier wave synchronization is lost.

After a predetermined time, when the abnormal synchronization detection signal is no longer output from the abnormal synchronization prevention circuit 13, the data selector 7 switches the input from the reference bias signal input terminal 7b to the phase error signal input terminal 7a. Reference numeral 7 outputs the phase error signal input from the phase error signal input terminal 7a again from the carrier recovery circuit control signal output terminal 7c, and supplies it to the VCO 9 to start pulling in synchronization.

The system was operated by the reference carrier having a frequency very close to the frequency of the original carrier oscillated by the above-described reference bias signal until immediately before the start of the synchronization pull-in. Start with frequency.

As described above, during abnormal synchronization, the carrier recovery loop starts pulling in synchronization from a frequency very close to the reference carrier oscillated by the above-described reference bias signal. Can be obtained.

Next, a specific embodiment of the abnormal synchronization prevention circuit 13 used in the present invention will be described with reference to FIG. In FIG. 2, reference numeral 4 denotes the above-described discriminator, and reference numerals 4a and 4b denote A / D converters constituting the discriminator 4, which are clock signals having a frequency twice as high as the clock signal output from the clock recovery circuit 3. It is driven by receiving a double clock signal (CLK × 2). 7 is the data selector described above,
Phase error signal input terminal 7a for inputting a phase error signal, reference bias signal input terminal 7 for inputting a reference bias signal
b, a carrier recovery circuit control signal output terminal 7b for outputting a carrier recovery circuit control signal to the amplifier 8.
That is, the data selector 7 is a changeover switch for selecting one of the phase error signal and the reference bias signal and outputting it to the carrier recovery circuit control signal output terminal 7c.

The above is the abnormal synchronization preventing circuit 13 according to the present invention.
The abnormal synchronization prevention circuit 13 according to the present invention includes shift registers 21a and 21b, a logic operation unit 22, AND circuits 23 and 24, and a multivibrator 25, which will be described below. Reference numeral 13a denotes an input terminal for an out-of-sync alarm signal, to which an out-of-sync alarm signal from the reproduced carrier out-of-sync monitor circuit 11 is input.

The A / D converter 4a in the discriminator 4 has an overflow (OF) / underflow (UF) output terminal. The overflow / underflow is applied to an input exceeding the upper and lower limits of quantization. Can be output.

Assuming that the A / D converter 4a identifies Ich (channel) identification data and the A / D converter 4b identifies Qch identification data, the shift register 21a Among the identification data of the A / D converter 4a, the output SI1 of the first pass (most significant digit) is sequentially shifted.
Of the identification data of the converter 4a, the output (OF) / (UF) of overflow / underflow is sequentially shifted.

The A / D converters 4a and 4b are driven by the double clock signal CLK × 2 of the reproduced clock signal. Therefore, the data of the demodulated eye pattern and the temporal intermediate between this data and the next data are obtained. Data relating to the phase arrangement of the signal at the point will be obtained alternately. Then, the shift register 21a outputs four bits from the least significant bit to monitor four consecutive bits of the output SI1 of the first pass in the identification data of the A / D converter 4a, and the shift register 21b outputs Output (OF) of overflow / underflow in identification data of A / D converter 4a
In order to obtain / (UF) as identification data at the time point shifted by 3 bits, the third least significant bit is used as an output.

The logical operation unit 22 outputs the output of the A / D converter 4b for identifying the identification data of Qch (the first output in this example).
From the pass (most significant bit output) to the fifth pass (5 from the most significant bit)
Identification data SQ1 to SQ5 up to the bit output of the bit)
Is logically operated to detect abnormal synchronization based on whether or not a signal is detected in an abnormal synchronization detection area AN described later on the phase plane. When abnormal synchronization is detected (the signal is detected in the abnormal synchronization detection area AN). (When detected).

The AND circuit 23 performs an AND logic operation on the output signal of the logical operation unit 22, the 4-bit signal output from the shift register 21a, and the third bit signal output from the shift register 21b. ,

That is, the logical operation unit 22 is provided to detect a signal in the abnormal synchronization detection area AN viewed from the Qch based on the identification data of the Qch, and the output of the shift register 21a is a condition for monitoring the synchronization abnormality. The output of the shift register 21b is output with a time lag from the signal detection output in the abnormal synchronization detection area AN as viewed from Ich. It is provided in order to do.

Therefore, the AND of the output of the logical operation unit 22, the signal of 4 bits output from the shift register 21a, and the signal of the third bit output from the shift register 21b
By taking the logic with the AND circuit 23, the abnormal synchronization detection area A
It is possible to know whether or not there is a signal detection at N.

The AND circuit 24 performs an AND logic operation between the output of the AND circuit 23 and the output of the carrier out-of-synchronization alarm signal. Things. The multivibrator 25 operates in response to the output of the AND circuit 24, and generates a signal (level "L") for a predetermined time.

The signal generated by the multivibrator 25 is supplied to the select signal input terminal of the data selector 7 as a switching signal at the time of detecting abnormal synchronization, and the switching operation of the data selector 7 is performed.

When the data selector 7 is normal, it outputs the phase error signal input from the phase error signal input terminal 7a from the carrier recovery circuit control signal output terminal 7c and gives it to the voltage controlled oscillator (VCO) 9 at the subsequent stage. Vibrator 2
When the abnormal synchronization detection signal is output from the reference numeral 5, the data selector 7 outputs the reference bias input from the reference bias signal input terminal 11 from the carrier recovery circuit control signal output terminal 7c. The voltage controlled oscillator 9 outputs the reference bias signal. The carrier out-of-synchronization alarm signal is an alarm signal output from the reproduced carrier out-of-synchronization monitoring circuit 11 when the reproduced carrier is out of synchronization.

In such a configuration, the A /
The D converters 4a and 4b drive the A / D conversion of the signals from the mixers 2a and 2b by driving with the double clock signal CLK × 2 of the reproduced clock signal.

Therefore, the data of the demodulated eye pattern and the data relating to the phase arrangement of the signal at the time intermediate point between this data and the next data are alternately obtained from the A / D converters 4a and 4b. Become. Then, the shift register 21
a outputs four bits from the least significant bit in order to monitor four consecutive bits of the output SI1 of the first pass in the identification data of the A / D converter 4a, and the shift register 21b performs A / D conversion. In order to obtain the output (OF) / (UF) of the overflow / underflow in the identification data of the detector 4a as the identification data at the time point shifted by 3 bits, the output of the third least significant bit is output from the AND circuit 23. To enter.

The logical operation unit 22 outputs the output of the A / D converter 4b for identifying the identification data of Qch (the first output in this example).
From the pass (most significant bit output) to the fifth pass (5 from the most significant bit)
Identification data SQ1 to SQ5 up to the bit output of the bit)
When a signal is detected in the abnormal synchronization detection area AN described later on the phase plane, abnormal synchronization is detected and an output is input to the AND circuit 23. Therefore, an output is output from the AND circuit 23 when abnormal synchronization occurs.

FIG. 3 shows a constellation (phase plane) of the intermediate point of the data when the demodulated eye pattern at the time of normal synchronization is sampled by the double clock. In the figure, AN is an abnormal synchronization detection area set for performing abnormal synchronization detection. FIG. 4 shows a constellation at an intermediate point of data when a demodulated eye pattern at the time of abnormal synchronization is sampled by a double clock, and AN is an abnormal synchronization detection area as in FIG.

In the quadrature amplitude modulation method (including 4PSK), when synchronous detection is performed using a carrier, the phase to be synchronized is always π / 4, 3π / 4, 5π / 4, 7π on the phase plane.
/ 4, and the constellation (phase plane signal arrangement) of the temporal intermediate point between the data is as shown in FIG.

On the other hand, if an abnormal synchronization occurs that synchronizes with a carrier having a frequency different from the original carrier frequency, the phase of synchronization changes regularly, such as π / 4 or π / 2, for each data. Signal twisting occurs in the phase plane. Since this torsion coincides with the phase arrangement of data such as π / 4 and π / 2, it does not change from the normal state at the data point, but at the intermediate point in time between the data and the next data, FIG.
Twist occurs as shown in FIG. Therefore, focusing on the above, the above-described detection area AN is provided, and when data is detected in this area, abnormal synchronization is set, thereby detecting abnormal synchronization.

Therefore, as described above, the doubled clock CLK × 2 is input to the A / D converter 4a on the I channel side, and the data between the demodulated eye pattern data and the signal point is sampled. The logic operation unit 22 sorts the identification data SQ1 to SQ5 of the first to fifth passes of the output of the A / D converter 4b on the Q channel side, which sorts whether or not the data is detected in the detection area AN. The identification data on the I channel side is subjected to arithmetic processing, and the identification data SI1 of the first pass and the sampling between signal points are shifted by the shift registers 21a and 21b.
For four consecutive bits, and A / D converter 4a
Of the overflow / underflow output (OF) / (UF) in the identification data of (3) by monitoring the signal state at the time of shifting by 3 bits (that is, sampling between signal points that are intermediate between the signal points). .

The AND circuit 24 ANDs the abnormal synchronization detection signal obtained by passing these data through the AND circuit 23 and the carrier out-of-synchronization signal.
An output is obtained when there is an abnormal synchronization detection signal and there is no carrier out-of-synchronization signal to prevent erroneous determination of carrier out-of-synchronization and abnormal synchronization. Then, the multivibrator 25 inputs an abnormal synchronization detection signal to the select signal input terminal of the data selector 7 for a certain period of time.

The data selector 7 outputs the phase error signal input from the phase error signal input terminal 7a from the carrier recovery circuit control signal output terminal 7c when normal, and sends it to the voltage control oscillator (VCO) 9 at the subsequent stage via the amplifier 8. Thus, the reference carrier is reproduced from the voltage-controlled oscillator 9.

However, when abnormal synchronization occurs and the abnormal synchronization detection signal is output from the multivibrator 25 of the abnormal synchronization prevention circuit 13 and input to the input terminal of the select signal, the input is switched by this, and the data selector 7 switches. Instead of the phase error signal, the reference bias signal input from the reference bias signal input terminal 7b is output from the carrier recovery circuit control signal output terminal 7c.

This reference bias signal is supplied to the voltage controlled oscillator 9
The reference voltage generator 9a is set at such a level that it can oscillate at a frequency close to the reference carrier, whereby the voltage controlled oscillator 9 oscillates at a frequency close to the reference carrier. However, since there is no phase error information, carrier wave synchronization is lost.

After a certain period of time, the abnormal synchronization prevention circuit 1
3 stops the output, the data selector 7 is switched back to the original state and returns to the normal state, and the phase error signal input from the phase error signal input terminal 7a is output to the carrier recovery circuit control signal output terminal 7c. Output more and start pull-in.

At this time, the carrier recovery loop outputs a playback carrier having a frequency very close to the original carrier frequency oscillated by the above-mentioned reference bias signal, and synchronization starts from the frequency of the playback carrier. Normal synchronization is obtained without abnormal synchronization.

The present invention is not limited to the embodiment described above and shown in the drawings, but may be modified as appropriate without departing from the scope of the invention.
A method is also possible in which the I and Q channels are switched, or an abnormality is detected in four regions in combination with the replaced detection regions.

As described above, the carrier recovery loop temporarily switches to the reference bias signal that can oscillate at a frequency very close to the reference carrier, instead of the phase error signal given to the voltage-controlled oscillator at the time of abnormal synchronization. The oscillator is oscillated by the reference bias signal, and synchronization is started from a frequency very close to the oscillated reference carrier, so that abnormal synchronization is not obtained but normal synchronization is obtained.

As described above, the present invention is used for demodulation of a quadrature amplitude modulation type digital radio apparatus. The present invention identifies a demodulated baseband signal, obtains a phase error signal therefrom, and oscillates at an oscillation frequency according to a control signal. The phase error signal is given as a control signal to an oscillating means for obtaining a reproduced carrier, and the oscillation is controlled, and the reproduced carrier is given a 90 ° phase difference and mixed with the received signal to obtain a demodulated baseband signal. A monitoring means for monitoring carrier out-of-synchronization based on the demodulated baseband signal and outputting a carrier out-of-synchronization alarm signal when carrier out-of-synchronization occurs; and receiving data demodulated based on the demodulated baseband signal. The demodulated eye pattern is sampled at twice the transmission speed of the received data, and data is detected from the detection area of the sampled data. Abnormal synchronization detecting means for detecting abnormal synchronization by detecting torsion of the data, abnormal synchronization preventing means 13 for generating a signal for a predetermined time when the abnormal synchronization is detected without the carrier out-of-synchronization alarm signal, While receiving a phase error signal and a reference signal for oscillating a signal having a reference carrier frequency close to the frequency of the carrier, normally selecting the phase error signal as the control signal and receiving the generated signal of the abnormal synchronization prevention means And selecting means for selecting the reference signal as the control signal and supplying the control signal to the oscillating means.

In such a configuration, the demodulated baseband signal is identified, and a phase error signal is obtained therefrom.
This is supplied to the oscillating means as a control signal, and the oscillating means oscillates in accordance with the control signal to obtain a reproduced carrier, and the reproduced carrier is mixed with the received signal with a phase difference of 90 °, thereby obtaining The demodulated baseband signal is obtained by synchronous detection, and the received data is reproduced based on the demodulated baseband signal. At this time, if the reproduced carrier is out of sync with the carrier frequency of the received signal, the reproduced received data is synchronized with the carrier. Because it will not be correct by coming off,
The oscillation frequency of the oscillation means is controlled and adjusted. However, in the case of a signal having a low transmission rate, abnormal synchronization may occur in which the reproduced carrier is stabilized at a frequency different from the original carrier frequency, and the data is not correctly reproduced.

Accordingly, in the present apparatus, the monitoring means monitors the out-of-synchronization of the carrier based on the demodulated baseband signal, and
Also, the demodulated eye pattern of the received data demodulated based on the demodulated baseband signal by the abnormal synchronization detection means is sampled at twice the transmission speed of the received data, and the torsion of the data is detected from the detection area of the sampled data. Then, abnormal synchronization is detected, and when the abnormal synchronization is detected, the abnormal synchronization preventing means generates a signal for a predetermined time under the condition that there is no loss of carrier wave synchronization.
The selection means receives the phase error signal and a reference signal for oscillating a signal having a reference carrier frequency close to the frequency of the carrier, and normally selects the phase error signal as the control signal. While receiving the generated signal, the reference signal is selected as the control signal and supplied to the oscillating means.

As a result, when abnormal synchronization occurs in the synchronous detection state by the reproduced carrier having a frequency different from the original carrier frequency, the oscillation of the oscillation means is controlled based on the reference signal for a predetermined time, and thereafter, the demodulation base is controlled. The oscillation control of the oscillating means is performed by the phase error signal based on the band signal, but the oscillation control of the oscillating means based on the reference signal is a frequency approximate to the carrier frequency of the received signal. As a result, the demodulation system is in a state very close to the correct phase, and from this state, synchronization is started by the phase error signal, so that correct synchronization can be obtained.

[0088] placed in abnormal synchronization detection means, especially in the present invention
Te, by sampling the demodulated eye pattern of the received data demodulated based on the demodulated baseband signal at twice the rate of the transmission rate of the received data, to check the state of the signal at the midpoint of the original sampling point Also
In the state of the demodulated eye pattern, normal synchronization and abnormal synchronization are determined and abnormal synchronization is determined. Therefore, abnormal synchronization can be detected by a simple method, and when the out-of-sync alarm is determined to be normal synchronization, the carrier wave is determined. After the reproduction loop is cut once, a frequency very close to the normal synchronization is generated, and then returned to the loop, the normal synchronization is performed, so that the abnormal synchronization can be prevented. Can be prevented.

[0089]

[Effect of the Invention] Thus, the demodulator of the digital radio apparatus of the multi-level quadrature modulation system the present invention is to apply the carrier recovery loop of a so-called Costas method, with a simple configuration, the teeth
A method of quadrature amplitude modulation that can prevent abnormal synchronization
A demodulator for a digital digital radio device can be provided.

[0090]

[0091]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of the abnormal synchronization prevention circuit of FIG. 1 including a peripheral portion;

FIG. 3 is a diagram of a constellation (phase plane) of an intermediate point of data when a demodulated eye pattern at the time of normal synchronization is sampled by a double clock.

FIG. 4 is a diagram of a constellation (phase plane) of an intermediate point of data when a demodulated eye pattern at the time of abnormal synchronization is sampled by a double clock.

FIG. 5 is a diagram for explaining a four-phase PSK wave by orthogonal synthesis of a binary AM signal.

FIG. 6 is a phase plane layout diagram of QAM and PSK.

FIG. 7 is a diagram for explaining identification data.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... IF modulation wave input terminal, 2a, 2b ... Mixer, 3 ... Clock regeneration circuit, 4 ... Identifier, 4a, 4b ... A / D converter, 5 ... Demodulation logic circuit, 6 ... Digital logic operation part, 7
... data selector, 7a ... phase error signal input terminal, 7b
... reference bias signal input terminal, 8 ... amplifier with loop filter, 9 ... voltage controlled oscillator, 9a ... reference voltage generator, 1
0: 90 ° power divider; 11: recovery carrier out-of-synchronization monitoring circuit; 12: phase error signal generation circuit; 13: abnormal synchronization prevention circuit; 22: logical operation unit; 23, 24: AND circuit;
25 Multivibrator, 23 Carrier recovery circuit control signal output terminal.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuru Hirama 3-1-1 Asahigaoka, Hino-shi, Tokyo Toshiba Communication Systems Engineering Co., Ltd. (56) References JP-A-1-99351 (JP, A) JP-A JP-A-3-139048 (JP, A) JP-A-3-17955 (JP, A) JP-A-61-281746 (JP, A) JP-A-63-161712 (JP, A) JP-A-5-37574 (JP) , A) Tokiko Hei 1-29324 (JP, B2) Modulation / demodulation circuit for 16QAM digital radio equipment using B-319 Reed-Solomon error correction circuit, Proc. ], Japan, September 17, 1990, p. 2-319 (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00

Claims (1)

(57) [Claims] 1. A method for demodulating a quadrature amplitude modulation type digital radio apparatus, comprising: identifying a demodulated baseband signal; obtaining a phase error signal from the demodulated baseband signal; oscillating at an oscillation frequency according to a control signal; The phase error signal is given as a control signal to an oscillating means for obtaining a carrier, and the oscillation is controlled, and the reproduced carrier has a 90 ° phase difference and is mixed with a received signal to obtain a demodulated baseband signal. Monitoring means for monitoring carrier out-of-synchronization based on the demodulated baseband signal and outputting a carrier out-of-synchronization alarm signal when carrier out-of-synchronization occurs; The pattern is sampled at twice the transmission speed of the received data, and the twist of the data is detected from the detection area of the sampled data. Abnormal synchronization detecting means for detecting and detecting abnormal synchronization; abnormal synchronization preventing means for generating a signal for a predetermined time when abnormal synchronization is detected without the carrier wave out-of-synchronization alarm signal; and the phase error signal and carrier wave A reference signal for oscillating a signal having a reference carrier frequency close to the frequency of the reference signal, and normally selects the phase error signal as the control signal, and receives the generated signal of the abnormal synchronization prevention means, while receiving the reference signal. A demodulating device for a quadrature amplitude modulation type digital radio apparatus, comprising: selecting means for selecting the control signal and supplying the control signal to the oscillating means.