JP3865893B2 - Demodulator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an angle modulation type demodulation circuit, and more particularly to a means for correcting an output frequency error of a local signal oscillator in the demodulation circuit.
[0002]
[Prior art]
In a conventional digital mobile communication system, the modulation efficiency is 1 bps / Hz (data transmission rate / occupied bandwidth), and the modulated waveform has a constant envelope with no modulation information in amplitude. Angular modulation schemes such as value FM or PLL 4-phase PSK have been adopted. In recent years, a π / 4 shift QPSK system having a higher signal transmission efficiency with a modulation efficiency of 2 bps / Hz has been developed and adopted in digital car phone systems and digital MCA (Multi Channel Access) systems.
[0003]
The π / 4 shift QPSK is composed of 4 symbol states with 2 bits of signal as one symbol, that is, combinations of 2 bits of modulated signal (-1, -1), (-1,1), (1, -1) , Is a four-value (4-phase) phase modulation method in which the carrier phase change is changed to ± 45 ° and ± 135 ° corresponding to (1,1), and is a kind of constant envelope modulation method. By using a relatively easy linearity compensation technique in combination, the spread of the power spectrum due to the carrier phase shift can be narrowed, so that there is a feature that interference between adjacent channels can be reduced.
[0004]
On the other hand, as a method for demodulating the above-mentioned π / 4 shift QPSK, a synchronous detection method or a delay detection method is generally used, and theoretically, a carrier wave having a reference phase is recovered from the modulated signal and received. The synchronous detection method of decoding data (modulated signal) by comparing with the wave phase has better characteristics. However, the synchronous detection method makes it difficult to recover the carrier wave in mobile communication in which high-speed fading is likely to occur, and the delay detection method has a phase of a modulated wave delayed by a delay circuit having a predetermined delay time and the next modulated signal. Compared with the wave phase, the relative phase change is detected and the modulated signal data is decoded, so that carrier wave recovery is unnecessary, and therefore, the characteristics are better than those of the synchronous detection method.
[0005]
FIG. 6 is a functional block diagram showing a configuration example of a demodulation circuit using a delay detection method for demodulating a conventional π / 4 shift QPSK. The demodulation circuit shown in this figure includes a quadrature detection unit 101 that detects an in-phase component and a quadrature component of a modulated signal composed of a local signal oscillator 102, a π / 2 phase shifter 103, and multipliers 104 and 105, A delay detector 106 connected to the quadrature detection unit 101 that detects a relative phase change of the modulated signal corresponding to a symbol change of the modulation signal and decodes and outputs the modulation signal, and generates and determines a symbol synchronization signal A symbol synchronization generator 107 connected to the delay detector 106 for outputting a symbol synchronization signal to the converters 108 and 109 and the parallel / serial converter 113, and a sign for determining a sign of a binary signal (-1, +1) of a sine wave Determiners 108 and 109 connected to the delay detector 106 that outputs a wave signal, a complex conjugate unit 110 that forms a complex conjugate of the output signals of the determiners 108 and 109, and an output signal of the delay detector 106 A complex multiplier 111 for multiplying the output signal of the complex conjugate unit 110; A frequency error estimator 112 for estimating a frequency error Δf included in the local signal oscillator 102 from an output signal of the generator 111 and feeding back the estimated result to the local signal oscillator; and parallel outputs of the determiners 108 and 109 A parallel-serial converter 113 that converts a signal into a serial signal is configured.
[0006]
When the demodulated circuit does not include a frequency error in the output of the local signal oscillator 102, when the modulated signal is input to the quadrature detection unit 101, the frequency of the input modulated wave signal and the local signal oscillator are output to the outputs of the multipliers 104 and 105. An in-phase component and a quadrature component of the modulated signal having a frequency corresponding to the difference from the output frequency of 102 are derived. The in-phase component signal and the quadrature component signal are detected by the delay detector 106 as a relative phase difference of the modulated signal corresponding to the symbol change of the modulation signal, and the symbol data of the modulation signal weighted at the time of transmission described above by this phase difference. Is decrypted. FIG. 7 is a signal space layout diagram of the decoded signal at the output of the delay detector 106. As shown in this figure, when the local signal oscillator 102 does not include a frequency error, the signal is designed to be arranged at a position shifted by 45 ° from the I axis and the Q axis. This signal is converted into serial data by the parallel / serial converter 103 after the signs of the I component and Q component signals are determined by the determiners 108 and 109, and the modulated signal is demodulated.
[0007]
However, since the output of the local signal oscillator 102 generally includes a frequency error (Δf), the signal output from the delay detector 106 deviates from the signal space arrangement shown in FIG. FIG. 8 is a signal space layout diagram of signals at the output of the delay detector 106 when the local signal oscillator 102 output includes a frequency error. Since the temporal change of the signal phase is regarded as a frequency change, conversely, when the frequency changes by Δf, the signal phase changes by Δθ. Therefore, when the output of the local signal oscillator 102 deviates from the reference by Δf, the signal shifts the phase angle by Δθ in the signal space arrangement as shown in FIG. This phase shift of Δθ deteriorates the BER (Bit Error Rate, signal error probability) characteristics for the reason described later.
[0008]
The reason why the signal space arrangement when the local signal oscillator 102 shown in FIG. 8 has a frequency error of Δf is degraded compared to the signal space arrangement when there is no frequency error shown in FIG. When signal phase jitter (phase fluctuation) occurs, the decision threshold margin in the sign decision units 108 and 109 is ± 45 ° in FIG. 7, but in FIG. 8, the threshold margin is unidirectional (Q-axis direction). This is because, for example, the probability that the modulation signal (1,1) is erroneously determined as (-1,1) is increased.
[0009]
Therefore, in order to compensate for the phase shift of Δθ in the signal space arrangement shown in FIG. 8, the complex multiplier 111 combines the output signal of the delay detector 106 and the conjugate signal of the code decision unit 108 and 109 output signal by the complex conjugate unit 110. The method of complex multiplication was used. FIG. 9 is a diagram for explaining these complex operation processes in a signal space arrangement. As shown in FIG. 9, for example, assuming that the output signal of the delay detector 106 is in the first quadrant of the signal space arrangement, the complex conjugate 110 input signal (71) has no frequency error in the local signal oscillator. The complex multiplier 111 output obtained as a result of complex multiplication of the signal (72) obtained by conjugating this signal with the output signal (73) of the delay detector 106 shown in FIG. 8 is known. The signal (74) is at a position of Δθ from the I axis.
[0010]
Regardless of which quadrant of the spatial position shown in FIG. 8 the output signal of the delay detector 106 is, the result of the complex operation described above is the position of Δθ from the I axis. Therefore, as shown in FIG. 8, at the output of the delay detector 106, four values are necessary to represent the four Δθ corresponding to the four types of symbols of the modulation signal as absolute values from the I axis. The output of the complex multiplier 111 can be expressed by one Δθ (absolute value). Therefore, the frequency error estimator 112 can uniquely determine the phase shift value Δθ based on the output signal of the complex multiplier 111, and the frequency error Δf can be estimated by time differentiation of the phase shift value.
[0011]
By feeding back this Δf information to the local signal oscillator 102, the output frequency of the local signal oscillator 102 is controlled so as to cancel Δf, thereby preventing the above-described deterioration of the BER characteristics related to the output frequency error of the local signal oscillator 102. can do.
[0012]
As the symbol synchronization generator 107, a zero cross detection method is used. That is, the output signal of the delay detector 106 is taken out to detect a point that crosses the zero level of the sine wave signal (a level located between the positive and negative maximum values of the sine wave signal), and ½ symbol from the zero cross point A position with a period shift is obtained, and this is output as a sample timing signal to operate the determiners 108 and 109 and the parallel-serial converter 113.
[0013]
[Problems to be solved by the invention]
However, the conventional demodulation circuit as described above has the following problems. That is, in order to detect the output frequency error of the local signal oscillator, first, symbol synchronization is established by the symbol synchronization generator 107 in order to determine the sample timing in the code determiners 108 and 109, and then the code is determined by the determiners 108 and 109. It is necessary to detect the frequency error by inputting the output signal to the complex conjugate unit and performing complex operation with the complex multiplier. Therefore, since establishment of symbol synchronization and frequency error detection of the local signal oscillator cannot be performed at the same time, it takes time to acquire synchronization as a demodulation circuit, and as a result, it takes time until the user starts a call. It was.
Further, in order to detect the output frequency error of the local signal oscillator, a complex arithmetic unit such as a complex conjugate or complex multiplier having a complicated circuit configuration is required, which is a problem in miniaturizing the entire demodulation circuit.
The present invention has been made in order to solve the above-described problems related to the conventional demodulation circuit, and is capable of simultaneously establishing symbol synchronization and detecting the output frequency error of the local signal oscillator, and without using a complex arithmetic unit. An object of the present invention is to provide a demodulator circuit capable of reducing the size of the demodulator.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 of the demodulating circuit according to the present invention is a modulated signal that is angle-modulated by a modulating signal that alternately changes between two fixed positions in a signal space arrangement. And detecting an output frequency error included in the local signal oscillator used to separate the in-phase component and the quadrature component with respect to the intermediate value between the maximum value and the minimum value in the time waveform of the detector output signal, and The output frequency error of the local signal oscillator is corrected and controlled using the detected frequency error information.
The invention according to claim 2 of the demodulating circuit according to the present invention is the demodulating circuit according to claim 1, wherein the symbol synchronizing signal is generated based on a time interval in which the time waveform of the detector output signal produces a maximum value and a minimum value. Configure to generate.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on the illustrated embodiment. FIG. 1 is a functional block diagram showing an embodiment of a demodulation circuit according to the present invention. The demodulating circuit shown in this example is a demodulating circuit for demodulating π / 4 shift QPSK, and the in-phase of the modulated signal composed of the local signal oscillator 2, the π / 2 phase shifter 3, and the multipliers 4 and 5. A quadrature detection unit 1 for detecting a component and a quadrature component, and the quadrature detection unit 1 that detects a relative phase change of a modulated signal corresponding to a symbol change of the modulation signal and decodes and outputs the modulation signal. A connected delay detector 6; and determiners 8, 9 connected to the delay detector 6 for determining a sign of a sine wave binary signal (-1, +1) and outputting a rectangular wave signal; The parallel-serial converter 10 that converts the parallel output signals of the determiners 8 and 9 into serial signals and the in-phase or quadrature component output signals of the delay detector 106 (in FIG. 1, the in-phase component output signals are used). A maximum / minimum detector 11 for detecting the maximum value and the minimum value, and based on the output signal of the maximum / minimum detector 11 A frequency error estimator 12 connected to the local signal oscillator 2 for estimating a frequency error Δf included in the local signal oscillator 2 and a symbol synchronization signal based on an output signal of the maximum / minimum detector 11 and generating the determination And a symbol synchronization generator 13 for outputting a symbol synchronization signal to the parallel / serial converter 10.
[0016]
In the demodulation circuit shown in this figure, when there is no frequency error in the output of the local signal oscillator 2, when the modulated signal is input to the quadrature detector 1, the frequency of the input modulated signal and the local signal are output to the outputs of the multipliers 4 and 5. An in-phase component and a quadrature component of the modulated signal having a frequency corresponding to the difference from the output frequency of the oscillator 2 are derived. In this signal, the relative phase difference between the modulated signals corresponding to the symbol change is detected by the delay detector 6, and the symbol data of the modulated signal weighted at the time of transmission described above is decoded by this phase difference. This decoded signal is converted into serial data by the parallel-serial converter 10 after the signs of the I-component and Q-component signals are determined by the determiners 8 and 9, and the modulated signal is demodulated. is there.
[0017]
At this time, when the modulation signal is a preamble signal that repeats transition between two specific positions in the signal space arrangement (a signal of a predetermined pattern arranged at the beginning of each frame of the transmission signal for synchronization) Consider. FIG. 2 is a diagram showing an example of the signal space arrangement of signals at the output of the delay detector 6 when the modulated signal when there is no frequency error in the local signal oscillator 2 is a preamble signal. As shown in this figure, the output signal of the delay detector 6 reciprocates at positions shifted by 45 ° from the I axis and the Q axis, respectively.
[0018]
FIG. 3 is a diagram illustrating the time change of the amplitude change of the signal shown in FIG. 2 with respect to the I axis. Since the transition of the signal position in the signal space arrangement shown in FIG. 2 changes periodically with respect to the passage of time with respect to the origin of the I axis (intersection with the Q axis), it can be represented as a time waveform in FIG. It becomes like this.
[0019]
However, when there is an error of Δf in the output frequency of the local signal oscillator 2, as described above, the signal space arrangement is shifted by Δθ compared to when there is no error (see FIG. 8). FIG. 4 is a signal space layout diagram corresponding to FIG. 2 when the output frequency of the local signal oscillator 2 has an error of Δf. FIG. 5 is a diagram showing the time change of the amplitude change of the signal shown in FIG. 4 with respect to the I axis. The transition of the signal position in the signal space arrangement shown in FIG. 4 changes periodically around the point shifted from the origin of the I axis (intersection with the Q axis) to the negative (left) side over time. Therefore, as shown in FIG. 5, the entire waveform is shifted to the negative side.
[0020]
When the signal shown in FIG. 5 is input, the local maximum / minimum detector 11 differentiates the signal using a differentiator to obtain a local maximum value and a local minimum value of the signal, and an intermediate value between the local maximum value and the local minimum value shown in FIG. ΔI is calculated. This ΔI is generated as a result of the phase shift of Δθ shown in FIG. 4 and is uniquely determined corresponding to Δθ. Therefore, if ΔI can be calculated, Δθ can be obtained, and if ΔΔ is time-differentiated in the frequency error estimator 12, Δf (output frequency error of the local signal oscillator 2) can be obtained. The signal is sent to the oscillator 2 and the local signal oscillator 2 is controlled so as to cancel the output frequency error.
[0021]
Further, the symbol synchronization generator 13 detects the interval time at which the signal level is maximum / minimum from the output signal of the maximum / minimum detector 11, and determines the middle of this detection time as the symbol of the signal input to the delay detector 6. At the same time, this is supplied to the decision units 8, 9 and the parallel-serial converter 10 as a symbol synchronization time.
[0022]
As described above, the demodulation circuit according to the present invention detects the output frequency error of the local signal oscillator 2 from the maximum value and the minimum value of the time waveform of the delay detector 6 output signal regardless of the symbol synchronization generation. It is a thing.
Therefore, the demodulating circuit according to the present invention can simultaneously perform symbol synchronization generation and detection of the output frequency error of the local signal oscillator 2, so that synchronization can be acquired faster than a conventional demodulating circuit and a complex arithmetic unit is required. Therefore, the circuit can be downsized.
[0023]
As described above, the example in which the delay detector output signal transits between the first quadrant and the second quadrant of the signal space layout diagram has been described. However, the delay detector output signal has other quadrants, for example, the second quadrant and the third quadrant. Even in the case of a preamble signal that changes between quadrants, the output frequency error of the local signal oscillator can be detected by the same operation as described above. In this case, it is convenient to express the waveform shown in FIG. 5 by an amplitude change with respect to the Q axis.
[0024]
In the above-mentioned maximum / minimum detector 11, the maximum value or the minimum value of the detected signal may fluctuate due to noise or the like, but at this time, a plurality of maximum values and minimum values are detected at a predetermined time interval, If the average is taken, the detection accuracy can be improved.
[0025]
【The invention's effect】
As described above, the present invention calculates the output frequency error of the local signal oscillator based on the intermediate value between the maximum value and the minimum value of the output signal waveform of the delay detector. Thus, the detection of the output frequency error can be performed at the same time. Therefore, the synchronization acquisition as a demodulation circuit is fast, and a complex arithmetic unit is not required.
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing an embodiment of a demodulation circuit according to the present invention. FIG. 2 is a signal space of a delay detector output when there is no error in the output frequency of a local signal oscillator in the demodulation circuit according to the present invention. Fig. 3 shows an arrangement example. Fig. 3 shows the signal shown in Fig. 2 as time elapses in amplitude change with respect to the I axis. Fig. 4 shows the case where there is an error in the output frequency of the local signal oscillator in the demodulation circuit according to the present invention. FIG. 5 is a diagram showing the signal space arrangement corresponding to FIG. 2 of the delay detector output of FIG. 5. FIG. 5 is a diagram showing the signal shown in FIG. 4 over time with respect to the I axis. Functional block diagram showing a configuration example of the QPSK demodulator circuit. FIG. 7 is a diagram showing a signal space arrangement of the delay detector output when there is no error in the output frequency of the local signal oscillator in the conventional π / 4 shift QPSK demodulator circuit. 8) Conventional π / 4 shift FIG. 9 is a diagram showing the signal space arrangement of the delay detector output when there is an error in the output frequency of the local signal oscillator in the QPSK demodulating circuit. Figure [Explanation of symbols]
1. ・ Quadrature detector
2. Local signal oscillator
3 ・ ・ π / 2 phase shifter
4, 5, ... Multiplier
6. Delay detector
8, 9 ... Sign decision unit
10. ・ Parallel series converter
11. ・ Maximum / minimum detector
12. ・ Frequency error estimator
13. Symbol synchronization generator
101 ・ ・ Quadrature detector
102 ・ ・ Local signal oscillator
103 ・ ・ π / 2 phase shifter
104, 105 ... multiplier
106 ・ ・ Delay detector
107 .. Symbol synchronization generator
108, 109 ... Sign decision unit
110 ・ ・ Complex conjugate
111 ・ ・ Complex multiplier
112 ・ ・ Frequency error estimator
113 ・ ・ Parallel converter

Claims (2)

Output frequency error included in local signal oscillator used to separate in-phase component and quadrature component of modulated signal angle-modulated by modulation signal that alternates between two fixed positions in signal space arrangement Is detected based on an intermediate value between the maximum value and the minimum value in the time waveform of the detector output signal, and the output frequency error of the local signal oscillator is corrected and controlled using the detected frequency error information. A demodulation circuit characterized by that. 2. The demodulator circuit according to claim 1, wherein the demodulator circuit is configured to generate a symbol synchronization signal based on a time interval at which a time waveform of the detector output signal generates a maximum value and a minimum value.

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