JPH11122318A - Afc circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small sized high speed AFC circuit by realizing a frequency error estimate device where the circuit is made small and the processing time is reduced. SOLUTION: In the AFC circuit that has a frequency error estimate device 112 correcting automatically an output frequency error included in a local signal oscillator 102 used to separate a modulated signal into an in-phase component and a quadrature component to demodulate a modulated signal subject to angular modulation, an arc tangent arithmetic processing in the frequency error estimate device 112 is conducted by using a tangent function table stored in a storage means 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an AFC (Automatic Frequency Control) circuit for correcting an output frequency error of a local signal oscillator used in an angle modulation type demodulation circuit.

[0002]

2. Description of the Related Art In a conventional digital mobile communication system, the modulation efficiency is 1 bps / Hz (data transmission speed / occupied bandwidth).
GMSK, 4-level FM, or PLL that is resistant to fading fluctuations due to a constant envelope whose modulated waveform has no modulation information in amplitude
Angle modulation methods such as 4-phase PSK have been adopted. In recent years, a π / 4 shift QPSK scheme having a higher signal transmission efficiency than a modulation efficiency of 2 bps / Hz has been developed and adopted in a digital car telephone system and a digital MCA (Multi Channel Access) system.

[0003] The π / 4 shift QPSK has four symbol states using two bits for a signal as one symbol, that is, a combination (-1, -1), (-1,1), (1,1) of two bits of a modulated signal. This is a four-level (four-phase) phase modulation system in which the carrier phase change is changed to ± 45 ° and ± 135 ° corresponding to (-1) and (1,1), and is a type of constant envelope modulation system. By using a relatively easy linearity compensation technique together, it is possible to narrow the spread of the power spectrum due to the carrier phase shift, so that interference between adjacent channels can be reduced.

On the other hand, as a method for demodulating the above-mentioned π / 4 shift QPSK, a synchronous detection method or a delay detection method is generally used, and theoretically, a carrier having a reference phase is reproduced from a modulated signal. The synchronous detection method of decoding the data (modulated signal) by comparing it with the phase of the received wave has more excellent characteristics. However, the synchronous detection method is not practical in mobile communication in which high-speed fading is likely to occur, and it is difficult to reproduce the carrier wave and the like. On the other hand, the delay detection method compares the phase of a modulated wave delayed in a delay circuit having a predetermined delay time with the next modulated wave phase, detects a relative phase change, and decodes the modulated signal data. Therefore, carrier recovery is unnecessary, and therefore, it has better characteristics than the synchronous detection method in the field of mobile communication.

[0005] FIG. 3 is a functional block diagram showing a configuration example of a conventional demodulation circuit using a delay detection method for demodulating π / 4 shift QPSK. The demodulation circuit shown in FIG. 1 includes a local signal oscillator 102, a π / 2 phase shifter 103, and a quadrature detection unit 101 that detects an in-phase component and a quadrature component of a modulated signal that includes multipliers 104 and 105; A delay detector 106 connected to the quadrature detector 101 for detecting a relative phase change of the modulated signal corresponding to a symbol change of the modulation signal and decoding and outputting the modulation signal, and generating and determining a symbol synchronization signal Container 108,1
09 and a symbol synchronization generator 107 connected to the delay detector 106 which outputs a symbol synchronization signal to a parallel / serial converter 113.
And a determiner 10 connected to the delay detector 106 which determines the sign of the sine wave binary signal (-1, +1) and outputs a rectangular wave signal.
8, 109; a complex conjugate unit 110 for forming a complex conjugate of the output signals of the decision units 108 and 109; and a complex multiplier 111 for multiplying the output signal of the differential detector 106 and the output signal of the complex conjugate unit 110.
A frequency error estimator 112 for estimating a frequency error Δf included in the local signal oscillator 102 from an output signal of the complex multiplier 111, and feeding back the estimated result to the local signal oscillator 102; It comprises a parallel-serial converter 113 for converting the parallel output signals 108 and 109 into a serial signal. Here, an AFC circuit 114 is formed by the complex conjugate unit 110, the complex multiplier 111, and the frequency error estimator 112.

[0006] This demodulation circuit, when the output of the local signal oscillator 102 does not include a frequency error, when the modulated signal is input to the quadrature detector 101, the output of the multipliers 104 and 105 and the frequency of the input modulated wave signal An in-phase component and a quadrature component of a modulated signal having a frequency corresponding to a difference from the output frequency of the local signal oscillator 102 are derived. The in-phase component signal and the quadrature component signal are detected by the delay detector 106 as a relative phase difference of the modulated signal corresponding to the symbol change of the modulation signal, and the symbol data of the modulation signal weighted at the time of transmission described above by this phase difference Is decoded. Figure 4 shows the delay detector 1
FIG. 14 is a signal space arrangement diagram of the decoded signal at the output of 06. As shown in this figure, the local signal oscillator 102
If no frequency error is included in the signal, the signal is designed to be arranged at positions shifted by 45 ° from the I axis and the Q axis, respectively. This signal is converted to serial data by the parallel / serial converter 103 after the signs of the I component and Q component signals are determined by the determiners 108 and 109, and the modulated signal is demodulated.

However, since the output of the local signal oscillator 102 generally includes a frequency error (Δf), the delay detector 106
Are shifted from the signal space arrangement shown in FIG. FIG. 5 is a signal space layout diagram of a signal at the output of the differential detector 106 when a frequency error is included in the output of the local signal oscillator 102. Since a temporal change in the signal phase is regarded as a frequency change, conversely, when the frequency changes by Δf, the signal phase changes by Δθ. Therefore, when the output of the local signal oscillator 102 deviates from the reference by Δf, the phase angle of the signal shifts by Δθ in the signal space arrangement as shown in FIG. This phase shift of Δθ is
The BER (Bit Error Rate, signal error probability) characteristic is degraded for the reasons described below.

[0008] As shown in FIG.
The reason why the BER characteristic deteriorates in the signal space arrangement with the frequency error of f compared to the signal space arrangement without the frequency error shown in Fig. 4 is that phase jitter (phase fluctuation) of the signal occurs due to noise etc. Then, the decision threshold margins in the sign decision units 108 and 109 are ± 45 ° in FIG.
In FIG. 5, the threshold margin is 45 in one direction (Q-axis direction).
This is because the probability that the modulated signal of (1,1) is erroneously determined as (-1,1) is increased, for example.

[0009] Therefore, Δ in the signal space arrangement shown in FIG.
In order to compensate for the phase shift of θ, a method is used in which a complex multiplier 111 multiplies the output signal of the differential detector 106 and the conjugate signal of the sign determination units 108 and 109 by the complex conjugate unit 110 by a complex multiplier 111. FIG. 6 is a diagram illustrating these complex arithmetic processes in a signal space arrangement. As shown in FIG. 6, for example, if the output signal of the delay detector 106 is in the first quadrant of the signal space arrangement, the complex conjugate device 110 input signal (71)
Is known to be in a position where there is no frequency error in the local signal oscillator, and the signal (72) obtained by taking the conjugate of this signal and the output signal (73) of the delay detector 106 shown in FIG. Complex multiplier 111 output signal obtained as a result of complex multiplication (74)
Is a position of Δθ from the I axis.

[0010] Regardless of the quadrant of the spatial position shown in FIG.
The position is Δθ from the I axis. Therefore, as shown in FIG. 5, at the output of the delay detector 106, four values were necessary to represent four Δθs corresponding to the four types of symbols of the modulated signal by absolute values from the I axis. The output of the complex multiplier 111 can be represented by one Δθ (absolute value).
Therefore, based on the output signal of the complex multiplier 111, the frequency error estimator 112 uses the frequency shift value Δf as described later.
Can be determined uniquely. By feeding back the information of this Δf to the local signal oscillator 102,
By controlling so as to cancel the output frequency error Δf of the local signal oscillator 102, it is possible to prevent the BER characteristic from deteriorating due to the output frequency error of the local signal oscillator 102 described above.

FIG. 7 is a functional block diagram showing a configuration example of the frequency error estimator 112. The frequency error estimator 11 shown in FIG.
2 is a divider 115 for dividing the Q component value of the output signal of the complex multiplier 111 by the I component value, and an arc tangent calculator 11 for calculating an arc tangent of the output signal of the divider 115.
6 and a frequency error calculator 117 for calculating a frequency error Δf from the output signal of the arc tangent calculator 116. When the output signal 74 of the complex multiplier 111 shown in FIG. 6 is input, the frequency error estimator 112 shown in this diagram performs Q / I calculation (division) and calculates the Q / I arc tangent to obtain a Δ
θ, and from the value of Δθ, the frequency error Δf
Is calculated. Δf = Δθ · fs / 2π (1) where fs is the symbol frequency of the signal. Since the frequency error estimator 112 operates as described above, it is possible to obtain Δf in a short time regardless of the value of Δθ.

FIG. 8 is a functional block diagram showing another example of the configuration of the frequency error estimator 112. FIG. 9 is a signal space layout diagram for explaining the operation of threshold decision unit 118 included in frequency error estimator 112 shown in FIG. The frequency error estimator shown in FIG. 8 is simply a threshold
The operation of the frequency error estimator will be described below with reference to FIG. Complex multiplier 111
When the output signal is input to the frequency error estimator, as shown in FIG. 9, the threshold decision unit 118 provides desired positive and negative threshold values for the Q value, and the input signal determines these threshold values. If it exceeds, it is determined that there is a uniform phase shift Δθ, and the output frequency of the local signal oscillator is controlled so as to correct Δf corresponding to Δθ.
This operation is repeated until the θ value becomes equal to or smaller than the threshold value. Since the frequency error estimator does not require an operation such as an arc tangent as compared with the frequency error estimator shown in FIG. 7, the circuit can be downsized.

[0013]

However, the frequency error estimator constituting the above-mentioned conventional AFC circuit has the following problems. That is, FIG.
Since the frequency error estimator shown in (1) performs an arctangent operation that requires the calculation of an infinite series (Maclaurin series), the circuit configuration for realizing this operation is complicated, and the frequency error estimator cannot be downsized. When the Δθ value is large, the frequency error estimator shown in FIG. 8 cannot fully correct Δf corresponding to Δθ in one operation according to the above-described operation principle, and repeats several correction control operations. Processing time is long. Therefore, in the conventional frequency error estimator, it has been difficult to realize the miniaturization of the circuit and the shortening of the processing time. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems related to the frequency error estimator in the conventional AFC circuit, and has realized a frequency error estimator capable of reducing the size of the circuit and increasing the processing time. It aims to provide a small, high-speed AFC circuit.

[0014]

In order to achieve the above object, the invention according to claim 1 of the AFC circuit according to the present invention provides an AFC circuit that modulates the modulated signal in phase to demodulate the angle-modulated signal. In the AFC circuit having a frequency error estimator for automatically correcting the output frequency error included in the local signal oscillator used to separate the component I and the quadrature component Q, the frequency error estimator, Q / I Storage means for storing a tangent function table showing the relationship between the tangent function value and the arc tangent value; a divider for dividing the Q component by the I component; and a phase for estimating a phase error based on the output of the divider and the tangent function table. It comprises an error estimating means and a frequency error calculator for obtaining a frequency error based on the estimated phase error.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 shows A according to the present invention.
FIG. 3 is a functional block diagram illustrating an embodiment of a frequency error estimator included in the FC circuit. The frequency error estimator shown in this example includes a divider 115 that divides the Q component value of the output signal of the complex multiplier 111 by the I component value, a storage unit 10 that stores a tangent function table, and an output of the divider 115. From the signal and the tangent function table stored in the storage means 10, Q / I
And a frequency error calculator 117 for calculating a frequency error Δf from an output signal of the discrete phase error estimated value 11. Here, the divider 115 and the frequency error calculator 112 are the same as the conventional one. FIG. 2 is a diagram showing a numerical example of a tangent function table stored in the storage means 10.

[0016] The frequency error estimator according to the present invention, when the output signal 74 of the complex multiplier 111 shown in FIG.
At 115, a Q / I operation (division) is performed, and the result is tan (Δ
θ) is output to the discrete phase error estimator 11. The discrete phase error estimator 11 obtains a corresponding upper value from the lower value of the tangent function table shown in FIG. 2 to calculate Δθ from the tan (Δθ) value, calculates Δθ, and calculates this as a frequency error calculator. Output to 117. The frequency error calculator 117 is described above.
Using the equation (1), the output frequency error Δf of the local signal oscillator
Is calculated.

Since the frequency error estimator according to the present invention operates as described above, the arc tangent operation is not required, so that the arc tangent operation circuit is not required, and the circuit can be downsized. Further, since Δf can be corrected by one operation, the processing speed is high.

[0018]

As described above, according to the present invention, since the tangent function table is stored in the storage means in the frequency error estimator, the arc tangent operation circuit becomes unnecessary and the local signal oscillator can be operated by one operation. Since the output frequency error (Δf) can be corrected, it is very effective in realizing an AFC circuit capable of high-speed processing with a reduced circuit size.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a frequency error estimator constituting an AFC circuit according to the present invention.

FIG. 2 is a diagram illustrating a numerical example of a tangent function table stored in a storage unit of a frequency error estimator included in an AFC circuit according to the present invention.

FIG. 3 is a functional block diagram illustrating a configuration example of a conventional π / 4 shift QPSK demodulation circuit.

FIG. 4 is a diagram showing a signal space arrangement of a differential detector output when there is no error in an output frequency of a local signal oscillator in a conventional π / 4 shift QPSK demodulation circuit.

FIG. 5 is a diagram illustrating a signal space arrangement of a differential detector output in a case where there is an error in an output frequency of a local signal oscillator in a conventional π / 4 shift QPSK demodulation circuit.

FIG. 6 is a diagram illustrating a complex operation process in a conventional π / 4 shift QPSK demodulation circuit in a signal space arrangement.

FIG. 7 is a functional block diagram showing a first configuration example of a conventional frequency error estimator.

FIG. 8 is a functional block diagram illustrating a second configuration example of a conventional frequency error estimator.

9 is a signal space layout diagram for explaining the operation of the frequency error estimator of FIG.

[Explanation of symbols]

 10, storage means 11, discrete phase error estimator 101, quadrature detector 102, local signal oscillator 103, π / 2 phase shifter 104, 105, multiplier 106, delay detector 107, Symbol synchronization generator 108, 109Sign decision unit 110Complex conjugate unit 111Complex multiplier 112Frequency error estimator 113Parallel-serial converter 114 AFC circuit 115 Divider 116・ Arc tangent calculator 117 ・ ・ Frequency error calculator 118 ・ ・ Threshold detector

Claims (1)

[Claims] 1. An automatic correction of an output frequency error included in a local signal oscillator used to separate an in-phase component I and a quadrature component Q for demodulating an angle-modulated signal. An AFC circuit having a frequency error estimator for storing the frequency error estimator in a storage means storing a tangent function table indicating the relationship between Q / I and its arc tangent value, and dividing the Q component by the I component. , A phase error estimating means for estimating a phase error based on the output of the divider and a tangent function table, and a frequency error calculator for obtaining a frequency error based on the estimated phase error. AFC circuit.