JP3518429B2 - Digital PLL device and symbol synchronizer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase locked loop (hereinafter referred to as digital PLL) device and a symbol using the digital PLL device when demodulating a digitally modulated signal. The present invention relates to a symbol synchronizer for synchronizing. This symbol synchronization device is particularly suitable for application to a frequency hopping receiver for a wireless LAN system.

[0002]

2. Description of the Related Art Spread spectrum (SS)
m) A frequency hopping system (FH system) as one communication system
There is. In addition, with this FH system, direct diffusion (Direct
Sequence, hereinafter referred to as a DS system) is also a DS / FH hybrid system. FIG.
FIG. 4 is a block diagram showing an example of a conventional FH system. In the figure, 71 is an encoder, 72 is a digital modulator, and 7
3 is a mixer, 74 is a hopping pattern generator, 75 is a frequency synthesizer, 76 is a high frequency amplifier, 77 is a transmitting antenna, 78 is a receiving antenna, 79 is a high frequency amplifier, 8
0 is a mixer, 81 is a hopping pattern generator, 82 is a frequency synthesizer, 83 is a digital demodulator, and 84 is a decoder.

On the transmitting side, the transmission information is the encoder 71.
Source coding is performed in and converted into transmission data. At that time, encoding suitable for transmission may be performed if necessary. The transmission data is digitally modulated in the intermediate frequency band by the digital modulator 72, and then frequency-converted by the output signal of the frequency synthesizer 75 in the mixer 73. In accordance with the hopping pattern output from the hopping pattern generator 74, the frequency synthesizer 75 temporally changes the frequency to be frequency-converted to switch the transmission frequency channel. Therefore, the digitally modulated signal is transmitted on the frequency channel corresponding to the hopping pattern. As a result, a spread spectrum signal having a wide frequency band is spread, amplified by the high frequency amplifier 76, and transmitted from the transmission antenna 77.

On the receiving side, the spread spectrum signal is
The signal is received by the receiving antenna 78, amplified by the high frequency amplifier 79, input to the mixer 80, and despread.
The hopping pattern generator 81 generates the same hopping pattern in synchronization with the hopping pattern generator 74 on the transmission side, and the frequency synthesizer 82 outputs the reference oscillation signal of the same frequency as that output by the frequency synthesizer 75 on the transmission side. To do. Then, by selectively receiving a signal on the same frequency channel as the transmitted signal, the transmitted spread spectrum signal is despread to a signal in the intermediate frequency band. The despread signal is input to the digital demodulator 83 through a signal component of the reception frequency band of each frequency channel in the intermediate frequency band by a band pass filter (not shown). In the digital demodulator 83, demodulated data is obtained by performing digital demodulation corresponding to the digital modulator 72 on the transmission side. In the decoder 84, the demodulated data is subjected to information source decoding corresponding to the encoder on the transmission side, and reception information is output. In that case, decoding for transmission may be performed corresponding to the encoder on the transmission side.

Currently, the most popular digital modulation method is Quadrature Phase Shift Keying,
Hereinafter, phase modulation (Phase Shift Ke) such as QPSK
ying, hereinafter referred to as PSK), quadrature amplitude modulation (Quadratu
re Amplitude Modulation (hereinafter referred to as QAM)). In mobile communication, the QPSK demodulation method is mainly differential detection. However, since the synchronous detection has a good error rate characteristic, the synchronous detection is mainly used for fixed communication. Therefore, in consideration of the optimum design, it is desired to use differential detection and synchronous detection together so that they can be switched according to the communication path environment, and to secure high communication quality in data communication. However, in synchronous detection, normally, carrier reproduction is performed to establish carrier synchronization, and then symbol synchronization (bit synchronization) is performed. In the FH system, however, carrier synchronization and symbol synchronization (bit synchronization) are performed each time the frequency channel is switched. ) Is established, frame synchronization is established, and data is received. Therefore, the following problems specific to the FH system occur.

FIG. 14 is an explanatory diagram showing changes in carrier frequency in the FH system. FIG. 15 is an explanatory diagram of a start portion of a transmission frame transmitted in the frequency hopping period in the FH system. In FIG. 14, the carrier of the digitally modulated signal is continuously changed from the frequency f ₁ to the current frequency f ₂ by frequency conversion (spreading) on the transmission side, and after a certain amount of time, the target It falls within the vicinity of the frequency f ₂ . However, since a PLL is generally used for frequency conversion, the frequency f
Even when the frequency becomes close to ₂ , the carrier frequency converges while vibrating near the target frequency f ₂ . Further, since the PLL is also used for frequency conversion on the receiving side, the carrier of the signal converted to the intermediate frequency band by frequency conversion (despreading) similarly converges while vibrating near the intermediate frequency. It will be. This period of vibration is called the settling period. Reception of a transmission frame is started during this settling period. As an example, the frame format first starts from the symbol synchronization preamble shown in FIG. 15, and is followed by a frame synchronization signal and information data. In synchronous detection, the carrier synchronization circuit performs a phase lock operation during the symbol synchronization preamble period to create a carrier copy.

In the conventional Costas loop as the carrier synchronizing circuit, the demodulated baseband signals I and Q are calculated based on the symbol synchronizing preamble, and the phase error with respect to the carrier is output from the digitally modulated signal. To do. This phase error is smoothed by a loop filter, and the oscillation frequency of the reference frequency oscillator is controlled so as to follow the carrier frequency.

However, since the response of the loop filter is slow, it takes time to complete the carrier synchronization, so that it is necessary to lengthen the symbol synchronization preamble. Furthermore, it is necessary to perform a symbol synchronization operation for outputting a clock signal from the time when this carrier synchronization is completed. As a result, if the time of one frame is short, the preamble length occupies most of the frame length, the ratio of the time for transmitting data becomes small, and there is a problem that the throughput deteriorates. In order to improve the throughput, it is necessary to shorten the symbol synchronization preamble. Therefore, it is desired to enable symbol synchronization without performing carrier synchronization (carrier phase tracking). Therefore, for this symbol synchronization, a digital PLL device capable of simple and stable synchronization acquisition is required. Such a digital PLL device is also useful as a digital PLL device that synchronizes with a general synchronization signal.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is a digital PLL device that enables simple and stable synchronization, and a symbol using this digital PLL device. It is an object of the present invention to provide a synchronization device.

[0010]

The present invention is a digital PLL device for outputting a clock signal synchronized with the cycle of an input signal, the correlation output means, the periodic signal generating means, the phase error determining means, and the error correction. Means, the correlation output means outputs a correlation signal by taking a correlation between the input signal and the reference phase data, the periodic signal generating means,
A periodic signal capable of periodic control is generated, and the periodic signal or a signal based on the periodic signal is output as the clock signal, and the phase error determination means determines the level of the correlation signal at a predetermined phase timing of the periodic signal. Is detected to determine the phase error between the input signal and the periodic signal, and the error correction means controls the period of the periodic signal according to the phase error. Therefore, since the integration operation of the correlation output means is less susceptible to the influence of the disturbance of the input signal, the operation of the digital phase locked loop device is stabilized.

According to the present invention, the correlation output means further comprises:
A signal obtained by binarizing the input signal is sequentially input to the shift means, and it is determined whether or not each tap output of the shift means and the binarized reference phase data string match, and the added value of the determination output is calculated. It is to output sequentially. Therefore, the correlation value can be output with a simple configuration.

In the present invention, the phase error determining means may detect the phase of the correlation signal by detecting the level of the correlation signal at the predetermined phase timing of the periodic signal and timings before and after the predetermined phase timing. It is for determining an error, and has a synchronization determination means, wherein the synchronization determination means determines that the phase error at the predetermined phase timing is small over one or more cycles of the synchronization signal, and thereafter, When it is determined that at least one of the phase errors in the predetermined phase timing and the preceding and following phase timings is small over one or more cycles of the synchronization signal, the clock signal is started to be output to the outside. Therefore, it is possible to perform the synchronization determination that is not easily affected by the phase jitter.

According to the present invention, a symbol synchronizing signal of a digitally modulated signal receives a synchronizing signal whose phase rotation direction with respect to a carrier is inverted for each symbol, and generates a clock signal synchronizing with the symbol of the digitally modulated signal. A symbol synchronization device having a carrier synchronization means, a phase angle output means, and a digital PLL device, wherein the carrier synchronization means outputs a reference frequency signal that follows the frequency of the carrier based on the synchronization signal. Then, the phase angle output means outputs a phase angle signal representing an IQ plane phase angle of the digitally modulated signal with respect to the reference frequency signal, and the digital PLL device has a digital PLL device having various forms described above. Is. Therefore, since the integration operation of the phase detecting means is less susceptible to the disturbance of the input signal, the operation of the symbol synchronizer becomes stable.

[0014]

1 is a block diagram of a digital demodulator for explaining an embodiment of a symbol synchronization apparatus of the present invention. In the figure, 1 is a reference frequency oscillator, 2
Is a 90 ° phase shifter, 3 and 4 are demodulation multipliers, 5 and 6 are low-pass filters, 7 is an A / D converter, 8 is an IQ phase angle calculation unit, 9 is a symbol synchronization unit, 10 is a differential output unit, 11 is 1
Sampling clock delay unit, 12 is a subtractor, 13 is 2
A digitization unit, 14 is a digital PLL (DPLL) unit, and 15 is a phase angle determination unit. Although description will be made on the premise of QPSK demodulation, the same applies to carrier synchronization and symbol synchronization when QAM demodulation is performed. FIG. 2 is an operation explanatory diagram of the block configuration of FIG. 1 at the time of receiving the symbol synchronization preamble. Numerical data is expressed as a waveform. FIG. 16 is an explanatory diagram showing an example of the symbol synchronization preamble. As an example, four-phase phase modulation (QPS
The case of K) is shown on the IQ phase plane coordinates. The symbol synchronization preamble is defined as a repetitive signal by the radio equipment technical standard. In QPSK, IQ
It is assigned to two states of + 90 ° rotation and −90 ° rotation in the phase plane.

In FIG. 1, the received signal frequency-converted into the intermediate frequency band is balanced and demodulated by the demodulation multipliers 3 and 4 by the reference frequency signal output from the reference frequency oscillator 1 and passed through the low pass filters 5 and 6 to the base band. The signals become I and Q. The A / D converter 7 converts each baseband signal I, Q into numerical data at the timing of the sampling signal. The sampling signal is set to be generated a plurality of times, for example, 16 times per unit period of 1 symbol (1 bit when viewed as the baseband signals I and Q). In the IQ phase angle calculation unit 8, A /
Numerical data output from the D converter 7 is input to discriminate the phase angle of the digitally modulated signal with respect to the reference frequency signal. Specifically, it is performed by referring to a trigonometric function operation or a lookup table.

The symbol synchronization unit 9 receives this phase angle, detects a symbol synchronization preamble signal in which the symbol phase rotation direction with respect to the carrier is inverted at the symbol signal point, and a symbol synchronization pulse synchronized with this symbol synchronization preamble signal. (Clock signal) is generated and output to the phase angle determination unit 15 . The phase angle determination unit 15 outputs demodulated data by determining the phase angle output from the IQ phase angle calculation unit 8 with the symbol synchronization pulse as the determination timing. In the symbol synchronization unit 9, the output of the differential output unit 10 including the 1-sampling clock delay unit 11 and the subtractor 12 becomes a phase angle differential signal, which is binarized in the binarization unit 13 and is output to the digital PLL unit 14. Is entered. Digital PLL unit 14
Outputs a symbol synchronization pulse (clock signal) in synchronization with the binarized phase angle differential signal.

The operation of the symbol synchronization section shown in FIG. 1 will be described in detail with reference to FIG. FIG. 2A shows the phase angle signal output from the IQ phase angle calculation unit 8 as the waveform amplitude when receiving the symbol synchronization preamble. Actually, the sampling value as shown in FIG. 2D is output as digitized data. Note that, in order to make the drawings easy to see, in this specification, 8 sampling clocks are generated per symbol, but in the prototype, it is set to 16 sampling clocks per symbol. In the phase angle signal, a portion having a positive slope and a portion having a negative slope repeatedly appear for each symbol. The positive and negative peak points are
The symbol signal point, that is, the center point of the symbol section. Each of the baseband signals I and Q is the center point of the bit section. That is, if the baseband signals I and Q are sampled at the timing of this peak, symbol (bit) synchronization can be achieved, so that demodulated data can be determined corresponding to the symbol signal points.

However, there is a static frequency offset (frequency offset) between the transmitting side and the receiving side due to the frequency error of the reference frequency oscillator when symbol synchronization is performed or when demodulated data is determined. As shown in FIG. 2A, the phase angle of the carrier shifts in one direction as a whole due to the frequency offset. In addition, in communication between the base station and the mobile, the reception frequency shifts due to the Doppler effect. Further, there is a problem that the frequency fluctuates during the frequency hopping settling period. In the differential output unit 10, I
The phase angle data output from the Q phase angle calculation unit 8 is input to the 1 sampling clock delay unit 11 and the 1 sampling clock delay unit 11
The phase angle data output from is subtracted. As a result, a signal obtained by subtracting (differentiating) the phase angle is output.

FIG. 2 (b) shows the phase angle differential signal output from the differential output section 10 as the waveform amplitude during reception of the symbol synchronization preamble. In fact, Figure 2
The sampling value as shown in (e) is output as digitized data. By taking the difference, the phase drift due to the frequency offset is eliminated. The slope of the frequency offset becomes a DC offset, but the DC offset can be easily removed. Not only the frequency offset but also the gradual fluctuation of the frequency can be removed. Figure 2
Since the level change timing of the binarized phase angle differential signal shown in (c) corresponds to the switching point of the slope of the phase angle,
As a result, the symbol signal point can be detected. The interval between level change timings is the period of the transmitted symbols and is not affected by frequency fluctuations.

In the digital PLL unit 14, the binary phase angle differential signal is phase-compared with the internally generated periodic signal, and the period of the periodic signal is corrected according to the phase error. The phase is locked to the phase of the binarized phase angle differential signal. When locked continuously,
The clock signal is output to the phase angle determination unit 15. In the phase angle determination unit 15, the phase angle output from the IQ phase angle calculation unit 8 is set at a predetermined timing of the clock signal, that is,
The data determined by the symbol signal point timing and digitally demodulated is output.

FIG. 3 is an explanatory view showing the movement of the phase plane coordinate axes with reference to the carrier of the digitally modulated signal. In order to perform digital demodulation, not only symbol synchronization but also carrier synchronization must be established in principle. If carrier synchronization (carrier phase tracking) is not performed, the phase plane coordinate axis based on the carrier rotates on the phase plane coordinate based on the reference frequency signal. The phase plane coordinate axis of the reference frequency signal is [I ₀ , Q ₀ ]. Initially, even if the phase of the reference frequency signal exactly matches the phase of the carrier, the phase plane coordinate axis of the carrier is, for example, [I
₁ , Q ₁ ] (offset phase angle Δ ₁ ), [I ₂ , Q ₂ ] (offset phase angle Δ ₂ ), ...

Since the symbol signal points of the digitally modulated signal are defined on the phase plane coordinates of the carrier,
Rotate together. For example, the symbol signal points of the symbol synchronization preamble signal indicated by black circles move in time when viewed on the phase plane coordinates of the reference frequency signal.
Since the baseband signals I and Q are I and Q components on the phase plane coordinates [I ₀ , Q ₀ ] based on the reference frequency signal,
If only this can be sampled at the time of the symbol (bit) center, I, Q on the phase plane coordinates [I ₁ , Q ₁ ], [I ₂ , Q ₂ ] ... Of the carrier of the digitally modulated signal. I can't get the ingredients. However, the phase angle determination unit 15 has a margin of ± 45 ° in the determination. Therefore, the error does not substantially occur unless the offset phase angle is rotated beyond the range of ± 45 °. As a result, a determination error does not occur unless the phase shift exceeds the allowable range during one synchronization frame period. The differential signal of FIG. 2C is stable in this range, and the symbol synchronization point can be established.

It is also possible to demodulate by following the carrier phase change. The present applicant has filed Japanese Patent Application No. 10-288
Japanese Patent Application No. 316 and Japanese Patent Application No. 10-288317 have applied for an invention relating to a carrier phase tracking device. In summary, the phase angle of the demodulated signal output from the IQ phase angle calculator 8 is corrected according to the known offset phase angle Δ ₁ at the above-described clock signal determination timing, and then the data determination is performed. At the same time, the offset phase angle Δ ₁ is updated according to the offset phase angle shift amount (Δ ₂ −Δ ₁ ). At that time, the IQ phase angle calculation unit 8 determines that the phase angle is 3
When changing over a range of 60 ° (multiple rotations), the change of the phase angle is continuously tracked over a range of 360 °. As a result, even if carrier synchronization is not performed prior to symbol synchronization, if symbol synchronization is achieved, digital demodulation can be performed even if the phase angle rotates beyond the range of ± 45 °.

Returning to FIG. 1 again, the symbol synchronization section 9 will be described. By the above-described differentiation operation, it is possible to obtain the clock signal in which the phase fluctuation due to the frequency offset or the like is canceled. However, since the differential operation is included in the extraction of the symbol change points, the disturbance of the phase angle due to noise, multipath fading, delay spread, etc.
Since it reacts sensitively, there is a risk of unstable operation. This problem will be described first in the case where the digital PLL unit 14 preprocesses the binarized phase angle differential output using a histogram circuit.

FIG. 4 is a block diagram of the histogram circuit. In the figure, 21-1 to 21-16 are shift registers, 22-
1 to 22-16 are adders, 23 is a shift register group shift controller, and 24 is a histogram data selector. Figure 5
FIG. 5 is an explanatory diagram of a sampling signal input to the histogram circuit shown in FIG. The symbol synchronization preamble signal is a differential output unit 10 and a binarization unit 13 shown in FIG.
And becomes a binarized phase angle differential signal.

If the binary phase angle fine signal is represented by a waveform,
One cycle has a length of 2 symbols. If the difference between these binary phase angle differential signals is taken, the symbol change point (symbol signal point)
Is obtained. This change point signal is input to the shift register groups 21-1 to 21-16. The sampling clocks are set to have a predetermined number of cycles per 1 symbol length, but are shown as 16 per 1 symbol length. The sampling clocks within this one symbol length will be described with circled numbers (1) to (16) according to their sampling points.

In FIG. 4, the symbol change point signals are distributed to the shift registers 21-1 to 21-16 of the numbers corresponding to the sampling points, and then,
Is entered. In addition, the shift register group shift control unit 23
By this, the shift registers 21-1 to 21-16 are shifted once per one symbol length. In the shift register group, the symbol change point signal has a plurality of periods, 16 symbols in the illustrated example.
Accumulated over a cycle. Each shift register 21-1 ~ 21
-16, the outputs of the taps are added by the adders 22-1 to 22-16 and output to the histogram data selector 24. The histogram data selector 24 obtains a histogram of symbol change points for each sampling point over a plurality of cycles (a plurality of symbols),
Select the statistically most probable symbol change point. The selected symbol change point is used to control the phase of the internal oscillator.

FIG. 6 is a schematic explanatory view for explaining a histogram of symbol change points. Sample points
The appearance frequency of the symbol change point is shown for each of (1) to (16). In the illustrated example, it is estimated that the symbol change point of the symbol synchronization preamble is at the sampling point (1). However, due to the above-mentioned disturbance, false symbol change points will appear in the histogram, and if the sampling point with the highest appearance frequency is simply estimated as the symbol change point, the symbol synchronization becomes inaccurate or, in some cases, synchronization detection is performed. There is also the danger of becoming impossible.

FIG. 7 shows the digital PLL unit 1 shown in FIG.
4 is a block diagram showing a first example of No. 4 of FIG. 31 in the figure
Is a correlation output unit, 32 is a latch, 33 is a VSCO (Variab
le Step controlled Oscillator), 34 is an error correction unit, and 35 is a synchronization determination unit. The VSCO 33 is a digital oscillator capable of stepwise controlling the phase of the oscillation cycle according to input information. FIG. 8 is a block configuration diagram showing an example of the correlation output unit shown in FIG. 7. In the figure, 41 is a shift register, 42 is an exclusive OR (EXOR), and 43 is an adder. This digital PLL unit includes a correlation output unit 3
Since 1 is an integral element, simple and stable symbol synchronization is possible even when a differential output is input.

The binarized phase angle differential signal is sequentially input to the correlation output unit 31. As described later, the correlation between the binarized phase angle differential signal and the set reference phase bit string (reference phase signal) is detected, and the correlation signal is output. VSCO
33 generates at least one periodic signal capable of stepwise controlling the start phase of one period. The above-mentioned correlation signal is latched in the latch 32 at the rising timing of this periodic signal. At the same time, in order to obtain the symbol signal point timing for the phase angle determination, a signal phase-synchronized with this periodic signal is generated and output as a clock signal. The periodic signal itself may be the clock signal. The output of the latch 32 is input to the error correction unit 34, and the error correction unit 34 outputs to the VSCO 33 a period control signal corresponding to the phase error between the symbol synchronization preamble and the period signal of the VSCO 33, and the next signal of the period signal is output. The start phase of the cycle (for example, the rising timing) is controlled. At the same time, the error correction unit 34 outputs the error state to the synchronization determination unit 35. The synchronization determination unit 35 determines the establishment of synchronization according to the error state, and starts output of a signal output from the VSCO 33 and phase-synchronized with the above-described periodic signal as a clock signal.

The correlation output unit will be described with reference to FIG. Two
The binarized phase angle differential signal is sequentially input to the shift register 41 by a predetermined number of sampling clocks per symbol length, that is, eight sampling clocks in the illustrated example. In the illustrated example, the shift register 41 is set to the number of taps for accumulating binary data for one cycle and two symbol lengths. Shift register 4
The tap outputs of 1 are respectively judged by the exclusive OR 42 to be correlated or non-coincident with the bit string indicating the reference phase, and the adder 43 adds the matched numbers.
The adder 43 outputs a correlation signal indicating the phase relationship between the binarized phase angle differential signal and the reference phase.

FIG. 9 is an operation explanatory diagram of the correlation output unit shown in FIG. FIG. 10 is an operation explanatory diagram showing a correlation signal output from the correlation output unit shown in FIG. FIG. 9A shows
The reference phase data {1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0} is expressed along the taps of the shift register in FIG. It is a thing. FIGS. 9B to 9F show the binarized phase angle differential signal along the taps of the shift register in FIG. Figure 9 (b) ~ Figure 9 (e), respectively, representing the state at time t = t ₀ ~t _4. 9 (f) shows that at the same time t = t _{1 as} in FIG. 9 (c),
It represents a state of disturbance.

In the case of FIG. 9B, since the outputs of the exclusive OR 42 shown in FIG. 8 are all 0, the correlation signal output from the adder 43 is also 0. In the case of FIG. 9C, 1
Since the half of the six exclusive ORs 42 becomes 1, the output of the adder 43 becomes 8. In the case of FIG. 9D, all the exclusive ORs 42 are 1, so the output of the adder 43 is 1
It becomes 6. In the case of FIG. 9E, the output of the adder 43 becomes 8 again. As shown in FIG. 10, the correlation signal outputs a triangular correlation signal in accordance with the phase with the reference phase signal as a reference in a period of one cycle and two symbols. Time t
In = t _1, the correlation values, taking the median 8 of the maximum value 16 and minimum value 0. This median value is a value corresponding to 1/2 of the number of taps of the shift register 41. At this time, the binarized phase angle differential signal is at the boundary of the 1-symbol section after 1/4 cycle (1/2 symbol length) has elapsed from the falling edge. The shift register 41 shown in FIG. 8 is in the state shown in FIG. 9C. Therefore, if the phase of the first periodic signal output by the VSCO 33 is locked at the time when the correlation value is the median value 8, the symbol input by the VSCO 33 as the binarized phase angle differential signal It can be synchronized with the period of the synchronization preamble. It should be noted that even at time t = t _3, the same correlation value as at time t = t ₁ is output. However, when t = t ₁ and t
= T ₃ means the shape of the correlation value output, and / or
There is no problem because it can be easily discriminated from the register value distribution of the shift register 41. For example, by monitoring the time derivative of the correlation value, it can be seen that the time t = t ₁ is in the positive period and the time t = t ₃ is in the negative period.

The correlation signal output from the correlation output unit 31 is latched at the rising timing of the periodic signal output from the VSCO 33. When the cycle of the periodic signal generated by the VSCO 33 becomes longer than the cycle of the binarized phase angle differential signal, the level of the latched correlation signal becomes higher than the above-mentioned predetermined value (median value 8). At this time, the error correction unit 3
4 controls to shorten the next period of the periodic signal output from the VSCO 33. Conversely, if the cycle of the periodic signal becomes shorter than the cycle of the binarized phase angle differential signal, the level of the latched correlation signal becomes smaller than the above-mentioned predetermined value (median value 8). At this time, the error correction unit 34 determines that the VSCO 3
Control is performed so as to lengthen the next cycle of the cyclic signal output by No. 3. In this way, the period of the periodic signal is feedback-controlled, and the output phase of the periodic signal is also synchronized with the phase of the binarized phase angle differential signal. In the phase locked state, the symbol signal point at the center of one symbol section is at the level change point of the binarized phase angle differential signal. Therefore, V
If the SCO 33 generates a signal whose phase is shifted by 1/4 cycle (1/2 symbol length) from the above-described cyclic signal, and uses this as a clock signal, its falling edge and rising edge become symbol signal points. Further, if the VSCO 33 generates a 1/2 cycle signal that rises in synchronization with the rising edge of the periodic signal described above and uses this as a clock signal, the trailing edge becomes the symbol signal point. A value deviating from the above-mentioned median value 8 may be set as the predetermined value. The phase of the periodic signal output from the VSCO 33 is locked at the phase where the correlation value becomes the predetermined value. However, avoid locking the phase in the vicinity of the phase where the correlation value shows upper and lower peaks. When a value outside the median value of 8 is set as the predetermined value, it is necessary to determine the output phase of the signal that is output as the clock signal and is phase-synchronized with the periodic signal so that the phase angle can be determined at the timing of the symbol signal point. There is.

In the above description, as the reference phase bit string (reference phase signal), in the waveform representation shown in FIG. 9A, the left half of the duty ratio of 50% is all 1s and the right half is all 0s. However, a bit string obtained by cyclically shifting this array may be used. Of course, a plurality of reference phase bit strings may be used. Further, although the description has been given by making the cycle of the reference phase bit string and the cycle of the input binarized phase angle differential signal coincident with each other, they do not have to coincide with each other as long as the cycles are not significantly different. Although a slight deviation occurs depending on the setting of the cycle of the input signal, the cycle of the reference phase bit string, and the sampling clock cycle, the input signal is symmetrically or substantially symmetrically as shown in FIG. 9C. In the state accumulated in, the correlation value becomes a value at or near the median value. Therefore, at the time when the correlation value is the median value or a predetermined value near the median value and the correlation value has a positive slope, the VSCO
If the phase of the periodic signal output by 33 is locked, the periodic signal is synchronized with the period and phase of the input signal regardless of the period of the input signal unless the period of the input signal is significantly different from the period of the reference phase bit string. be able to.

In the illustrated example, binary values 0 and 1 are used to detect the correlation between bit data. However, the correlation can also be detected by other means. For example, if -1,1 is used as the binary value, the exclusive OR 4
By replacing the operation of 2 with multiplication, the correlation value can be output in the same manner. Instead of the input binarized phase angle differential signal, a pre-binarized phase angle differential signal including this (one sample value is a plurality of bits having polarity) may be used. Also, instead of the reference phase bit string, a reference phase data string including this (1 data is a plurality of bits having polarity)
May be used. In the case described above, if the function of the shift register 41 is executed by controlling the memory, it does not matter whether the input signal is bit data.

Now, returning to FIG. 7, description will be made. The error correction unit 34 receives the output of the latch 32 and inputs the output from the conventional PLL.
The error data is fed back to the VSCO 33 by performing the same correction calculation as that of the loop filter of No. 1, and the start phase of the next cycle is controlled. In this way, the digital PLL unit shown in FIG. 7 locks in. The synchronization determination unit 35 determines lock-in when the binarized phase angle differential signal and the phase of the periodic signal output by the VSCO 33 are synchronized, and outputs a signal phase-synchronized with this periodic signal as a clock signal. The phase angle determination unit 15 shown in 1 determines the phase angle of the central signal point of the symbol based on this clock signal. However, it is conceivable that a condition may be accidentally regarded as lock-in due to disturbances caused by various causes. Therefore, when the periodic signal output from the VSCO 33 is locked in a state in which the same period is maintained (a state in which no error correction is performed) over a plurality of predetermined symbols, it is determined to be synchronized.

In FIG. 10, when the periodic signal output from the VSCO 33 rises at or near time t = t ₃ , it is determined that the slope of the correlation value is opposite, as already described. it can. In this reverse state, the loop of the VSCO 33 is forcibly kicked, and the VSCO 33 starts from the next rising sampling timing.
Is controlled so that the output phase of the output signal becomes a VSCO output waveform as shown or a waveform having a phase close to this. As a result, fast lockup is possible.

The problem here is the phase jitter due to disturbance or SSB noise of the local oscillator. If there is phase jitter, the lock-in state may not be present at the next rising timing of the periodic signal output by the VSCO 33 even if it is determined that the lock-in is performed at the previous rising timing of the periodic signal output by the VSCO 33. However, if the phase jitter is light, the lock-in state will occur at the sampling timings before and after this. In this case, if there is no phase jitter, it is a state to be judged as "synchronized state", so that it must be allowed.

FIG. 11 is a block diagram of the second embodiment of the digital PLL device of the present invention. Figure 7
The same parts as those in FIG. 5
1 is an error determination unit, 52 is a 3-tap shift register,
Reference numeral 53 is a 1-sampling timing delay unit, 54 is a 3-bit latch, and 55 is a synchronization determination unit.

In the second example, the output of the correlation output unit 31 determines in the error determination unit 51 whether the absolute value of the error output is small, for example, 2 or less. When the absolute value of the error is 2 or less, "1" is set. When the absolute value is more than 2, "0" is set.
(The correlation value changes by ± 2 due to the phase shift of one sampling timing). The 3-tap shift register 52 shifts an input bit according to a sampling clock. The rising timing of the VSCO 33 is delayed by the 1-sample timing delay unit 53 and then input to the 3-bit latch 54. The output of the 3-tap shift register 52 is latched at the input rising timing, and the rising edge timing is input to the synchronization determination unit 55. Output in parallel. At this time, since the timing of the rising pulse of the VSCO 33 and the determination result of the error determination unit 51 at the timing before and after the one sampling clock are input to the 3-tap shift register, the 3-bit latch 54 also
This determination result is latched. Strictly speaking, the 1-sample timing delay section 53 delays the sample timing slightly longer than the 1-sample timing so that latching is performed after the 1-tap shift of the shift register 52 is completed.

The synchronization determination unit 55 considers jitter and
Follow the procedure below to establish symbol synchronization.
It (1) The lock-in judgment is based on the frequency output by the VSCO 33.
The correlation output unit 31 may have an error due to the rising timing of the synchronization signal.
The difference output is latched, and the error determination unit 51
When the value is within the predetermined value, for example, the error output is +
2, 0, -2 (within 1 sampling timing
Lock-in is true for the phase shift). Lock-in is true
, The central latch of the 3-bit latch 54 becomes 1.
It At this time, the error correction unit 34 causes the VSCO 33 to
The error data given to is zero. (2) One or more predetermined symbol lengths, preferably plural
For the symbol length, eg, 2 symbols,
It is determined that the lock-in state defined in (1) has continued.
Set. (3) Next, the rise of the periodic signal output by the VSCO 33
Timing of gari and each one sampler before and after
Three timings of error judgment output in clock signal
If there is a gap, the lock-in described above is true (3 bits
If any one of the latches 54 is 1), the symbol is the same.
The period acquisition operation is continued. (4) One or more of the symbol synchronization acquisition operations of (3)
If it is repeated a predetermined number of times, preferably a plurality of times, for example, four times, the maximum
The lock-in is finally determined, and the phase angle determination unit in the subsequent stage15
(Fig. 1) shows the clock signal output from VSCO 33.
Start external output of.

In the illustrated example, the 3-tap shift register 52 and the 3-bit latch 54 are used to determine the error between the rising timing of the VSCO 33, one sampling timing immediately before it, and one sampling timing immediately thereafter. Synchronized. Instead of this, the synchronization determination may be performed by determining the rising timing of the VSCO 33 and the error at each of a plurality of sampling timings before and after the rising timing. In this case, a shift register with four or more taps and a latch with the same number of bits may be used. In the multi-tap shift register, VSCO3 is selected according to the design of the tap position that holds the error at the rising timing of VSCO33.
The rising timing of 3 is delayed by a delay unit similar to the 1-sampling timing delay unit 53 so that the output of the shift register having a plurality of taps is captured in the latch of a plurality of bits. Alternatively, the synchronization determination may be performed by determining an error between the rising timing of the VSCO 33 and the sampling timings that are separated by a plurality of samples before and after the rising timing.

Next, the basic operation of the above digital PLL will be described. FIG. 12 is a block configuration diagram in which the digital PLL loop shown in FIG. 7 is simplified.
In the figure, 61 is a correlation output unit, 62 is an error correction unit, and 63 is V
SCO and latch. As shown in FIG. 12, the digital PLL includes a first-order IIR filter (Infinite impul
se Response Filter). The coefficient calculation in the error correction unit 62 is β = 1/2 by bit shift calculation.
And rounded down. Furthermore, VSCO63
When the phase is incremented (or decremented) by one step due to error correction, the output of the correlation output unit 61 that takes the exclusive OR is incremented (or decremented) by two steps, so α = 2 times here. Is being processed. As a result, the magnification becomes 1 in one loop. The transfer function by Z conversion is as follows. H (Z) = 1 / (1-αβZ ⁻¹ ) where α = 2 and β = 1/2

In the stability judgment by the characteristic equation, the pole of Z =
Since it becomes 1, it is the boundary where the system becomes unstable. But,
In the error correction unit, since the fraction is rounded down by 1/2 calculation, it can be determined that there is no problem in loop stability.
Let us consider the margin of the system for the differential operation.
The binarized phase angle differential signal is input to the correlation output unit 61, where the binarized phase angle differential signal is integrated over a data string having a length of 2 symbols. In addition, there is a PLL loop with a first-order IIR filter, and the total is 2
It has two integral elements. That is, although the input signal itself is a signal that has been differentiated, by using the digital PLL 14 described above, there are more integral operations as a whole. As a result, the symbol synchronization unit operates stably. This is a great advantage of the symbol synchronization unit 9 described above.

Next, noise and multi-bus fading will be briefly examined. Since all of these generate disturbance in the detected waveform (phase angle), the differentiated binary signal of the symbol synchronization preamble causes chattering pulses when the H and L levels are switched. However, these signals are canceled to some extent by being integrated by the correlation output unit 61 over two symbols.

The disturbance has a property that the amount of phase change is small, symbol interference is likely to occur, and is likely to occur at the leading edge and the trailing edge of the symbol. Furthermore, since the communication path environment does not change so much in a short time, the state of disturbance at the leading edge and the trailing edge can be estimated to be the same except for white noise. Apply this state to the circuit operation. It is assumed that the number sequence showing the transmitted signals for two symbols for each sampling value is x, the number sequence showing the occurrence of disturbance is e (the sampling point where the disturbance is generated is 1), and the received signal is y. However, for simplification, it is assumed that the transmission vector is differentiated, and “,” indicates a symbol delimiter. y: {01111110, 10000001} = x:
{11111111,00000000} + e: {10
000001, 10000001} Assume that the VSCO 33 is operating at the lock-in position where the two symbols are shifted by 1/2 symbol, and the correlation output unit 61
Then, the reference phase signal is correlated with two symbols.

FIG. 9C shows the signal x at this time,
FIG. 9F shows the signal y at this point. Phase comparison is
Since the exclusive OR (XOR) operation is performed for each sampling value, the result of XOR is {1111, 0000111111, 0000} when the disturbance is not generated, and in the above case where the disturbance is generated. , {1110,10
001110, 1000}, and the number of sampling points where 1 stands, that is, the correlation value is the same value 8 whether or not there is an error. That is, the error correction unit 62
Outputs a lock-in state, and symbol synchronization can be detected safely even if there is a disturbance.

The digital PLL section described above can be used not only in a symbol synchronizer in a frequency hopping receiver or the like, but also can input a signal having a periodicity by utilizing a structural feature having two integrating elements. Then, it can be used as a versatile digital PLL device that outputs a periodic signal synchronized with this signal.

In the above description, the symbol synchronization in the case where the carrier synchronization is not performed has been described. However, the symbol synchronization can be performed in the same configuration even when the carrier synchronization is performed. When carrier synchronization is performed, in FIG. 1, the differential operation by the differential output unit 10 is not always necessary. When the differentiating operation is not performed, the phase angle signal output from the phase angle calculating unit 8 is the binarizing unit 13.
Is binarized and input to the digital PLL unit 14. Even when demodulation is performed by differential detection instead of synchronous detection, symbol synchronization can be performed with the same configuration. Also in this case, the differential operation by the differential output unit 10 is not always necessary.

In the digital PLL section shown in FIG.
The correlation output unit 31 correlates the binarized phase angle signal with the reference phase bit string and outputs the correlation value. As the reference phase bit string, the one described above can be used as it is. In this case, the input waveform of the “binarized phase angle differential signal” shown in FIG.
Assuming that the input waveform of the “valued phase angle signal” is used, the one-symbol section is shifted by ¼ cycle and becomes a section showing “one symbol length”. Therefore, the rising point and the falling point of the periodic signal output from the VSCO 33 are the center points of the symbol section, in other words, the symbol signal points, so that the periodic signal can be output as it is as a clock signal.

[0052]

As is apparent from the above description, the digital PLL device of the present invention has the effect of being simple and not easily affected by the disturbance of the input signal. The symbol synchronization device of the present invention has an effect of enabling stable synchronization.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a digital demodulator for explaining an embodiment of a symbol synchronization device of the present invention.

FIG. 2 shows the reception of a symbol synchronization preamble.
FIG. 3 is an operation explanatory diagram of the block configuration of FIG. 1.

FIG. 3 is an explanatory diagram showing movement of a phase plane coordinate axis with reference to a carrier of a digitally modulated signal.

FIG. 4 is a block diagram of a histogram circuit.

5 is an explanatory diagram of a sampling signal input to the histogram circuit shown in FIG.

FIG. 6 is a schematic explanatory diagram for explaining a histogram of symbol change points.

FIG. 7 is a block configuration diagram of a first embodiment of a digital PLL device of the present invention.

8 is a block configuration diagram showing a correlation output unit shown in FIG. 7. FIG.

9 is an explanatory diagram of the operation of the correlation output unit in FIG.

10 is an explanatory diagram showing a correlation signal output from the correlation output unit in FIG.

FIG. 11 is a block configuration diagram of a second embodiment of a digital PLL device of the present invention.

FIG. 12 is a block configuration diagram in which the digital PLL shown in FIG. 7 is simplified.

FIG. 13 is a block diagram showing an example of a conventional frequency hopping system.

FIG. 14 is an explanatory diagram showing changes in carrier frequency in a frequency hopping system.

FIG. 15 is an explanatory diagram of a start portion of a transmission frame transmitted in one frequency hopping period in the frequency hopping system.

FIG. 16 is an explanatory diagram showing an example of a symbol synchronization preamble.

[Explanation of symbols]

1 Reference Frequency Oscillator, 8 IQ Phase Angle Calculation Unit, 9 Symbol Synchronization Unit, 10 Differentiation Output Unit, 11 1 Sampling Clock Delay Unit, 12 Subtractor, 13 Binarization Unit, 14
Digital PLL section, 31 correlation output section, 32 latch, 33 VSCO, 34 error correction section, 35 synchronization determination section

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04B 1/713 H03L 7/08 H04L 7/033 H04L 27/22 H04L 27/38

Claims (2)

(57) [Claims] 1. A digital PLL device for outputting a clock signal synchronized with a cycle of a digitally modulated input signal, comprising: a correlation output means, a periodic signal generating means, a phase error determining means, an error correcting means, and , A synchronization determination means, and the correlation output means outputs a binary signal of the input signal.
Input to the shift register sequentially, and
Inconsistency between the top output and the binarized reference phase data string
The level corresponding to the added value of the judgment output is judged.
Sequentially output as a correlation signal, the periodic signal generating means generates a period controllable periodic signal, and outputs the periodic signal or a signal based on the periodic signal as the clock signal, the phase error determination means, Predetermined phase timing of the periodic signal and timing before and after the predetermined phase timing
The level of the correlation signal as a phase error
The error correction means controls the cycle of the periodic signal according to the phase error, and the synchronization determination means sets the cycle of the input signal to one or a plurality of cycles.
The phase error at the predetermined phase timing
Is determined to be small, and then 1 of the periodic signal
Or, over a plurality of cycles, the predetermined phase timing and
Less phase error in the phase timing before and after
When it is determined that both are small, the clock
Digital PLL characterized by outputting signals to the outside
apparatus. 2. A symbol synchronization device for receiving a synchronization signal having a phase rotation direction inverted with respect to a carrier at a signal point of a digitally modulated signal, and generating a clock signal synchronized with a symbol of the digitally modulated signal. , Carrier synchronization means, phase angle output means, and digital P
An LL device, the carrier synchronization means outputs a reference frequency signal that follows the frequency of the carrier based on the synchronization signal, and the phase angle output means performs the digital modulation on the reference frequency signal. The symbol synchronization device according to claim 1 , wherein the digital PLL device is a PLL device according to claim 1 , which outputs a phase angle signal indicating a phase angle of a signal, and the digital PLL device receives the phase angle signal as an input signal.