JP3973332B2 - Digital modulation / demodulation synchronization system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit for demodulating a modulated wave modulated by a digital signal, and more particularly, to a synchronization method of a digital demodulator that asynchronously demodulates an angle-modulated wave modulated by differential encoding.
[0002]
[Prior art]
Conventionally, as a modulation / demodulation method of a digital signal, an amplitude modulation method for changing the amplitude of a carrier wave according to a state value of the digital signal and an angle modulation method for changing a phase or a frequency are well known. In general, an angle modulation system that is not easily affected by amplitude distortion in the transmission path is used.
Here, the π / 4 shift QPSK four-phase phase modulation (π / 4 shift QPSK) method of angle modulation having excellent distortion resistance and suitable for mobile communication will be briefly described.
FIG. 2 is a schematic configuration diagram of a conventional π / 4 shift QPSK modulator. As shown in the figure, the present modulation device includes a serial / parallel converter 61, a differential encoding circuit 62, low pass filters 63a and 63b, multipliers 64a and 64b, a 90 ° phase shifter 65, a signal generator 66, and An adder 67 is included.
In the above configuration, the serial / parallel converter 61 converts the input digital binary data string into unit data (X, Y) having a set of 2 bits. This unit data is generally called one symbol, and data processing is performed with this as one cycle.
The differential encoding circuit 62 generates a baseband signal composed of an I channel and a Q channel in which (X, Y) information is carried with respect to a change (difference) in the signal. The low-pass filters 63a and 63b limit the band of the baseband signal and output it to the multipliers 64a and 64b.
In the multipliers 64a and 64b, the in-phase component of the carrier wave ωC generated by the signal generator 66 and the phase of the output signal of the signal generator 66 by the 90 ° phase shifter 65 are changed to π / 2. The orthogonal components of the shifted carrier wave ωC are multiplied and amplitude-modulated, respectively, and then both are combined in an adder 67 to obtain a modulated wave.
[0003]
In the π / 4 shift QPSK system, amplitudes “A” and “−A” are assigned to binary signals “1” and “0”, and four signal point data (I, Q) are assigned to one symbol. Based on this, a four-phase phase modulation (QPSK) system that performs phase modulation based on this is basically used.
That is, as shown in the relationship diagram between the π / 4 shift QPSK symbol and the phase in FIG. 3, the arrangement of the I and Q signal points is the same as the QPSK signal point arrangement shown as a black dot in the figure for each symbol. The phase modulation is performed by alternately using the signal point arrangement indicated by white dots in the figure shifted by π / 4.
Therefore, the phase difference ΔΦ with respect to the preceding symbol is always an odd multiple of π / 4, and the relationship with the input unit data (X, Y) is expressed as in the table of FIG.
[0004]
On the other hand, the synchronous detection method and the delay detection method are well known as methods for demodulating the modulated wave, but in theory, the synchronous detection method has better characteristics, but high-speed fading occurs. In digital mobile communications in which sudden phase fluctuations are likely to occur, the delay detection method is more suitable than the synchronous detection method.
The delay detection method detects the next modulated wave with reference to the modulated wave delayed by the delay circuit having a predetermined delay time, and is thus modulated with the differentially encoded signal as described above. It is necessary to be a modulated wave. In addition, since it is not necessary to regenerate a carrier wave, the configuration is simpler than that of synchronous detection, which is suitable for mobile communication.
For example, in the case of the above-mentioned π / 4 shift QPSK system, the phase difference ΔΦ between the two is obtained by detecting the next modulated wave with reference to the phase of the modulated wave preceding by one symbol, and this is decoded according to the table of FIG. do it.
[0005]
FIG. 4A is a schematic configuration diagram showing a basic configuration of a conventional digital demodulator that demodulates a π / 4 shift QPSK modulated wave using delay detection. As shown in the figure, the demodulator includes multipliers 71a and 71b, a 90 ° phase shifter 72, a signal generator 73, low-pass filters 74a and 74b, A / D converters 75a and 75b, It comprises a delay detector 76, data identification units 77a and 77b, a clock recovery circuit 78, and a parallel / serial conversion unit 79.
In the above-described configuration, the input modulated wave is a signal having the same frequency as the carrier wave ωC generated by the signal generator 73 in the multipliers 71a and 71b and the phase of the carrier wave ωC is shifted by π / 2 by the 90 ° phase shifter 72. Each of the signals is multiplied to be converted into baseband signals of I channel and Q channel.
The I and Q signals are band-limited by low-pass filters 74a and 74b, respectively, and converted to digital signals by A / D converters 75a and 75b. A difference in signal point between the digitized I and Q signals and a signal preceding one symbol by the delay detection circuit 76, that is, a phase difference ΔΦ, is detected. Based on the relationship shown in FIG. Decrypt into Y.
[0006]
The detection signals X and Y from the delay detection circuit 76 are output to the data identification units 77a and 77b and the clock recovery circuit 78. The clock recovery circuit 78 determines a synchronization point to be described later, and supplies a synchronization clock signal to the data identification units 77a and 77b for each symbol period based on the synchronization point. The data identification units 77a and 77b determine basic data (X, Y) from the output signal of the delay detection circuit 76 based on the synchronous clock signal, and the basic data (X, Y) is converted into a parallel / serial converter. In 79, the signal is demodulated into a binary data string signal before modulation.
[0007]
FIG. 5A shows an eye pattern obtained by overwriting the detection signal from the delay detection circuit 76 a plurality of times. The eye pattern in which the binary signal (X =) 1 or 0 shown in FIG. The most open point (synchronization point) The signal level of Ps is generally identified as demodulated data of each symbol.
The important point in the above demodulation processing is how to determine the synchronization point. Conventionally, the clock recovery circuit determines the synchronization point and generates a synchronization clock signal. As a method, a method of detecting the maximum eye opening point of the eye pattern as a synchronization point is taken.
[0008]
As is apparent from the eye pattern shown in FIG. 5A, at the synchronization point Ps where the eye is most open, the level of the detection signal is concentrated at a relatively high density a or -a (X = 1 or 0). In the vicinity thereof, the level is almost the same as that of the synchronization point Ps. Conversely, the probability that the levels do not match increases as the distance from the synchronization point Ps approaches the zero cross point (Pc in the figure). That is, when a plurality of sample points are set for a detection signal for one symbol period, the signal level at each sample point is sampled, and the signal levels of two adjacent sample points are correlated, the signal levels match. The correlation increases in the vicinity of the synchronization point, and decreases when the signal levels of the two sample points are different. In other words, the correlation between the sampling values at the point Ps in FIG. 5A increases, but decreases at the point Pc. Focusing on this point, the correlation is detected, and the synchronization point is detected by comparing the magnitudes.
[0009]
Specifically, as shown in FIG. 5B, the signal level is sampled at predetermined sample points (8 points per symbol in the figure) every symbol period, and adjacent sample points are sampled. After detecting the correlation between the data, that is, P1 and P2, P2 and P3,... Sequentially, the correlation data is compared, and the sample point pair (P4 and P5 in FIG. A pair or a pair of P5 and P6) is obtained, and one of the sample point pairs is set as a synchronization point.
[0010]
FIG. 4B is a schematic configuration diagram of a conventional digital demodulation device to which the above-described method for detecting a correlation and setting a synchronization point is applied. In the configuration shown in FIG. 4, the clock synthesizing circuit 78 shown in FIG. 4A is composed of a correlation detection circuit 18a and a correlation determination circuit 18b.
In the figure, a correlation detection circuit 78a samples the levels of the detection signals X and Y input from the delay detection circuit 76 at a plurality of sample points set in advance for each symbol period, and two adjacent sample points. The correlations between the signals sampled as a set are detected, the detected correlations are added for each set of sample points corresponding to X and Y, and each of them is accumulated for a plurality of symbols before being output to the correlation determination circuit 78b. . In the correlation determination circuit 78b, the size of the correlation data is compared to detect the set of extraction points having the highest correlation, and one of the sample points is determined as the synchronization point, and the synchronization clock signal is determined as the data identification circuit. 77a and 77b.
[0011]
[Problems to be solved by the invention]
However, when there is very little noise in the transmission path of the modulated signal, the eye pattern of the received signal is clean and the correlation between the sample points can be taken without any problem as shown in the eye pattern example of FIG. When there is noise in the transmission path of the modulation signal, as shown in FIG. 6B, the eye pattern of the received signal is disturbed, and the signal levels of the sample points are scattered.
In such a state, the correlation value is lost, and the correlation does not always reach the maximum value at the synchronization point, the synchronization point cannot be determined, and the synchronization search operation is repeated again until the synchronization point is detected. There was a problem that it took a long time.
The present invention has been made to solve the above problems, and provides a synchronization method in digital modulation / demodulation capable of stably detecting a synchronization point even when there is noise in a modulation signal transmission line. For the purpose.
[0012]
[Means for Solving the Problems]
To solve the above problems, the synchronization method of the first aspect of the present invention, in the digital demodulation device to obtain a digital signal a modulated wave modulated by differential encoding by detecting a predetermined detection means, said detection means Sampling the output signal from a plurality of sample points set in advance for each unit data period (symbol period), and calculating a variance using a moving average for each sample point; First sync point detecting means for detecting a sample point indicating a minimum variance value from among the variances of the respective sample points calculated by the first variance calculating means, and samples detected by the first sync point detecting means. synchronization point establishment means distribution of points for outputting a synchronizing clock signal as a synchronization point the sample point when more than a predetermined variance threshold A second dispersion calculating means for calculating the variance of each sample point based on the average value of variance calculated in the previous SL sample points detected by the first synchronization point detecting means, which is calculated by said second distributed computation means and a second synchronization point detecting means for detecting a sample point showing the minimum of the distributed values from among the variance of each sample point, the dispersion of the first sample point detected by the synchronization point detection means a predetermined dispersion When the value is larger than the threshold value, the variance value of the sample point detected by the second synchronization point detection unit is compared with the variance value of the sample point detected by the first synchronization point detection unit, and the variance value is small. A synchronization clock signal is output from the synchronization point determination means with the other sample point as a synchronization point.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. In the synchronization method according to the present invention, in order to obtain the maximum eye opening of the eye pattern, a method of calculating variances from data values of a plurality of sample points set in advance in data for each period is adopted. At this time, the values that can be taken by the data values of the sample points at the synchronization point should be concentrated at a certain point, so the variance at the synchronization point is considered to be the smallest compared to the variance at the other sample points. Based on this, the variance at each sample point is obtained, and the sample point having the smallest value is set as the synchronization point, and the symbol “1” or “0” is determined.
[0014]
FIG. 1 is a schematic configuration diagram of a π / 4 shift QPSK demodulator based on a synchronization method according to the present invention.
As shown in the figure, the present modulation apparatus includes an A / D converter 1 that converts received analog data into a digital signal, multipliers 21a and 21b, a 90 ° phase shifter 22, a signal generator 23, and a thinning filter 24a. , 24b and low-pass filters 25a and 25b, a DDC unit 2, a Nyquist filter filter 3, a delay detector 4, a phase conversion unit 51 that takes an absolute value of an input signal, a moving average dispersion calculation unit 52, and an average value fixed The synchronization processing unit 5 includes a variance calculation unit 53 and a synchronization point determination unit 54, data determination units 6 a and 6 b, and a parallel / serial conversion unit 7.
The moving average variance calculation unit 52 is a block for obtaining a variance from the moving average, and an average value calculation unit 521 for obtaining a moving average of input data, a variance value calculation unit 522 for obtaining a variance for each sample point, and each sample point A minimum variance search unit 523 that searches for the minimum variance from among the variances of, and a synchronization point search unit 524 that searches for the position of the sample point that exhibits the minimum variance searched by the minimum variance search unit 523. The average value fixed variance calculation unit 53 is a block for obtaining a variance by fixing an average value of variance calculation. The average value fixed variance calculation unit 531, the average value fixed variance minimum value search unit 532, and the average It is comprised with the value fixed synchronous point search part 533.
[0015]
In the above configuration, the analog reception input is converted into a digital signal by the A / D converter 1 and output to the multipliers 21 a and 21 b of the DDC unit 2.
The signals input to the multipliers 21a and 21b are multiplied by a signal having a frequency equal to the carrier wave ωC generated by the signal generator 23 and a signal whose phase is shifted by π / 2 by the 90 ° phase shifter 22, respectively. And converted into an I signal and a Q signal in the baseband frequency band. Further, this signal is lowered to a predetermined sampling rate in the thinning circuits 24a and 24b, band-limited by the low-pass filters 25a and 25b, unnecessary signals are removed, and output to the Nyquist filter filter 3.
Wherein the Nyquist filter filters 3, I signal, Q signal is band-limited so as not to generate inter-symbol interference each detects a phase difference ΔΦ between the signal of one symbol preceding the delay detector 4, shown in Figure 3 Decode into X and Y based on the relationship.
[0016]
The above-described detection output signals X and Y are output from the data determination units 6a and 6b, respectively, and are also output to the phase conversion unit 51 of the synchronization processing unit 5 for data processing as follows. In this case, the signal output to the synchronization processing unit 5 may be either one of the X and Y signals of the detection output.
The data input to the phase conversion unit 51 are all converted to absolute values in order to calculate the average of the input data, and the average value calculation unit 521 obtains a moving average value in units of several tens of samples for each predetermined sample point. . Next, the moving average variance calculator 522 obtains the variance for each sample point based on the moving average value.
The moving average variance minimum value search unit 523 searches for the minimum variance value by comparing the variances of the sample points obtained by the moving average variance calculation unit 522. The moving average synchronization point search unit 524 searches for the position of the sample point at which the minimum variance is obtained, stores and holds this position as a synchronization point by the moving average, and averages the variance calculation at the synchronization point by the moving average. Is output to the variance calculation unit 531 of the average value fixed variance calculation unit 53.
[0017]
The average fixed variance calculation unit 53 is a block for obtaining a variance using a common average value for each sample point. The common average value is output from the moving average synchronization point search unit 524. Use the average of the variance values at the sync point.
The output data of the phase conversion unit 51 is input to the average value fixed variance calculation unit 531, and the variance for each sample point is calculated using the average value (fixed value) input from the moving average synchronization point search unit 524. The
The average value fixed variance minimum search unit 532 compares the variance of each sample point obtained by the average value fixed variance calculation unit 531 to obtain the minimum variance, and then the average value fixed synchronization point search unit 533 The sample point from which the minimum value of variance is obtained is searched and stored as a synchronization point.
However, in the calculation of variance using a moving average, when noise is added, the average value deviates from the average value that can be taken by the symbol of the original synchronization point, and the variance of the shifted point is obtained.
[0018]
Therefore, the synchronization point determination unit 54 compares the variance of the synchronization point by the moving average obtained by the moving average variance calculation unit 52 with a preset variance threshold value, and the variance value of the moving average is less than or equal to the threshold value. In such a case, the synchronization point obtained by the average synchronization point search unit 524 is determined as the final synchronization point.
On the other hand, if the variance value of the moving average is greater than or equal to the threshold value, the variance values of the synchronization points obtained by the moving average synchronization point search unit 524 and the average value fixed synchronization point search unit 533 are compared, and is smaller. The synchronization point from which the variance value is obtained is determined as the final synchronization point.
The synchronization point is determined as described above, and the synchronization clock signal is output to the data determination units 6a and 6b. The data determination units 6a and 6b acquire data at the timing of the synchronous clock signal and determine “0” or “1” of the data.
By determining the synchronization point by the above-described method, a stable and highly reliable synchronization point can be obtained even when there is a lot of noise in the data propagation path.
[0019]
【The invention's effect】
As described above, the synchronization method according to the present invention calculates the variance by the moving average of a plurality of predetermined sample points in order to obtain the synchronization in digital modulation / demodulation as the synchronization point at the point where the eye opening of the eye pattern is the maximum. If the minimum dispersion value among the obtained dispersions is less than or equal to a preset dispersion threshold value, the sample point indicating the minimum dispersion is synchronized.
Further, when the variance value is larger than a preset variance threshold, an average value obtained by calculating the minimum variance value by the variance by the moving average is obtained when obtaining variance at the predetermined plurality of sample points. The variance is obtained as an average value (fixed). Compare the minimum variance obtained from the variance of each sample point obtained by fixing this average value with the minimum variance obtained by the moving average, and select the sample point that shows the smaller variance value as the synchronization point. To do.
By doing so, the synchronization method of the present invention can stably capture the synchronization even when the signal quality deteriorates due to the noise of the propagation path, and greatly contributes to providing a synchronization method with high noise resistance. can do.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an embodiment of a π / 4 shift QPSK demodulator based on a synchronization method according to the present invention.
FIG. 2 is a schematic configuration diagram illustrating an example of a conventional π / 4 shift QPSK modulator.
FIG. 3 is a chart showing a relationship between a π / 4 shift QPSK symbol and a phase.
4A is a schematic configuration diagram showing a basic configuration of a conventional π / 4 shift QPSK demodulator, and FIG. 4B is a digital demodulation using a clock recovery circuit that detects a first issue and sets a synchronization point. 1 is a schematic configuration diagram illustrating an example of an apparatus.
FIG. 5A is an eye pattern of a detection signal;
(B) is explanatory drawing of the relationship between the eye pattern of a detection signal, and a sample point.
FIG. 6A is a diagram showing an example of an eye pattern when there is no noise;
(B) is a figure which shows an example of an eye pattern when there exists noise.
[Explanation of symbols]
(Hereinafter, according to the present invention)
1 .... A / D converter, 2 .... DDC part, 3 .... Nyquist filter,
4 .... delay detector, 5 .... synchronization processing unit, 6a, 6b ... data determination unit,
7. Parallel / serial converter, 21a, 21b, Multiplier,
22 ... 90 ° phase shifter, 23 ... Signal generator,
24a, 24b ... thinning filter, 25a, 25b ... low pass filter,
51 .. Phase conversion unit 52.. Moving average variance calculation unit
53 .. Average value fixed variance calculation unit 54.. Sync point determination unit
521 .. Moving average average value calculation unit,
522 .. Moving value variance calculation unit,
523 .. Moving average variance minimum value search unit,
524 .. Synchronous point search part of moving average,
531 .. variance value calculation unit with fixed average value,
532 ..Minimum variance search unit with fixed average value,
533 .. Sync point search unit with fixed average value (hereinafter related to the prior art)
61 .. Serial / parallel converter, 62 .. Differential encoding circuit,
63 ·· Low-pass filter, 64a, 64b ·· Multiplier,
65 ... 90 degree phase shifter, 66 ... Signal generator, 67 ... Adder,
71a, 71b, multiplier, 72, 90 ° phase shifter, 73, signal generator,
74a, 74b, low pass filter, 75a, 75b, A / D converter,
76. Delay detector 77a, 77b Data identification part
78 ·· Clock recovery circuit, 78a ·· Correlation detection circuit 78b ·· Correlation determination circuit, 79 ·· Parallel / serial converter

Claims (1)

In a digital demodulator for obtaining a digital signal by detecting a modulated wave modulated by differential encoding by a predetermined detection means,
First dispersion calculation means for sampling an output signal from the detection means at a plurality of sample points set in advance for each unit data period (symbol period) and calculating a dispersion using a moving average for each sample point When,
First synchronization point detection means for detecting a sample point indicating a minimum dispersion value from among the dispersions of the respective sample points calculated by the first dispersion calculation means;
Synchronization point determination means for outputting a synchronization clock signal with the sample point as a synchronization point when the variance of the sample points detected by the first synchronization point detection means is less than or equal to a predetermined dispersion threshold ;
Second variance calculation means for calculating the variance of each sample point based on the average value of the variance calculation of the sample points detected by the first synchronization point detection means;
Second synchronization point detection means for detecting a sample point indicating a minimum dispersion value from among the dispersions of the respective sample points calculated by the second dispersion calculation means,
When the variance of the sample points detected by the first sync point detecting means is larger than a predetermined variance threshold, the variance of the sample points detected by the second sync point detecting means and the first sync check A synchronization value of the sample point detected by the output means, and a synchronization clock signal is output from the synchronization point determination means with the sample point having the smaller variance value as a synchronization point. method.

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