JP2003218969A - Demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a demodulator that detects a symbol synchronization position by using sampled data and calculates a calculation amount without increasing the configuration by giving a synchronization timing for data determination after delay detection and prevents deterioration in demodulation quality even when the S/N is deteriorated in order to solve a problem of a conventional demodulation circuit that causes synchronization position extracting accuracy when the S/N is deteriorated. <P>SOLUTION: In the demodulator, an orthogonal detection circuit 1 applies orthogonal detection to a received signal, an analog/digital converter circuit 6 applies oversampling to the resulting signal, a delay detection circuit 2 takes a phase difference between the over-sampled orthogonal data and orthogonal data of one preceding symbol, when a data decision 4 decides the data of the phase difference according to a synchronization timing from the symbol synchronization circuit 3 and outputs demodulated data, the symbol synchronization circuit 3 obtains an in-phase component of a difference vector with the orthogonal data subjected to n-sample delay to extract synchronization timing and outputs it to the data decision circuit 4. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PSK demodulator in digital radio communication, and more particularly to a demodulator which has a small amount of calculation and can prevent deterioration of demodulation quality due to S / N deterioration.

[0002]

2. Description of the Related Art In digital radio communication, sampling clock timing synchronization or symbol timing synchronization is performed in order to properly receive the transmitted information signal by receiving the digital transmission signal transmitted from a digital radio transmitter on the receiving side. The synchronization probability technology such as frame synchronization is important. Especially in the demodulation process of the receiving device,
The symbol synchronization technology that extracts the optimum demodulation timing is
This is an important technology that determines the quality of the reception error rate.

A conventional clock timing recovery technique is disclosed in Japanese Patent Laid-Open No. 2000-6910 published on March 3, 2000.
No. 0 "Clock timing recovery circuit and demodulator" (Applicant: Nippon Telegraph and Telephone Corporation, inventor: Toshiaki Takao and others)
There is. This conventional technique uses a correction clock obtained by delaying a reference clock having a constant period by a time τ and performing phase correction, samples a baseband signal at a timing that advances a rising point or a falling point by δt, and samples the baseband signal. The square sum Ra ² of
The baseband signal is sampled at a timing in which the rising or falling point of the correction clock is delayed by time δt, the sum of squares Rb ² of the sampled baseband is obtained, and the sum of squares Ra ² of the sampled baseband and the square The sum Rb ² is compared, and if the result of the comparison is that the former is large, the time τ is shortened, and if the latter is large, the time τ is increased, and these are newly set as the time τ to generate a correction clock. This is a method of reproducing as a sample clock having a desired clock timing.

A configuration example of the technique disclosed in the above publication will be briefly described with reference to FIG. FIG. 5 is a block diagram showing a basic embodiment for realizing a conventional sample clock reproduction method, and shows an example of the structure of a demodulation device having a clock timing reproduction circuit. The conventional demodulator has an IF
A detector 5 to which a signal is input, and an analog / digital converter (A / D) for converting the detector output into a digital signal
6, a baseband signal processing circuit 7 for processing the sample signal output from the analog / digital converter 6 to obtain a decoded signal, and a clock timing recovery circuit for recovering the clock timing for obtaining the decoded signal from the IF signal and the sample signal 8 and.

The clock timing recovery circuit 8 includes a reference clock oscillator (O
SC) 81, a phase shifter 84 for phase-correcting this reference clock to generate a correction clock (t0), a sample clock generation circuit 85 for generating a sample clock from the correction clock, and a baseband signal sampled by the sample clock. Sum square circuit 82 for calculating the square value of the sample signal obtained by the above, and clock phase control for controlling the phase shifter by obtaining the clock phase control signal (φ) from the square value of the sample signal obtained by the square sum circuit 82. And a circuit 83.

That is, the conventional demodulator is a clock timing recovery circuit 8 for adjusting the phase of the sample clock for sampling the received baseband signal so that it becomes a desired phase, and a demodulator using the same.

The features of the prior art are as follows.
In the clock timing recovery circuit 8, a correction clock whose timing is delayed by a time τ with respect to the reference clock generated from the reference clock oscillator 81 is generated by the phase shifter 84, and this correction clock is advanced by the time δt. The sample clock generation circuit 85 generates a second timing sample clock with the correction clock delayed by the time δt, the A / D conversion circuit 6 samples the baseband signal at each timing, and the square sum circuit 82 first The sum of squares Ra ² of the baseband signals sampled at the timing of ¹ and the sum of squares Rb ² of the baseband signals sampled at the second timing are calculated and compared by the clock phase control circuit 83. The time τ is adjusted.

Specifically, in the clock phase control circuit 83,
When the sum of squares Ra ² is larger than the sum of squares Rb ² , the time τ is made slightly smaller to obtain the sum of squares R 2.
When b ² is larger than the sum of squares Ra ² , the time τ is slightly increased and the new time τ is supplied to the phase shifter 84.

The output of the sum-of-squares circuit 82 obtained by the conventional method and its averaged output have the waveforms shown in FIG. 5, and the maximum average or output is obtained at a timing substantially equal to the desired clock timing. That is what will happen. FIG. 5 is an explanatory diagram showing the output of the square sum circuit for confirming the synchronization point in the conventional demodulator and the averaged output waveform thereof.

Another conventional symbol timing detection technique is disclosed in Japanese Patent Laid-Open No. 200-2003 published on August 31, 2001.
1-237905 "Symbol Timing Detection Method"
(Applicant: Hitachi Kokusai Electric Inc., inventor: Kinichi Higurashi and others). This prior art is a symbol timing detection method in which a detected reception signal is oversampled N times per symbol period, and a symbol timing is detected from an in-phase component signal and a quadrature component signal in a preamble section of the oversampled reception signal. Of the in-phase component signal and the quadrature component signal are calculated, the position M1 at which the square value gives the maximum value and the position M2 at which the square value gives the minimum value are searched, and the midpoint m = M2 between M1 and M2.
(M1 + M2) / 2 found and the remainder mmod obtained by dividing m by N
This is a symbol timing detection method in which N is the symbol timing, whereby the amount of calculation for symbol timing detection can be reduced.

[0011]

However, in the technique of the above-mentioned conventional Japanese Patent Laid-Open No. 2000-69100, the difference between the peak (synchronization timing) of the averaged output waveform and other timing is small as shown in FIG. S / N of received signal
There is a problem that it is difficult to identify the peak timing at the time of deterioration, the synchronization position extraction accuracy is deteriorated, and the error rate characteristic at the time of demodulation is deteriorated. FIG. 6 is a waveform diagram showing a synchronization point in the conventional technique.

Further, the above-mentioned conventional Japanese Patent Laid-Open No. 2001-2379.
In the technique of No. 05, symbol timing is detected from the oversampled quadrature detection signal, and sampling is performed again in symbol units at the detected symbol timing. Therefore, a configuration for performing sampling is required twice, and the configuration is increased. There was a problem.

The present invention has been made in view of the above circumstances, and increases the configuration by detecting a symbol synchronization position using sampled data and giving a synchronization timing to data determination after differential detection. It is an object of the present invention to provide a demodulation device capable of reducing the amount of calculation without being required and preventing deterioration of demodulation quality even when S / N is deteriorated.

[0014]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art is a demodulator, in which a PSK-modulated received signal is quadrature-detected and separated into an in-phase component and a quadrature component of the quadrature signal. The phase difference between the quadrature detection circuit, the A / D conversion circuit that oversamples the in-phase component and the quadrature component of the quadrature signal and digitizes the quadrature data, and outputs the quadrature data from the quadrature data one symbol before is calculated. A differential detection circuit that takes the data, a data determination circuit that determines the data of the phase difference according to the synchronization timing, and outputs demodulated data;
A demodulator having a symbol synchronization circuit that supplies synchronization timing to a data determination circuit, wherein the symbol synchronization circuit inputs quadrature data from an A / D conversion circuit, and for each oversampling timing within one symbol. , The in-phase component of the difference vector with the orthogonal data delayed by the number of n samples, which is sufficiently smaller than the number of oversamplings,
Since it is a symbol synchronization circuit that outputs the oversampling timing that minimizes the in-phase component of the difference vector as the synchronization timing to the data determination circuit, the symbol synchronization position is detected using the oversampled data, and the data after delay detection is detected. By giving the synchronization timing to the determination, it is possible to reduce the calculation amount without increasing the configuration, and prevent the demodulation quality from being deteriorated even when the S / N is deteriorated.

According to the present invention for solving the above-mentioned problems of the conventional example, in a demodulator, a symbol synchronization circuit inputs quadrature data and delays by n samples, which is sufficiently smaller than the number of oversamplings. The n-sample delay circuit that outputs quadrature data, the complex conjugate circuit that calculates the vector difference between the quadrature data and the n-sample delayed quadrature data, and outputs the in-phase component of the vector difference as n-sample difference data, and the n-sample difference data are input. 1 symbol delay and output delayed n sample difference data 1
A symbol delay circuit, a difference circuit for obtaining the difference between the n-sample difference data and the delayed n-sample difference data, a square sum circuit for obtaining and outputting the sum of squares of the differences, and an output from the sum of squares circuit for one symbol oversampling. A symbol synchronization circuit having an averaging circuit for averaging at each timing and a synchronization detection circuit for outputting the oversampling timing that minimizes the output of the averaging circuit as the synchronization timing to the data determination circuit. Without doing so, it is possible to reduce the calculation amount and prevent deterioration of demodulation quality even when S / N is deteriorated.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. The demodulation device according to the present invention is
The SK-modulated received signal is quadrature-detected by the quadrature detection circuit to be separated into the in-phase component and the quadrature component of the quadrature signal, each of which is oversampled by the A / D conversion circuit to output quadrature data, and the delay detection circuit outputs one symbol. The phase difference with the previous quadrature data is taken, and the data decision circuit outputs the demodulated data by determining the data of the phase difference according to the synchronization timing from the symbol synchronization circuit. At this time, the symbol synchronization circuit inputs the quadrature data, For each oversampling timing within one symbol, the in-phase component of the difference vector with respect to the orthogonal data delayed by n samples, which is sufficiently smaller than the oversampling number, is obtained, and the oversampling timing at which the in-phase component of the difference vector is minimized is calculated. Since it is output to the data judgment circuit as the synchronization timing, it is oversampled. Using chromatography data to detect the symbol synchronization, by giving a synchronization timing data determined after the delay detection, reducing the amount of computation without increasing the structure,
In addition, the deterioration of demodulation quality can be prevented even when the S / N is deteriorated.

In the demodulator according to the present invention, the symbol synchronization circuit inputs the quadrature data, delays the number of n samples sufficiently smaller than the oversampling number, and outputs n sample delayed quadrature data, and an n sample delay circuit, A complex conjugate circuit that obtains a vector difference between orthogonal data and n-sample delayed quadrature data, and outputs the in-phase component of the vector difference as n-sample difference data, and n-sample difference data is input and delayed by one symbol to delay n-sample difference data. A 1-symbol delay circuit that outputs, a difference circuit that calculates the difference between the n-sample difference data and the delayed n-sample difference data, and a square sum circuit that calculates and outputs the sum of squares of the differences.
An averaging circuit that averages the output from the square sum circuit at each oversampling timing of one symbol, and a synchronization detection circuit that outputs the oversampling timing that minimizes the output of the averaging circuit to the data determination circuit as the synchronization timing. Since it has, the amount of calculation can be reduced without increasing the configuration, and the deterioration of the demodulation quality can be prevented even when the S / N is deteriorated.

First, a schematic configuration of a demodulation device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a schematic block diagram of a demodulator according to the present invention. The demodulator according to the embodiment of the present invention, as shown in FIG.
It includes a quadrature detection circuit 1, A / D conversion circuits 6a and 6b, a delay detection circuit 2, a symbol synchronization circuit 3, and a data determination circuit 4.

Each part of the demodulation device of the present invention will be described. The quadrature detection circuit 1 receives the received high frequency (Radio Frequency
ncy: RF) signal is quadrature-detected and in-phase component signal I
(T) and the quadrature component signal Q (t) are separated and output.

The A / D conversion circuit 6a receives the in-phase component signal I
(T) is sampled and in-phase component digital data (referred to as in-phase component data) I ′ (t) is output. T-sampling is performed on one symbol and output. Similarly, the A / D conversion circuit 6b
Is for sampling the quadrature component signal Q (t) and outputting digital data (referred to as quadrature component data) Q ′ (t). T symbol is oversampled and output for one symbol. . In-phase component data I '
(T) and the orthogonal component data Q '(t) are collectively referred to as orthogonal data.

The differential detection circuit 2 takes a complex conjugate of the sampled quadrature data (the in-phase component data I '(t) and the quadrature component data Q' (t)) with the quadrature data one symbol before. This is a general differential detection circuit that obtains a phase difference by. The symbol synchronization circuit 3 extracts the optimum demodulation timing (synchronization timing) of the quadrature detection output I (t) and Q (t), and the synchronization timing extraction method here is a feature of the present invention. Details will be described later. The data determination circuit 4 uses the synchronization timing signal from the symbol synchronization circuit 3 to determine the sign of the phase difference value from the delay detection circuit 2 according to the modulation method, and outputs it as demodulated data.

Next, the synchronization timing extraction method in the symbol synchronization circuit 3 of the demodulator of the present invention will be described. In the synchronization timing extraction method of the present invention, due to the nature of phase modulation (Phase Shift Keying: PSK modulation) performed on the transmission side, the phase-modulated modulated wave only shifts the phase at the symbol point, that is, the amplitude does not change, that is, The symbol points are always constant amplitude points. By taking advantage of this property, when the vector difference between two signals near the symbol point of the received modulated wave is obtained, the orthogonal component of the vector difference takes a large value, but the in-phase component of the vector difference is 0.
It should be close to (zero).

Therefore, for the quadrature data (in-phase component data I '(t) and quadrature component data Q' (t)) obtained by over-sampling the quadrature detection output of the received wave for one symbol, the number of over-sampling is sufficient. A small n number of samples, for example, a vector difference (called a 2-sample difference) from orthogonal data delayed by 2 samples is obtained, and the timing at which the in-phase component of the 2-sample difference is the smallest is the synchronization timing.

The sampling interval for obtaining the vector difference is not limited to two samples,
It suffices if it is sufficiently small with respect to the number of oversamplings and is an even number of samples. For example, if the number of oversamplings is 10, 2 samples are appropriate.

Here, the reason why the sampling interval for obtaining the vector difference is set to an even sample will be described. When the time at the symbol position is A, the two timings sandwiching the symbol position are (A-Δt1) and (A + Δt).
Consider 2).

Considering the received signal R separated into I-phase and Q-phase quadrature signals, R (t) = I (t) + jQ (t), and the received signal at the symbol position and the time before and after the above timing. Is R (A) = I (A) + jQ (A) R (A-Δt1) = I (A-Δt1) + jQ (A-Δt1) R (A + Δt2) = I (A + Δt2) + jQ (A + Δt2).

Then, two timings sandwiching the symbol position
The difference vector Rs of the received signal of
Asked, R_S= R (A-Δt1) ・ R^*(A-Δt2) = I_S+ JQ_S Then,   I_S= I (A-Δt1) I (A + Δt2) + Q (A-Δt1) Q (A + Δt2)   Q_S= I (A-Δt1) Q (A + Δt2) + Q (A-Δt1) I (A + Δt2)                                                           (Equation 1) Is.

Where I (A) is I_Sym, Q (A) to Q
_SymAnd I (A-Δt1) is I_{Sy m}-ΔM_I, Q
Q of (A-Δt1)_Sym-ΔM_Q, I (A + Δt2) is I
_Sym+ ΔP_I, Q (A + Δt2) is Q_Sym+ ΔP_QWhen
If set, the in-phase component I of (Equation 1) I_SIs   I_S= (I_Sym-ΔM_I) (I_Sym+ ΔP_I) + (Q_Sym-ΔM_Q) (Q_{Sy m} + ΔP_Q)       = I_Sym ^Two+ (ΔP_I-ΔM_I) I_Sym-ΔM_IΔP_I         + Q_Sym ^Two+ (ΔP_Q-ΔM_Q) Q_Sym-ΔM_QΔP_Q Becomes The quadrature component Q_SIs not used, so nothing
To see.

In-phase component I of this difference vector_SIs 1
The same applies to the symbol before, so the symbol one symbol before
I '_SIs I '_S= I '_Sym ^Two+ (ΔP '_I-ΔM '_I) I '
_Sym-ΔM '_IΔP '_I + Q '_Sym ^Two+ (ΔP '_Q
-ΔM '_Q) Q '_Sym-ΔM '_QΔP '_Q Is.

Therefore, I_SAnd I'one symbol before_SWith
If you take the difference,   I_S-I '_S= (I_Sym ^Two+ Q_Sym ^Two)-(I '_Sym ^Two+ Q '_Sym ^Two)               + (ΔP_I-ΔM_I) I_Sym-ΔM_IΔP_I                   − (ΔP ′_I-ΔM '_I) I '_Sym+ ΔM '_IΔP '_I               + (ΔP_Q-ΔM_Q) Q_Sym-ΔM_QΔP_Q                   − (ΔP ′_Q-ΔM '_Q) Q '_Sym+ ΔM '_QΔP '_Q                                                                 (Equation 2) Becomes

In the above (Formula 2), the present invention is premised.
Since the PKS modulation method used is constant envelope modulation, (I_Sym ^Two+ Q_Sym ^Two)-(I '_Sym ^Two+ Q '
_Sym ^Two) = 0 Is. Also, since ΔM and ΔP are very small, ΔM_IΔP_I= ΔM_QΔP_Q= ΔM '_IΔP '_I= Δ
M '_QΔP '_Q≒ 0 If it is approximated by
Minute I_SThe difference between the symbols is   I_S-I '_S≈ (ΔP_I-ΔM_I) I_Sym− (ΔP ′_I-ΔM '_I) I '_Sym             + (ΔP_Q-ΔM_Q) Q_Sym− (ΔP ′_Q-ΔM '_Q) Q '_Sym                                                                 (Equation 3) Can be replaced with

Where I _Sym , Q _Sym ,
Since _I'Sym and _Q'Sym are each component at the symbol point, they may take various values. Therefore, in order to obtain a point where the power of the inter-symbol difference of the in-phase component I _S of the difference vector is smaller. it is desired is _{ΔP I -ΔM I ≒ 0 ΔP '} I -ΔM' I ≒ 0 ΔP Q -ΔM Q ≒ 0 ΔP 'Q -ΔM' Q ≒ 0 ( Equation 4).

In order to establish the relationship of (Equation 4) before and after the symbol point, Δt1, which is the interval between the timing of two received signals for which the difference vector is obtained and the symbol timing.
It is sufficient that Δt2 is Δt1≈Δt2.

Therefore, as the interval between the two received signals for which the vector difference is obtained, as shown in FIG. 7A, a signal (x in the figure) located at the same (time) distance as the time of the symbol point ( in the figure). ), This signal is a signal 2m × Δt apart when the oversampling interval is Δt, and the sampling interval for obtaining the vector difference needs to be an even sample. FIG. 7 is an explanatory diagram for explaining the sampling interval for obtaining the vector difference in the present invention.

If the sampling interval for obtaining the vector difference is set to an odd number of samples (for example, 3), FIG.
As shown in (b) and (c), the time intervals from the two received signals for which the vector difference is obtained to the symbol points are not equidistant, and the relationship of (Equation 4) does not hold. Therefore, the sampling interval for obtaining the vector difference needs to be sufficiently small with respect to the number of oversamplings and be an even number of samples.

In accordance with the above principle, in the present invention, the in-phase component of the difference of two samples of the quadrature data with respect to the timing of the same oversampling timing (number) for one symbol is taken into consideration in consideration of some variation in the synchronization timing. For the above, the sum of squares of the difference from the preceding symbol is further calculated, and averaged over a plurality of symbols, and the oversampling timing (number) that minimizes the average value is determined to be the synchronization timing.

Here, the principle of the synchronization timing extraction method of the present invention will be described using mathematical expressions and figures. In the description here, 8-phase PSK (Phase Shift Keying) is used, but the present invention is not limited to 8-phase, and BPSK,
Any constant envelope modulation such as QPSK or 16PSK can be applied.

When the modulated reception signal is R (t) (t is the sampling number), R (t) is quadrature-detected by the quadrature detection circuit 1 and the quadrature of I-phase and Q-phase is expressed by the following equation. Separated into signals. R (t) = I (t) + jQ (t) Then, assuming that the sampling number of one symbol (that is, the oversampling number) is T, the delay detection circuit 2 outputs R
If the complex conjugate of (t) and the data R ^* (tT) one symbol before is taken and the differential detection output signal which is the phase difference is R _D (t), then R _D (t) is as follows: . R _D (t) = R (t) ^* R ^* (tT) = [I (t) + jQ (t)] * [I (tT) -jQ (tT)] = [I (t) I (tT) + Q (t) Q (tT)] + j [Q (t) I (tT) -I (t) Q (tT)]

At this time, in the symbol synchronizing circuit 3, first,
In order to obtain the vector difference (two-sample difference) from the orthogonal signal (data) delayed by two samples, the complex conjugate of R (t) and the data R ^* (t-2) two samples before is performed, and the result is Assuming a 2-sample difference R _S (t), R _S (t) can be expressed by the following equation using a difference vector. R _S (t) = R (t) · R ^* (t-2) = I _S (t) + jQ _S (t)

Next, using the real number part (in-phase component) I _S (t) (2 sample difference data) in the difference vector of the 2 sample difference of the above equation, 2 sample difference data (delayed 2 sample difference) one symbol before Sum of squares of the difference with
_{When YN} (t) is obtained, S _YN (t) is given by the following equation. _{S YN (t) = (I} S (t) -I S (tT)) 2

When one symbol is oversampled by T, a remainder value (represented by t% T) obtained by dividing the sampling number t by the oversampling number T is a symbol synchronization point candidate. Therefore, the sum of squares S _YN (t) obtained above is
The sum of squares P (t% T) averaged over a plurality of symbols can be obtained by adding and averaging for each sample timing at which t% T becomes the same. As an example of averaging, P (t% T) = P (t% T) × λ + _SYN (t% T) × using a weighting factor λ (0 <λ <1)
It can be calculated by (1-λ).

Next, a configuration example of the symbol synchronization circuit 3 for realizing the above-described synchronization timing extraction method will be described with reference to FIG. FIG. 2 is a block diagram showing an internal configuration example of the symbol synchronization circuit 3 of the demodulation device of the present invention.
The inside of the symbol synchronization circuit 3 of the demodulation device of the present invention includes a 2-sample delay circuit 31, a complex conjugate circuit 32, a 1-symbol delay circuit 33, a difference circuit 34, and a square sum circuit 35.
It is composed of an averaging circuit 36 and a synchronization detecting circuit 37. The 2 sample delay circuit 31 corresponds to the n sample delay circuit in the claims.

Each part inside the symbol synchronization circuit 3 will be described. The 2-sample delay circuit 31 receives the input quadrature data (in-phase component data I ′ (t) and quadrature component data Q ′).
It is a delay element that delays by 2 samples with respect to (t), and outputs 2 sample difference data. The number of delay samples here is not limited to two samples, and may be an even number sample that is sufficiently smaller than the number of oversamplings. For example, if the number of oversamplings is 10, then 2 samples are appropriate, and thereafter 2
An example of sample delay will be described.

The complex conjugate circuit 32 inputs the quadrature data (in-phase component data I '(t) and quadrature component data Q').
(T)) is a general complex conjugate circuit that obtains the vector difference (two sample difference) of two samples by taking the complex conjugate of the orthogonal data two samples before delayed by the two sample delay circuit 31. Two-sample difference in-phase component _IS
Only (t) is output as 2-sample difference data.

The 1-symbol delay circuit 33 inputs 2
For the in-phase component I _S (t) (two-sample difference data) of the sample difference, one symbol (oversampling number T
Is a delay element that delays by T samples), and outputs it as delay 2 sample difference data. The difference circuit 34 outputs the in-phase component I _S (t) of the 2-sample difference output from the complex conjugate circuit 32 and the in-phase component I _S (tT of the 2-sample vector difference one symbol before output from the 1-symbol delay circuit 33. ) (Delayed 2 sample difference data). Square sum circuit 35, to take the absolute value of the difference of the in-phase component I _S of 2 samples obtained difference by the difference circuit 34, by squaring the difference between the in-phase component I _S outputs a square sum S _{YN (t)} It is a square sum circuit.

The averaging circuit 36 averages the values at the oversampling timing (number) for one symbol with respect to the sum of squares S _YN (t) output from the sum of squares circuit 35 over a plurality of symbols, and the average value P ( t%
T) is output. Specifically, the remainder of dividing the sampling number by the number of oversampling (T) is
Since it is an oversampling number for one symbol, the square sum circuit 35 is provided for each oversampling number.
When the sum of squares _SYNY (t) output from the above is added with appropriate weighting, the average value over a plurality of symbols at each oversampling number is obtained as the averaged output P (t% T). It will be.

The synchronization detection circuit 37 outputs a timing signal with the timing of the oversampling number that minimizes the averaged output P (t% T) from the averaging circuit 36 as the synchronization timing.

Next, regarding the operation of the demodulator of the present invention,
This will be described with reference to FIGS. In the demodulator of the present invention,
The received modulation signal (RF signal) is quadrature detected by the quadrature detection circuit 1 and separated into an in-phase component signal I (t) and a quadrature component signal Q (t) of the quadrature signal, and the A / D conversion circuits 6a, 6
In-phase component data I '(t) and quadrature component data Q' (t) of the quadrature data which are respectively oversampled T times in b
Is output.

At this time, in the symbol synchronizing circuit 3, the quadrature data (in-phase component data I '
(T) and the quadrature component data Q '(t) are delayed by two samples, and the quadrature data (the in-phase component data I' (t) and the quadrature component data Q '(t)) are delayed by 2 in the complex conjugate circuit 32. A complex conjugate of the quadrature data (in-phase component data I ′ (t−2) and quadrature component data Q ′ (t−2)) two samples before delayed by the sample delay circuit 31 is taken and a vector of two samples is obtained. The difference (2 sample difference) is obtained, and the in-phase component I _S (t) (2 sample difference data) is output.

Then, the in-phase component I of the difference of two samples I
_S (t) (2 sample difference data) is delayed by 1 symbol (T samples when the oversampling number is T) in the 1-symbol delay circuit 33 and output as delayed 2-sample difference data, which is then output to the complex circuit in the difference circuit 34. Conjugate circuit 32
The in-phase component I _S (t) of the two-sample difference output from
In-phase component I _S of the two-sample vector difference one symbol before
(tT) (delayed 2 sample difference data) is taken, and the sum of squares is further summed by the sum of squares circuit 35 to output the sum of squares S _YN (t).

Then, in the averaging circuit 36, the sum of squares S _YN (t) from the sum of squares circuit 35 is obtained at each timing (each oversampling number) of the remainder value obtained by dividing the sampling number by the oversampling number (T). Timing at which the averaged output P (t% T) is averaged and output at each timing, and the synchronization detection circuit 37 minimizes the averaged output P (t% T) from the averaging circuit 36. Is detected and is output as the synchronization timing when it becomes the minimum.

The quadrature detection circuit 1 outputs A / A
The in-phase component data I ′ (t) and the quadrature component data Q ′ (t) of the quadrature data oversampled by the D conversion circuits 6a and 6b are multiplied by the quadrature data of one symbol before in the differential detection circuit 2. The delay detection output signal R _D (t), which is the phase difference, is obtained by conjugation, and the data determination circuit 4
In (1), the differential detection output signal R _D (t) is subjected to code determination according to the synchronization timing from the symbol synchronization circuit 3 and demodulated data is output.

The average sum of squares P (t% output from the averaging circuit 36 in the symbol synchronizing circuit 3 described above is used.
For example, when the oversampling number T is 10, T) is a certain value of t% 10 (see FIG. 3A), as shown in FIG.
Then, in 5), the point where P (t% 10) changes to the bottom and this P (t% 10) becomes minimum (timing)
Is the symbol synchronization point. FIG. 3 is an explanatory diagram showing a state of the averaged sum of squares P (t% 10) at each sample number in one symbol.

In the same system, even when noise of S / N = 20 dB is added to the receiver input signal R (t), as shown in FIG. 3 (b), P (t
% 10) can be detected, and the symbol synchronization position can be sufficiently extracted even in a noise environment.

B when the demodulator of the present invention is used
The measurement result of the ER (Bit Error Rate) characteristic is shown in FIG.
FIG. 4 is a graph showing the measurement result of the BER characteristic in the demodulation device of the present invention. In FIG. 4, the weighting factor λ =
The case of 0.95 is shown. As can be seen from FIG. 4, a quadrature signal (data) of the received signal as in the demodulator of the present invention.
When the data determination after the differential detection in symbol units is performed with the oversampling timing at which the absolute value of the difference between the adjacent symbols of the in-phase component of the vector difference of 2 samples in (1) is set as the synchronization timing, there is little noise. However, even if there is a lot of noise, it is possible to achieve synchronization in a form that is very close to ideal synchronization.

In the configuration of the present invention shown in FIG. 2, the complex conjugate circuit 32 is described as outputting only the in-phase component I _S (t) with a difference of two samples.
Both the in-phase and quadrature components of the two-sample difference may be output, the difference circuit 34 may obtain the difference from the two-sample vector difference one symbol before, and only the in-phase component of the difference may be output.

According to the demodulator of the present invention, the PSK-modulated received signal is quadrature detected by the quadrature detection circuit 1 to be separated into the in-phase component and the quadrature component of the quadrature signal, and the A / D conversion circuit 6a,
6b oversamples each to output quadrature data, and the delay detection circuit 2 takes a phase difference from the quadrature data one symbol before, and the data determination circuit 4 uses the symbol synchronization circuit 3
Since the phase difference data is determined and the demodulated data is output in accordance with the synchronization timing from the above, if the number of oversamplings for one symbol is sufficient, Japanese Patent Laid-Open No. 2000-69
There is no need to adjust the sampling clock for synchronization as in No. 100, and the synchronization timing can be extracted from the sampled data, so that the configuration can be simplified.

Further, in the demodulator of the present invention, the symbol synchronization circuit 3 inputs the orthogonal data and delays each oversampling timing within one symbol by n samples which is sufficiently smaller than the oversampling number. Since the in-phase component of the difference vector with the data is obtained and the oversampling timing at which the in-phase component of the difference vector is minimized is output as the synchronization timing to the data determination circuit 4, the symbol synchronization position is detected using the oversampled data. However, by providing the synchronization timing for the data determination after the differential detection, the method disclosed in Japanese Patent Laid-Open No. 2001-2379
As in the technique of No. 05, there is no need to perform sampling again in symbol units, the amount of calculation can be reduced without increasing the configuration, and deterioration of demodulation quality can be prevented even when S / N is deteriorated. There is.

Further, according to the demodulator of the present invention, in the symbol synchronization circuit 3, the 2-sample delay circuit 31 inputs the quadrature data and delays by n samples (for example, 2 samples) sufficiently smaller than the oversampling number. Two
The sample delay quadrature data is output, and the complex conjugate circuit 32
, The vector difference between the quadrature data and the 2-sample delayed quadrature data is obtained, and the in-phase component of the vector difference is output as 2-sample difference data.
The sample difference data is input, delayed by one symbol, and delayed 2 sample difference data is output.
The difference between the sample difference data and the delayed two-sample difference data is calculated, the square sum circuit 35 calculates and outputs the square sum of the difference, and the averaging circuit 36 outputs the output from the square sum circuit 35 at each symbol oversampling timing. Since the synchronization detection circuit 37 outputs the oversampling timing at which the output of the averaging circuit 36 is the minimum to the data determination circuit as the synchronization timing, only the in-phase component of the vector difference from the 2-sample delayed quadrature data is Since 1-symbol delay, difference, sum of squares, and averaging are performed, there is an effect that the amount of calculation can be reduced and the synchronization timing can be extracted without increasing the configuration.

The average sum of squares of the difference between the in-phase component of the n-sample difference vector and the symbol one symbol before, which is obtained by the synchronization timing extraction method of the present invention, becomes minimum at the symbol timing, and noise is added to the received signal. Also, since the symbol timing becomes minimum at the symbol timing and the symbol timing can be reliably extracted, there is an effect that the deterioration of the demodulation quality can be prevented even when the S / N is deteriorated.

[0061]

According to the present invention, a PSK-modulated received signal is quadrature-detected by a quadrature detection circuit to be separated into an in-phase component and a quadrature component of the quadrature signal, and each is oversampled by an A / D conversion circuit to be quadrature. Outputs data and outputs 1 by delay detection circuit
This is a demodulator that takes the phase difference from the quadrature data before the symbol, determines the data of the phase difference according to the synchronization timing from the symbol synchronization circuit in the data determination circuit, and outputs the demodulated data. For each oversampling timing within one symbol, the in-phase component of the difference vector with respect to the orthogonal data delayed by n samples, which is sufficiently smaller than the oversampling number, is obtained, and the in-phase component of the difference vector is minimized. Since the demodulator outputs the sample timing as the synchronization timing to the data determination circuit, the symbol synchronization position is detected using the oversampled data, and the synchronization timing is given to the data determination after the delay detection to increase the configuration. Reduce the amount of calculation without
Moreover, there is an effect that the deterioration of the demodulation quality can be prevented even when the S / N is deteriorated.

Further, according to the present invention, in the symbol synchronization circuit, the n-sample delay circuit inputs quadrature data,
The n-sample delayed quadrature data is delayed by delaying the n-sample number sufficiently smaller than the oversampling number, and the complex conjugate circuit obtains the vector difference between the quadrature data and the n-sample delayed quadrature data, and the in-phase component of the vector difference is n. The difference circuit outputs as sample difference data, the 1-symbol delay circuit inputs n-sample difference data, delays by 1 symbol, and outputs delayed n-sample difference data.
The difference between the n-sample difference data and the delayed n-sample difference data is calculated, the sum of squares circuit calculates and outputs the sum of squares of the differences, and the averaging circuit averages the output from the sum of squares circuit at each symbol oversampling timing. Since the synchronization detection circuit is a demodulator that outputs the oversampling timing at which the output of the averaging circuit is the minimum to the data determination circuit as the synchronization timing, only the in-phase component of the vector difference from the n-sample delayed quadrature data is
Since 1-symbol delay, difference, sum of squares, and averaging are performed, there is an effect that the amount of calculation can be reduced and the synchronization timing can be extracted without increasing the configuration.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a demodulator according to the present invention.

FIG. 2 is a block diagram showing an internal configuration example of a symbol synchronization circuit of the demodulation device of the present invention.

FIG. 3 is an explanatory diagram showing a state of an average sum of squares P (t% 10) at each sample number in one symbol.

FIG. 4 is a graph showing the measurement results of BER characteristics in the demodulation device of the present invention.

FIG. 5 is a block diagram showing a basic embodiment for realizing a conventional sample clock reproduction method.

FIG. 6 is a waveform diagram showing a synchronization point in the conventional technique.

FIG. 7 is an explanatory diagram illustrating a sampling interval for obtaining a vector difference according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Quadrature detection circuit, 2 ... Delay detection circuit, 3 ... Symbol synchronizing circuit, 4 ... Data determination circuit, 31 ... 2 sample delay circuit, 32 ... Complex conjugate circuit, 33 ... 1 symbol delay circuit, 34 ... Difference circuit, 35 … Square sum circuit,
36 ... Averaging circuit, 37 ... Synchronization detection circuit, 5 ... Detector, 6,6a, 6b ... A / D conversion circuit, 7 ... Baseband signal processing circuit, 8 ... Clock timing recovery circuit, 81 ... Reference clock oscillator, 82 ... Sum of squares circuit, 83 ... Clock phase control circuit, 84 ... Phase shifter, 85 ... Sample clock generation circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5K004 AA05 FG02 FG03 FG04 FH08                       FH09                 5K047 AA03 BB01 EE02 HH15 MM38

Claims (2)

[Claims] 1. A quadrature detection circuit for quadrature-detecting a PSK-modulated received signal to separate it into an in-phase component and a quadrature component of the quadrature signal, and an in-phase component and a quadrature component of the quadrature signal are oversampled and digitized, respectively. A / which outputs orthogonal data
A D conversion circuit; a differential detection circuit that takes a phase difference between the orthogonal data and the orthogonal data one symbol before; a data determination circuit that determines the phase difference according to synchronization timing and outputs demodulated data; A demodulator having a symbol synchronization circuit that supplies synchronization timing to a determination circuit, wherein the symbol synchronization circuit inputs the orthogonal data from the A / D conversion circuit, and for each oversampling timing within one symbol. Then, the in-phase component of the difference vector with respect to the quadrature data delayed by the number of n samples, which is sufficiently smaller than the oversampling number, is obtained, and the oversampling timing at which the in-phase component of the difference vector is minimized is used as the synchronization timing in the data determination circuit. A demodulator, which is a symbol synchronization circuit for outputting. 2. An n-sample delay circuit for inputting quadrature data, delaying an n-sample number sufficiently smaller than an oversampling number, and outputting n-sample delayed quadrature data; A complex conjugate circuit that obtains a vector difference of sample-delayed quadrature data and outputs an in-phase component of the vector difference as n-sample difference data; and inputs the n-sample difference data and delays by 1 symbol to output delayed n-sample difference data A 1-symbol delay circuit, a difference circuit for obtaining a difference between the n-sample difference data and the delayed n-sample difference data, a square sum circuit for obtaining and outputting a square sum of the difference, and an output from the square sum circuit. An averaging circuit for averaging each symbol at each oversampling timing; Demodulator of claim 1, wherein the output of a symbol synchronization circuit having a synchronization detection circuit for outputting a data decision circuit as synchronization timing oversampling timing having the minimum.