JP2013128225A - Synchronization system and receiver including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To establish symbol synchronization accurately in a receiver with a simple configuration, without being affected by an amplitude level or jitter at a zero-cross point.SOLUTION: The synchronization system includes a 3-bit extraction unit 2 extracting from a demodulation signal three continuous bits sequentially while shifting bit by bit, a median value determination unit 3 for determining that the median value has the maximum absolute value out of the three bits thus extracted, and a synchronization establishment unit 4 for setting the sampling timing of the median value determined to be maximum as the symbol synchronization timing.

Description

  The present invention relates to a synchronization system that detects a peak of an amplitude level of a received signal and establishes symbol synchronization in communication, and a receiving apparatus including the same.

  In conventional receivers, for example, a technique of establishing symbol synchronization by a zero cross detection method has been widely used. FIG. 29 shows a signal having a demodulated binary value. Assuming that the demodulated binary signal is “−1” and “+1”, it passes through the center zero when changing from “−1” to “+1” or from “+1” to “−1”. The zero cross detection method is a method of detecting the timing (zero cross point) passing through this zero, estimating the center of the symbol therefrom, and setting the sampling timing as the symbol timing. For example, in the case of quadruple sampling, the center of the symbol is estimated by regarding the sampling timing two or three times after the zero cross point as the center of the symbol.

  This zero-cross detection method is useful when a Gaussian filter in which the zero-cross point does not fluctuate or a Nyquist filter with a large roll-off rate α is used as a filter of the receiving device. However, when a Nyquist filter with a small roll-off rate α is used, fluctuations occur at the zero cross point due to the occurrence of jitter, as shown in FIG. Therefore, the zero cross point cannot be detected correctly, and as a result, stable symbol synchronization may not be obtained.

  As symbol synchronization in the case where such a Nyquist filter with a small roll-off rate α is mounted, there is a method that uses signal dispersion of sample points as shown in Non-Patent Document 1 and FIG. Here, in order to facilitate understanding, it is assumed that the binary optimum sampling level is known in advance. The signal is oversampled, a plurality of samples are selected at a certain interval from the signal at symbol intervals, the square error from the optimum sampling position is calculated for each sample, and the sum is calculated. Thus, if the sum of the square errors is calculated for each oversampling, the sampling timing at which the sum of squares is minimized can be determined as the optimum timing.

  However, in wireless transmission, the level of the received signal constantly fluctuates due to changes in the surrounding environment (such as movement of transmitters and receivers and movement of people), and the optimal timing of the signal does not always come to the expected level. . For this reason, it is necessary to take measures such as estimating the optimum sampling level to be expected and appropriately changing it, and there is a disadvantage that the circuit becomes complicated.

CQ Publishing Communication System Design by Digital Signal Processing Yoshikazu Nishimura

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has a simple configuration, and a synchronization system and a receiving apparatus that can accurately establish symbol synchronization without being affected by amplitude levels and zero cross point jitter. The purpose is to provide.

  In order to achieve the above object, the synchronization system of the present invention includes a 3-bit extraction unit that sequentially extracts three consecutive bits while shifting one bit at a time from the demodulated signal, and a maximum absolute value of the median value among the extracted three bits. And a synchronization establishment unit for setting the sampling timing of the median determined to be the maximum as the symbol synchronization timing.

  In this invention, it is preferable to further include an oversampling unit that oversamples the baseband signal and a demodulation unit that demodulates the baseband signal oversampled by the oversampling unit.

  In the present invention, a code determination unit that determines a 3-bit code extracted by the 3-bit extraction unit is provided, and the median determination unit determines that all the 3-bit codes are the same by the code determination unit. In this case, it is preferable to determine that the absolute value of the median is the maximum.

  In the present invention, a code determination unit that determines a 3-bit code extracted by the 3-bit extraction unit is provided, and the synchronization establishment unit is determined by the code determination unit that all the 3-bit codes are the same. In this case, it is preferable to set the sampling timing of the median value to the symbol synchronization timing.

  In this invention, it comprises a threshold value comparison unit that compares the median value with a predetermined threshold value, and the median value determination unit, when the threshold value comparison unit determines that the median value is greater than or equal to the threshold value, It is preferable to determine that the absolute value of the value is maximum.

  In the present invention, a threshold value comparison unit that compares a median value determined to be the maximum by the median value determination unit with a predetermined threshold value, and the synchronization establishment unit is determined to be the maximum by the threshold value comparison unit. When it is determined that the median value is equal to or greater than the threshold value, it is preferable to set the sampling timing of the median value as the symbol synchronization timing.

  In the present invention, a timing counting unit that counts a sampling timing at which the absolute value of the median value is maximum is provided, and the synchronization establishing unit is configured such that the count number by the timing counting unit is equal to or greater than a predetermined count threshold value. It is preferable to update the symbol synchronization timing.

  In the present invention, a zero cross detection unit that detects that the demodulated signal demodulated by the demodulation unit crosses zero, and when the zero cross detection unit detects that the demodulated signal crosses zero, the timing count unit is The first predetermined value is preferably subtracted from the count number of the sampling timing crossing the zero.

  In the present invention, a zero cross detection unit that detects that the demodulated signal demodulated by the demodulation unit crosses zero, and when the zero cross detection unit detects that the demodulated signal crosses zero, the timing count unit is It is preferable to add a second predetermined value to the count number of the sampling timing separated by a predetermined time from the sampling timing crossing the zero.

  In the present invention, a three-symbol code determination unit that determines a code of three consecutive symbols is provided, and the median value determination unit has positive, negative, positive or negative signs of the three symbols determined by the three-symbol code determination unit. In this case, it is preferable that the 3-bit extraction unit sequentially extracts consecutive 3 bits in the central symbol of the consecutive 3 symbols.

  In the present invention, there is provided a count number comparison unit for comparing the count number counted by the timing count unit, and the upper two samplings having a large number of counts compared with the currently set symbol synchronization timing by the count number comparison unit If the difference between the count numbers is less than or equal to a predetermined value in the upper two sampling timings with a large number of counts compared by the count number comparison unit, the synchronization establishment unit It is preferable not to update the symbol synchronization timing.

  In the present invention, a reference setting unit for setting a reference value for determining the code of the demodulated signal is provided, and the reference setting unit calculates an intermediate value of the demodulated signal and sets the intermediate value as a reference value. It is preferable.

  The receiving apparatus of the present invention includes the synchronization system, receives a baseband signal in which a synchronization establishment signal transmitted from a transmitter is inserted, establishes symbol synchronization, and receives a payload signal transmitted thereafter. It is possible to make it possible.

  In the present invention, it is preferable that a PLL circuit that corrects a phase shift is further provided at a subsequent stage of the synchronization system.

  In the present invention, a PSK modulation / demodulation unit is separately provided for transmission / reception using a π / 4 shift DQPSK as a modulation / demodulation method, and the synchronization establishment signal is also transmitted / received when the modulation / demodulation method uses π / 4 shift DQPSK. Transmission / reception is preferably performed by an 8PSK modulation / demodulation method.

  In the present invention, it is preferable that a baseband signal in which the synchronization establishment signal is periodically inserted is transmitted from the transmitter for data having a frame length of a predetermined length or more.

  In this invention, it is preferable that the synchronization establishment signal transmitted from the transmitter is configured such that each symbol value does not continue for a predetermined period with the same code.

  According to the present invention, the sampling timing of the median value determined to have the maximum absolute value is set as the symbol synchronization timing. Therefore, since there is no need to cope with fluctuations in the amplitude level, it is possible to construct a receiving device with a simple configuration compared to a conventional receiving device. Even when a Nyquist filter with a small roll-off rate α is mounted, symbol synchronization can be established with high accuracy without being affected by jitter.

The block diagram which shows the structure of the synchronous system by one Embodiment of this invention, and a receiver provided with the same. The flowchart which shows operation | movement of the system. The figure which shows the relationship between the operation | movement of the system and the demodulation signal output from a demodulation part. The block diagram which shows the structure of the modification of the said synchronous system. The flowchart which shows operation | movement of the modification. An example of a waveform of a demodulated signal for which the modification effectively functions will be shown. The block diagram which shows the structure of another modification of the said synchronous system. The flowchart which shows operation | movement of the modification. An example of a waveform of a demodulated signal for which the modification effectively functions will be shown. The block diagram which shows the structure of another modification of the said synchronous system. The flowchart which shows operation | movement of the modification. 12 is a flowchart showing details of operations of # 5 to # 13 in FIG. The block diagram which shows the structure of another modification of the said synchronous system. The flowchart which shows operation | movement of the modification. An example of a waveform of a demodulated signal for which the modification effectively functions will be shown. The block diagram which shows the structure of another modification of the said synchronous system. The flowchart which shows operation | movement of the modification. An example of a waveform of a demodulated signal for which the modification effectively functions will be shown. The block diagram which shows the structure of another modification of the said synchronous system. The flowchart which shows operation | movement of the modification. The figure which shows an example of the count number counted by the timing count part of the modification, and compared with a count number comparison part. The block diagram which shows the structure of another modification of the said synchronous system. The flowchart which shows operation | movement of the modification. An example of a waveform of a demodulated signal for which the modification effectively functions will be shown. The block diagram which shows the structure of another modification of the said receiver. The figure which shows the effect by which the period of a synchronous clock timing is kept constant by the modification. The figure which shows an example of the modulation / demodulation system which concerns on another modification of the said receiver. The figure which shows an example of the flame | frame structure transmitted from a transmitter in the further another modification of the said receiver. The figure which shows an example of the signal waveform conventionally used in order to establish symbol synchronization in a receiver. The figure which shows the relationship between a roll-off rate and an eye pattern. The figure which shows the establishment method of the symbol synchronization in the conventional receiver.

(First embodiment)
A synchronization system according to a first embodiment of the present invention and a receiving apparatus including the same will be described with reference to the drawings. FIG. 1 shows the configuration of the receiving apparatus. The receiving apparatus is an apparatus that establishes symbol synchronization and frame synchronization using a synchronization establishment signal and a unique word included in a preamble signal transmitted from a transmitter, and receives a payload signal transmitted thereafter. The synchronization system is a system that is incorporated in a receiving apparatus, establishes symbol synchronization with respect to a received signal, and enables establishment of frame synchronization and reception of a payload signal. The synchronization system includes an oversampling unit 20, a demodulation unit 1, a 3-bit extraction unit 2, a median determination unit 3, a synchronization establishment unit 4, and the like. The oversampling unit 20 oversamples the input baseband signal at a cycle shorter than the symbol cycle. The baseband signal is obtained by down-converting the RF signal received by the RF signal receiving unit 30 of the receiving device. The demodulator 1 demodulates the baseband signal sampled by the oversampling unit 20. The 3-bit extraction unit 2 sequentially extracts three consecutive bits from the data sequence of the demodulated signal output from the demodulation unit 1. The median value determination unit 3 compares the absolute value of the 3-bit data string extracted by the 3-bit extraction unit 2 (that is, the absolute value of the central bit (median value) with the absolute value of the both end bits), thereby It is determined whether or not the absolute value of the bit is the maximum. The synchronization establishment unit 4 sets the sampling timing of the median value determined by the median value determination unit 3 to have the maximum absolute value as the symbol synchronization timing.

  FIG. 2 shows the operation of the synchronization system of the embodiment. FIG. 3 shows the relationship between the demodulated signal output from the demodulator 1 and the operation of the system. The waveform in FIG. 3 shows a demodulated signal, and shows a case where sampling is performed at a frequency four times the frequency of one symbol, that is, a case where sampling is performed four times at a timing of timing 0, 1, 2, 3 for one symbol. ing. The timing at which the demodulated signal is sampled corresponds to the timing at which the baseband signal is sampled by the oversampling unit. In addition, three points surrounded by a broken line indicate a 3-bit data string extracted in order by the 3-bit extraction unit 2. As shown in FIGS. 3A to 3D, the 3-bit extraction unit 2 sequentially extracts three consecutive bits while shifting one bit at a time from the sampled demodulated signal data string. Then, the median determination unit 3 searches for a case where the absolute value of the median is the maximum (that is, the median is a peak or a bottom).

  In FIG. 2, the RF signal received by the receiving unit is down-converted and input to the synchronization system as a baseband signal. The input baseband signal is sampled by the oversampling unit, and when the 1-bit equivalent is input to the demodulation unit 1 (# 1), it is demodulated by the demodulation unit 1 (# 2). Then, the 3-bit extraction unit 2 sequentially extracts three consecutive bits of the demodulated signal (# 3), and the median value determination unit 3 compares the extracted 3-bit absolute values (# 4).

  As a result, as shown in FIG. 3 (a), when a 3-bit frame surrounded by a broken line, that is, a data string of timings 0, 1, and 2, is extracted, the median value (the timing 1 value of the second bit) The absolute value of is not the maximum (NO in # 5) and returns to # 1. After that, as shown in FIG. 3B, the 3-bit extraction unit 2 sequentially extracts the next consecutive 3-bit data sequence while shifting by 1 bit from the 3-bit data sequence extracted in (a). . The same applies to FIGS. 3C and 3D. In this way, a continuous 3-bit data string is sequentially extracted while shifting by 1 bit. Then, when the 3 bits surrounded by a broken line in FIG. 3D, that is, the data string of timings 3, 0, 1 is extracted, the absolute value of the median (the timing 0 value of the second bit) becomes the maximum. (YES in # 5). In this case, the synchronization establishment unit 4 sets the sampling timing of the median value, that is, the timing 0 as the symbol synchronization timing (# 6). When the symbol synchronization timing is established in this way, a unique word can be detected and frame synchronization can be achieved, and a payload signal can be received.

  According to the synchronization system of this embodiment, the sampling timing of the median value determined to have the maximum absolute value is set as the symbol synchronization timing. Therefore, since it is not necessary to cope with fluctuations in the amplitude level, it is possible to construct a system with a simple configuration as compared with the conventional synchronous system. Further, even when a Nyquist filter with a small roll-off rate α is mounted, it is possible to suppress fluctuation of the zero cross point due to the influence of jitter, so that symbol synchronization can be established with high accuracy.

(Modification)
FIG. 4 shows a configuration of a modified example of the synchronization system according to the embodiment. The synchronization system of this modification further includes a code determination unit 5 with respect to the synchronization system shown in FIG. The code determination unit 5 determines the 3-bit code extracted by the 3-bit extraction unit 2.

  FIG. 5 shows the operation of the synchronization system according to this modification. FIG. 6 shows an example of a waveform of a demodulated signal in which the synchronization system according to this modification effectively functions. When the demodulated signal has a waveform as shown in FIG. 6 due to the influence of noise or the like, the timing 1 is inappropriate as the symbol synchronization timing. This is because, when the sampling magnification is sufficiently high, the sign is not inverted between the symbol synchronization timing and the adjacent timing in normal communication that is not affected by noise or the like. However, when 3 bits surrounded by a broken line, that is, a data string of timings 0, 1, and 2 are extracted, the median determination unit 3 determines that the value at the central timing 1 is the peak or the bottom, and the symbol synchronization timing. May be set incorrectly. Therefore, in this modification, only when the code determination unit 5 determines that all of the extracted 3-bit codes are the same, the median determination unit 3 determines that the absolute value of the median is the maximum. I decided to judge.

  That is, in FIG. 5, when the 3-bit extraction unit 2 sequentially extracts three consecutive bits of the demodulated signal (# 3), the code determination unit 5 determines the 3-bit code extracted by the 3-bit extraction unit 2 (# 11). If the 3-bit codes are the same (YES in # 11), median value determination unit 3 compares the median values and determines whether the absolute value is the maximum (# 4, # 5). On the other hand, if all the 3-bit codes are not the same (NO in # 11), the process returns to # 1. Other operations are the same as those of the modification shown in FIG.

  According to this modified example, whether or not the median value determination unit 3 has the maximum absolute value of the median value only when the code determination unit 5 determines that all the extracted 3-bit codes are the same. Determine. Therefore, when there is a possibility that the sign is inverted between 3 bits extracted due to the influence of noise or the like and the symbol synchronization timing is set erroneously, the comparison of absolute values by the median value determination unit 3 is not executed. It is possible to suppress erroneous detection of symbol synchronization timing.

  In this modification, the synchronization establishment unit 4 sets the median sampling timing as the symbol synchronization timing only when the code determination unit 5 determines that all the extracted 3-bit codes are the same. (# 6) may be configured. In this case, the processes of # 4 and # 5 are executed subsequent to # 3, and the process of # 11 is executed in the case of YES at # 5 and shifts to # 6.

(Modification)
FIG. 7 shows a configuration of a modified example of the synchronization system according to the embodiment. The synchronization system of this modification further includes a threshold comparison unit 6 with respect to the synchronization system shown in FIG. The threshold comparison unit 6 compares the 3-bit median value with a predetermined threshold value.

  FIG. 8 shows the operation of the synchronization system according to this modification. FIG. 9 shows an example of a waveform of a demodulated signal for which the synchronization system according to this modification effectively functions. When the demodulated signal has a waveform as shown in FIG. 9 due to the influence of noise or the like, the timing 2 is not the bottom value of the original demodulated signal but is inappropriate as the symbol synchronization timing. However, when 3 bits surrounded by a broken line, that is, a data string of timings 1, 2, and 3 are extracted, the median determination unit 3 determines that the value at the central timing 2 is the bottom value, and the symbol synchronization timing May be set incorrectly. Therefore, in this modification, the median value determination unit 3 determines that the median absolute value is the maximum only when the threshold value comparison unit 6 determines that the 3-bit median value is equal to or greater than a predetermined threshold value. I decided to judge.

  That is, in FIG. 8, the code determination unit 5 determines the 3-bit code extracted by the 3-bit extraction unit 2, and if both of the 3-bit codes are the same (YES in # 11), the threshold comparison unit 6 The absolute value of the median is compared with the threshold (# 12). Further, if the absolute value of the median is equal to or greater than the threshold (YES in # 12), median determination unit 3 compares the median and determines whether the absolute value is the maximum (# 4, # 5). If the absolute value of the median is less than the threshold value (NO in # 12), the process returns to # 1. Other operations are the same as those of the modification shown in FIG.

  According to this modification, only when the threshold comparison unit 6 determines that the 3-bit median is equal to or greater than the threshold, the median determination unit 3 determines whether or not the absolute value of the median is maximum. To do. Therefore, when there is a possibility that the peak or bottom timing of the demodulated signal generated near zero due to the influence of noise or the like is erroneously set as the symbol synchronization timing, the absolute value comparison by the median value determination unit 3 is not executed. . Thereby, the erroneous detection of the symbol synchronization timing can be further suppressed.

  In this modified example, when # 11 in FIG. 8 is skipped and the 3-bit extraction unit 2 sequentially extracts three consecutive bits of the demodulated signal (# 3), the threshold comparison unit 6 determines the absolute value of the median value. And the threshold value may be compared (# 12). Also, only when the threshold comparison unit 6 determines that the 3-bit median is equal to or greater than the threshold, the synchronization establishment unit 4 sets the median sampling timing to the symbol synchronization timing (# 6). May be. In this case, the processes of # 4 and # 5 are executed subsequent to # 11, and the process of # 12 is executed in the case of YES at # 5 and proceeds to # 6.

(Modification)
FIG. 10 shows a configuration of a modified example of the synchronization system according to the embodiment. The synchronization system of this modified example further includes a timing count unit 7 with respect to the synchronization system shown in FIG. The timing count unit 7 counts the sampling timing at which the absolute value of the median value is maximum.

  FIG. 11 shows the operation of the synchronization system according to this modification. FIG. 12 shows details of the process of # 13 in FIG. When median determination unit 3 determines that the absolute value of the median is maximum (YES in # 5), timing counting unit 7 counts up the sampling timing at which the absolute value of the median is determined to be maximum (# 13). ). In # 13, as shown in FIG. 12, when the maximum value is confirmed at timing 0 (YES in # 61), the count at timing 0 is incremented, that is, incremented by 1 (# 62). When the maximum value is confirmed at the timing 1, 2 or 3 (YES at # 63, # 65 or # 67), the count at the timing 1, 2 or 3 is incremented by 1 (# 64, # 66 or # 68). ). Then, the processes of # 1 to # 13 in FIG. 11 are repeatedly executed until the count number at any timing becomes equal to or greater than the predetermined count threshold (NO in # 14). When the count number is equal to or greater than a predetermined count threshold value (YES in # 14), synchronization establishment unit 4 sets the timing as the symbol synchronization timing (# 15). Thereafter, the counter is reset (# 16). Other operations are the same as those of the modification shown in FIG.

  According to this modification, the symbol synchronization timing is updated when the count number of the timing count unit 7 is equal to or greater than a predetermined count threshold. Thereby, the timing at which the peak or bottom of the demodulated signal is detected is statisticalized, and it is possible to prevent erroneously setting the timing at which the peak or bottom occurs accidentally as the symbol synchronization timing.

(Modification)
FIG. 13 shows a configuration of a modified example of the synchronization system according to the embodiment. The synchronization system of this modified example further includes a zero cross detection unit 8 with respect to the synchronization system shown in FIG. The zero-cross detector 8 detects that the demodulated signal demodulated by the demodulator 1 crosses zero. It can be detected that the demodulated signal crosses zero by, for example, comparing the codes of the three end bits (first bit and third bit) extracted by the 3-bit extraction unit 2. When the signs of the both end bits are different, it can be considered that the demodulated signal crosses zero.

  FIG. 14 shows the operation of the synchronization system according to this modification. FIG. 15 shows an example of a waveform of a demodulated signal for which the synchronization system according to this modification effectively functions. As shown in FIG. 15, the demodulated signal oscillates repeatedly alternately in the positive direction or the negative direction around zero. Therefore, when the demodulated signal is normal, the peak or bottom of the demodulated signal is generated at a timing away from the timing crossing zero, and the peak or bottom of the demodulated signal is generated at a timing near the timing crossing zero. Absent. Therefore, in this modification, the symbol synchronization timing is set in consideration of the timing of crossing zero.

  That is, in # 11 shown in FIG. 14, if all the three-bit codes are not the same (NO in # 11), the process proceeds to # 21 and the codes of both end bits are compared. If the signs of both end bits are the same (YES in # 21), the process returns to # 1. When the signs of the bits at both ends are different (NO in # 21), the timing count unit 7 subtracts the first predetermined value from the number of sampling timings crossing zero (# 22). Further, the second predetermined value is added to the number of counts of the sampling timing separated by a predetermined time from the sampling timing crossing zero (# 23), and the process returns to # 1.

  In addition, in # 22 and # 23, the sampling timing crossing zero is described, but it is considered that the sampling timing and the timing at which the demodulated signal crosses zero do not exactly match. Therefore, when the timings do not exactly match, the timing immediately before and / or immediately after the sampling timing crosses zero is handled as the sampling timing crossing zero. Other operations are the same as those of the above-described modification shown in FIG. In this modification, when the signs of both end bits are different (NO in # 21), the processes of # 22 and # 23 are executed. However, either one of the processes is executed. Also good. Further, since the sampling timing crossing zero may lack accuracy due to the occurrence of jitter, the first predetermined value may be set smaller than the second predetermined value.

  According to this modification, since the symbol synchronization timing is set in consideration of the timing crossing zero, it is possible to further prevent the symbol synchronization timing from being set to an incorrect timing. In addition, since the count of the second predetermined value is taken into account, the count number of the timing counter 7 reaches the predetermined value or more in a short time, so that the symbol synchronization timing can be updated frequently as necessary.

(Modification)
FIG. 16 shows a configuration of a modified example of the synchronization system according to the embodiment. The synchronization system according to this modification further includes a three-symbol code determination unit 9 with respect to the synchronization system shown in FIG. The 3-symbol code determination unit 9 determines the code of 3 consecutive symbols.

  FIG. 17 shows the operation of the synchronization system according to this modification. FIG. 18 shows an example of a waveform of a demodulated signal in which the synchronization system according to this modification effectively functions. As shown in FIG. 18A, when the sign of the symbol represented by the demodulated signal alternately repeats negative and positive, the timing of the peak or bottom of the demodulated signal coincides with the original symbol synchronization timing. However, as shown in (b), when the sign of the symbol of the demodulated signal is positive and negative and part of the code is continuous, the demodulated signal peak may occur at an intermediate timing of the original symbol synchronization timing. Or a peak may not occur at the correct symbol timing. For this reason, there is a possibility that the symbol synchronization timing is set erroneously. Therefore, in this modification, the 3-symbol determination unit 9 determines the code of 3 consecutive symbols, and the 3-bit extraction unit 2 is operated only when the code of the 3 symbols is positive / negative / positive / negative / positive / negative. did.

  That is, in # 2 shown in FIG. 17, when the baseband signal is demodulated by the demodulator 1, the 3-symbol code determination unit 9 determines the code of 3 consecutive symbols. If the three-symbol code determined by the three-symbol code determination unit is positive, negative, positive or negative (YES in # 31), the 3-bit extraction unit 2 calculates 3 consecutive bits in the center symbol of the 3 consecutive symbols. Extract in order (# 3). Other operations are the same as those of the above-described modification shown in FIG.

  According to the present modification, the configuration is such that the 3-bit extraction unit 2, the median value determination unit 3 and the like operate when the signs of three consecutive symbols are positive, negative, positive, negative, or positive. If the symbols have the same sign, the peak or bottom of the demodulated signal is not detected. Therefore, for example, in the demodulated signal shown in FIG. 18B, timing 2 is not detected as a peak, and it is possible to further prevent the symbol synchronization timing from being set to an incorrect timing.

(Modification)
FIG. 19 shows a configuration of a modified example of the synchronization system according to the embodiment. The synchronization system of this modified example further includes a count number comparison unit 10 with respect to the synchronization system shown in FIG. The count number comparison unit 10 compares the count number counted by the timing count unit 7 for each sampling timing.

  FIG. 20 shows the operation of the synchronization system according to this modification. FIG. 21 shows an example of the count number counted by the timing count unit 7 and compared by the count number comparison unit 10. In a synchronization system, there is a possibility that missing bits or more bits of the frame may occur due to the update of the symbol synchronization timing, so it may be preferable not to update the symbol synchronization timing unnecessarily. For example, as shown in FIG. 21, even when the timing 0 is set as the current symbol synchronization timing and the count number of the timing 3 reaches the count threshold, the difference from the timing 0 is This is the case when it is sufficiently close. In this case, there is no substantial difference between the timing 0 and the timing 3 as judged from the accuracy of the count by the timing count unit 7, and the frame synchronization is sufficiently established even at the timing 0 and the payload signal Can be received. Therefore, this modification operates as follows on the assumption that the currently set symbol synchronization timing is one of the upper two sampling timings with a large number of counts. That is, at the upper two sampling timings, the symbol synchronization timing is not updated when the difference in the count number is equal to or smaller than a predetermined count difference threshold, and the occurrence of missing bits is suppressed.

  In FIG. 20, even if the count number is equal to or greater than the predetermined count threshold value (YES in # 14), if the difference between the count numbers is less than the predetermined count difference threshold value in the upper two sampling timings (YES in # 32), The counter number is reset and the process returns to # 1. In this case, the symbol synchronization timing is not updated. On the other hand, if the count difference is equal to or greater than the predetermined count difference threshold (NO in # 32), the synchronization establishing unit 4 is operated to update the symbol synchronization timing (# 15). Other operations are the same as those of the above-described modification example shown in FIG.

  According to this modification, the symbol synchronization timing is not updated if the difference in the number of counts is less than a predetermined count difference threshold at the two upper sampling timings. As a result, occurrence of missing bits and increase in bits due to unnecessary update of symbol synchronization timing can be reduced, and occurrence of reception errors can be reduced.

(Modification)
FIG. 22 shows a configuration of a modified example of the synchronization system according to the embodiment. The synchronization system of this modification further includes a reference setting unit 11 with respect to the synchronization system shown in FIG. The reference setting unit 11 sets a reference value for determining the code of the demodulated signal.

  FIG. 23 shows the operation of the synchronization system according to this modification. FIG. 24 shows an example of a waveform of a demodulated signal for effectively functioning the synchronization system according to the present modification. When the RF signal receiving unit 30 performs down-conversion by a method such as direct conversion, a DC offset occurs, and when a DC component is added to the demodulated signal, the DC offset may be positive or negative as shown in FIG. Therefore, in this modification, the reference setting unit 11 is configured to set a reference value for determining the code of the demodulated signal in accordance with the DC component, that is, to correct the code from the initial zero, and to accurately determine the code. ing.

  That is, in # 2 shown in FIG. 23, when the baseband signal is demodulated by the demodulator 1, the reference setting unit 11 calculates an average value of a predetermined number of bits and sets a reference value for determining the sign of the demodulated signal. Set (# 41), then proceed to # 31. Accordingly, the code determination at # 11 is performed by comparing the extracted bit value with the corrected reference value. Other operations are the same as those of the above modification shown in FIG.

  According to this modification, the reference setting unit 11 optimizes the reference value for determining the sign of the demodulated signal. As a result, the influence of the DC offset of the demodulated signal can be reduced and the code can be determined accurately, so that the accuracy of symbol synchronization can be maintained satisfactorily.

(Modification)
FIG. 25 shows a configuration of a modified example of the receiving apparatus according to the embodiment. The receiver of this modification further includes a PLL (Phase-locked loop) circuit 13, a voltage control oscillator (VCO) 14, and a synchronization establishment unit 15 with respect to the synchronization system 12 equivalent to the receiver shown in FIG. Prepare. The PLL circuit 13 is provided in the subsequent stage of the synchronization system 12, generates a new output signal synchronized with the phase of the input signal, and corrects a slight phase shift. The voltage control oscillator 14 adjusts the oscillation frequency according to the voltage input from the phase comparator of the PLL circuit 13. The voltage control oscillator 14 may be incorporated in the PLL circuit 13. The synchronization establishment unit 15 establishes synchronization with the signal output from the voltage control transmitter 14.

  26A shows the synchronous clock timing when the PLL circuit 13 is not used, and FIG. 26B shows the synchronous clock timing when the PLL circuit 13 is used. As shown in FIG. 26A, when the PLL circuit 13 is not used, the period of the synchronous clock timing may be slightly shifted due to the influence of noise or the like. On the other hand, when the PLL circuit 13 is used as shown in FIG. 26B, the period of the synchronous clock timing can be kept constant by the newly generated output signal. In particular, fluctuations in symbol timing due to jitter and noise when the oversampling ratio is high, for example, 64 times the symbol clock, can be reduced, and stable symbol synchronization timing can be maintained.

(Modification)
FIG. 27 illustrates an example of a modulation / demodulation method according to a modification of the reception device according to the embodiment. The receiving apparatus is configured to be capable of transmitting and receiving with a corresponding transmitting apparatus using a π / 4 shift DQPSK modulation / demodulation method. In the π / 4 shift DQPSK modulation system, as shown in FIG. 27 (a), the movement destinations from (1, 0) and (-1, 0) are limited to those indicated by black dots, and (1, 0) Cannot move from (-1, 0) to (-1, 0) or from (-1, 0). On the other hand, in the 8PSK modulation system, as shown in FIG. 27 (b), it can move from (1, 0) to (-1, 0) or from (-1, 0) to (1,0). it can. As a result, the amplitude level of the signal can be increased.

  Therefore, in the present modification, in order to transmit / receive the synchronization establishment signal using the 8PSK modulation / demodulation method even for transmission / reception using π / 4 shift DQPSK as the modulation / demodulation method of the payload signal, the transmission apparatus uses the 8PSK modulation unit. The receiving apparatus further includes an 8PSK demodulator. That is, the receiving apparatus includes a π / 4 shift DQPSK demodulator for demodulating the payload signal and an 8PSK demodulator for demodulating the establishment signal.

  According to this modification, even when transmitting / receiving a payload signal using the π / 4 shift DQPSK modulation / demodulation method, the synchronization establishment signal can be transmitted / received using the 8PSK modulation / demodulation method. Can be increased. As a result, even when the amplitude level of the received signal is reduced as a whole, the peak or bottom of the demodulated signal can be accurately detected, and the accuracy of symbol synchronization can be maintained satisfactorily.

(Modification)
FIG. 28 illustrates an example of a frame configuration transmitted from the transmission device in the modification of the reception device according to the embodiment. 28A shows a normal frame configuration, and FIG. 28B shows a frame configuration in the present modification. As shown in FIG. 28A, in a normal frame configuration, one frame is configured by a preamble signal including a synchronization establishment signal and a payload signal as data. In this case, if the data string constituting the payload signal becomes longer in one frame, there is a possibility that synchronization may not be achieved as the data string is moved backward. Therefore, in this modified example, as shown in FIG. 28 (b), a signal for establishing synchronization is periodically inserted into data having a frame length of a predetermined length or more and transmitted from the transmission device, It is comprised so that it can receive with a receiver.

  According to this modification, the receiving device that receives the frame transmitted from the transmitting device periodically checks and corrects the symbol synchronization timing by using the synchronization establishment signal that is periodically inserted. Can do. As a result, even when a data string having a long frame length that may cause a shift in symbol synchronization timing is received, correct symbol synchronization timing can be maintained.

  The present invention is not limited to the configuration of the above-described embodiment, and at least three consecutive bits are sequentially extracted from the demodulated signal while being shifted one bit at a time, and it is determined that the absolute value of the median is the maximum. What is necessary is just to be comprised so that a synchronous timing may be established. Further, the present invention can be widely applied to establishment of symbol synchronization timing in both wired and wireless communications. In addition, the synchronization establishment signal transmitted from the transmission apparatus is configured so that each symbol value does not continue for a predetermined period with the same code (see FIG. 18A), thereby making it possible to prevent erroneous detection of symbol synchronization timing. This can be further prevented. In addition, a synchronization system and a reception device that appropriately combine the features of the above-described modifications may be used.

DESCRIPTION OF SYMBOLS 1 Demodulation part 2 3 bit extraction part 3 Median value determination part 4 Synchronization establishment part 5 Code determination part 6 Threshold comparison part 7 Timing count part 8 Zero cross detection part 9 3 Symbol code determination part 10 Count number comparison part 11 Reference setting part 13 PLL circuit

Claims (17)

  A 3-bit extraction unit that sequentially extracts three consecutive bits while shifting one bit at a time from the demodulated signal, a median value determination unit that determines that the absolute value of the median value is maximum among the extracted 3 bits, A synchronization system comprising a synchronization establishment unit that sets a sampling timing of a median value determined to be a symbol synchronization timing.   The synchronization system according to claim 1, further comprising: an oversampling unit that oversamples a baseband signal; and a demodulation unit that demodulates the baseband signal oversampled by the oversampling unit. A code determination unit for determining a 3-bit code extracted by the 3-bit extraction unit;
The median value determination unit determines that the absolute value of the median value is maximum when the code determination unit determines that all of the three-bit codes are the same. The synchronization system according to claim 1 or 2. A code determination unit for determining a 3-bit code extracted by the 3-bit extraction unit;
The synchronization establishment unit sets the sampling timing of the median value to a symbol synchronization timing when the code determination unit determines that all of the 3-bit codes are the same. The synchronization system according to claim 2. A threshold comparison unit that compares the median with a predetermined threshold;
The median value determination unit determines that the absolute value of the median value is maximum when the threshold value comparison unit determines that the median value is equal to or greater than the threshold value. The synchronization system according to claim 4. A threshold comparing unit that compares the median determined to be the maximum by the median determining unit with a predetermined threshold;
The synchronization establishment unit sets a sampling timing of the median value to a symbol synchronization timing when the median value determined to be the maximum by the threshold value comparison unit is determined to be equal to or greater than the threshold value. The synchronization system according to any one of claims 1 to 4. A timing counting unit that counts a sampling timing at which the absolute value of the median is maximum;
7. The symbol synchronization timing according to claim 1, wherein the synchronization establishment unit updates the symbol synchronization timing when a count number by the timing count unit is equal to or greater than a predetermined count threshold value. Synchronization system. A zero-cross detector that detects that the demodulated signal demodulated by the demodulator crosses zero;
When it is detected by the zero cross detector that the demodulated signal crosses zero,
The synchronization system according to claim 7, wherein the timing count unit subtracts a first predetermined value from a count number of sampling timings crossing the zero. A zero-cross detector that detects that the demodulated signal demodulated by the demodulator crosses zero;
When it is detected by the zero cross detector that the demodulated signal crosses zero,
9. The synchronization system according to claim 7, wherein the timing count unit adds a second predetermined value to a count number of sampling timings separated by a predetermined time from a sampling timing crossing the zero. A three-symbol code determination unit that determines a code of three consecutive symbols;
The median value determination unit is configured such that the 3-bit extraction unit continues in the center symbol of the three consecutive symbols when the sign of the three symbols determined by the three-symbol code determination unit is positive or negative or positive / negative. The synchronization system according to any one of claims 1 to 4, wherein three bits are extracted in order. A count number comparison unit for comparing the count number counted by the timing count unit;
The currently set symbol synchronization timing is one of the upper two sampling timings having a large number of counts compared by the count number comparison unit, and the difference between the count numbers is less than or equal to a predetermined value at the upper two sampling timings 11. The synchronization system according to claim 7, wherein the synchronization establishment unit does not update the symbol synchronization timing. A reference setting unit for setting a reference value for determining the code of the demodulated signal;
The synchronization system according to any one of claims 1 to 11, wherein the reference setting unit calculates an intermediate value of the demodulated signal and sets the intermediate value as the reference value. A synchronization system according to any one of claims 1 to 12, comprising:
A receiving apparatus comprising: a baseband signal into which a synchronization establishment signal transmitted from a transmitter is inserted; symbol synchronization is established; and a payload signal transmitted thereafter can be received.   The receiving apparatus according to claim 13, further comprising a PLL circuit that corrects a phase shift at a subsequent stage of the synchronization system. For transmission / reception using a π / 4 shift DQPSK modulation / demodulation method, a PSK modulation / demodulation unit is provided separately.
15. The receiving apparatus according to claim 13, wherein the synchronization establishment signal is transmitted / received by an 8PSK modulation / demodulation method even when the modulation / demodulation method uses π / 4 shift DQPSK.   16. The baseband signal in which the synchronization establishment signal is periodically inserted is transmitted from the transmitter for data having a frame length greater than or equal to a predetermined length. The receiving device according to one item.   17. The synchronization establishment signal transmitted from the transmitter is configured such that each symbol value is not consecutive for a predetermined period with the same code. Receiver.

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