CN110247751B - Method, device and storage medium for Quadrature Amplitude Modulation (QAM) signal bit synchronization - Google Patents
Method, device and storage medium for Quadrature Amplitude Modulation (QAM) signal bit synchronization Download PDFInfo
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- CN110247751B CN110247751B CN201811359474.XA CN201811359474A CN110247751B CN 110247751 B CN110247751 B CN 110247751B CN 201811359474 A CN201811359474 A CN 201811359474A CN 110247751 B CN110247751 B CN 110247751B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
Abstract
The invention discloses a method, a device and a storage medium for Quadrature Amplitude Modulation (QAM) signal bit synchronization, which are used for solving the technical problem of higher error rate of a demodulated QAM signal in the prior art. The method comprises the following steps: the two interpolation filters are used for resampling the input signal according to an interpolation base point and a first fractional interval of a previous symbol period in each symbol period, obtaining a resampled signal in each symbol period and sending the resampled signal to the clock error detector; the numerical control oscillator is connected between the two interpolation filters and used for calculating a second fractional interval of the current symbol period and providing an interpolation base point for the two interpolation filters; the fractional interval jump detector is connected between the two interpolation filters and used for detecting whether discontinuous sampling points occur in the first fractional interval; if so, the second fractional interval is used to correct the erroneous interpolation of the input signal inserted in the first fractional interval to obtain a new resample point.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method, an apparatus, and a storage medium for bit synchronization of quadrature amplitude modulation QAM signals.
Background
In wireless communication, after an all-digital receiver receives a baseband signal, a Quadrature Amplitude Modulation (QAM) modem in the receiver generally needs to demodulate a signal transmitted by a transmitter.
In the process of transmitting a baseband signal from a transmitter to a receiver, due to signal delay and interference of an interference signal, an original clock of the baseband signal is changed after the baseband signal is received, so in QAM baseband demodulation, a bit synchronization algorithm is usually required to be adopted to recover the original clock from the baseband signal, and then a correct signal is obtained. The bit synchronization algorithm typically employs a Gardner algorithm independent of the carrier Phase, which belongs to a non-data aided feedback loop, and is equally applicable to multilevel QAM signals, although the derivation of the Gardner algorithm is based on 2-level signals (Binary Phase Shift Keying (BPSK)/Quadrature Phase Shift Keying (QPSK)).
In the Gardner algorithm, an interpolation filter interpolates a resampling signal according to an interpolation base point and a fractional interval given by a Numerical Control Oscillator (NCO), and after interpolation, each symbol has two resampling points, one corresponding to an optimal sampling point of a received symbol and the other being a sampling point at the middle moment of the symbol, so that a Gardner loop is equivalent to resampling at 2 times of a symbol rate; then sending the resample signal into a Gardner clock error detector, calculating the phase error between the clock of the input signal and a local clock, filtering high-frequency noise in the input signal through a loop filter, wherein the output of the loop filter is the phase adjustment step length of the NCO; and finally, sending the phase adjustment step into NCO to calculate a new interpolation base point and a fraction interval, and sending the new interpolation base point and the fraction interval to an interpolation filter to obtain a new resampling signal. The whole loop works in such a cycle, feedback adjustment is continuously carried out, finally, the phase error between the clock of the input signal and the local clock is approximately 0, and the loop converges. Specifically, a Gardner bit synchronization loop is shown in FIG. 1.
Since the Gardner algorithm is derived based on the BPSK/QPSK signal, which has only two levels: +1 and-1. When BPSK/QPSK modulation is adopted, when symbol conversion occurs to the interpolated front and rear code elements, if there is no clock phase error, the resampling value at the middle time should be 0; in the presence of clock errors, a non-zero value will be generated whose magnitude is proportional to the magnitude of the error. However, if the Gardner algorithm is directly applied to QAM demodulation, since the QAM signal is a multilevel signal, even if there is no clock error after loop convergence has stabilized, the resample value at the middle time when symbol conversion occurs between the preceding and following symbols may not be 0, and the clock error cannot be correctly calculated when symbol conversion does not occur between the preceding and following symbols. Therefore, in QAM demodulation, the existing Gardner algorithm is used, so that the timing jitter is large, and the error rate is increased.
In view of this, how to effectively reduce the error rate of demodulating the QAM signal using the Gardner algorithm becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention provides a method, a device and a storage medium for Quadrature Amplitude Modulation (QAM) signal bit synchronization, which are used for solving the technical problem of higher error rate of demodulating a QAM signal by using a Gardner algorithm in the prior art.
In a first aspect, to solve the above technical problem, an apparatus for quadrature amplitude modulation QAM signal bit synchronization provided in an embodiment of the present invention includes a clock error detector and a loop filter, and:
two interpolation filters, which are used for resampling the input signal according to the interpolation base point and the first fractional interval of the previous symbol period in each symbol period, obtaining the resampled signal in each symbol period, and sending the resampled signal to the clock error detector;
the numerical control oscillator is connected between the two interpolation filters, is used for calculating a second fractional interval of the current symbol period, and provides an interpolation base point for the two interpolation filters;
a fractional interval jump detector connected between the two interpolation filters, connected with the numerically controlled oscillator, and used for detecting whether discontinuous sampling points occur in the first fractional interval; and when the discontinuous sampling points occur in the first fraction interval, correcting the error interpolation of the input signal inserted in the first fraction interval by using the second fraction interval to obtain new resampling points.
By adding a jump detector with fractional interval in the existing Gardner bit synchronous loop, the Gardner bit synchronous loop can automatically correct the error interpolation caused by timing jitter at the discontinuous point with fractional interval, thereby greatly reducing the error rate and ensuring that the error code performance of the Gardner bit synchronous loop is not sensitive to the timing jitter any more.
In one possible implementation, the clock error detector is connected between the resampled signal outputs of the two interpolation filters, and is configured to:
detecting a clock error of a clock of the sampling signal from a local clock and delivering the clock error to the loop filter.
In a possible implementation, the loop filter is connected between the clock error detector and the loop filter, and configured to:
and filtering high-frequency noise in the clock error to obtain the phase adjustment step size of the numerical control oscillator.
In one possible implementation, the fractionally-spaced transition detector is configured to:
calculating a difference between the second fractional interval and the first fractional interval;
and if the absolute value of the difference is larger than a preset threshold value, determining that the first fractional interval occurs at discontinuous sampling points, and enabling the two interpolation filters to resample the input signal based on the second fractional interval.
When the difference value between the second fraction interval and the first fraction interval is larger than the preset threshold value, the first fraction interval can be quickly determined to occur at discontinuous sampling points, and then the two interpolation filters resample the input signal based on the second fraction interval so as to correct interpolation errors and reduce the error rate.
In one possible implementation, the clock error detector includes:
the clock detection module based on decision feedback is connected with the two pre-filtering modules at two input ends respectively, and the output end of the clock detection module based on decision feedback is connected with the input end of the loop filter;
the two pre-filtering modules are used for performing pre-filtering shaping on the resampled signals;
and the clock detection module for decision feedback is used for calculating the clock error based on a preset algorithm.
The clock error detector in the Gardner bit synchronization loop is set as a pre-filtering module and a clock error detection module based on decision feedback to eliminate the reason of timing jitter, so that a loop filter in the Gardner bit synchronization loop can reduce the timing jitter by using a larger tap coefficient, the requirement of the loop filter on the data bit width is reduced, and chip resources are saved.
In one possible implementation, the spectral responses of the two pre-filtering modules are:
wherein Hpre(f) For the spectral response of the pre-filtering module, f is the frequency, G (f) is the spectral response of the raised cosine roll-off filter, and T is the symbol period.
In a possible implementation manner, the preset algorithm is:
τ(j)＝y_I(k-1)·sign[y_I(k)-y_I(k-2)]+y_Q(k-1)·sign[y_Q(k)-y_Q(k-2)]；
wherein τ (j) is the clock error, k is a natural number representing the number of the current symbol period, y _ I (k) is the I-path sampling signal of the current symbol period, y _ I (k-2) is the I-path sampling signal of the previous two symbol periods, y _ I (k-1) is the I-path sampling signal of the previous symbol period, y _ Q (k) is the Q-path sampling signal output by the current symbol period, y _ Q (k-1) is the Q-path sampling signal output by the previous symbol period, y _ Q (k-2) is the Q-path sampling signal output by the previous two symbol periods, and sign [ ] is the symbol of the calculation result within [ ].
In a second aspect, an embodiment of the present invention provides a method for bit synchronization of a quadrature amplitude modulation QAM signal, including:
based on an interpolation base point and a first fractional interval of a previous symbol period, resampling an input signal in the current symbol period by using two interpolation filters respectively to obtain a resampled signal;
calculating an interpolation base point and a second fractional interval of the current symbol period by using a numerical control oscillator based on the first fractional interval and the current phase adjustment step length;
and on the basis of the first fractional interval and the second fractional interval, judging whether the first fractional interval occurs at discontinuous sampling points by using a fractional interval jump detector, and if so, replacing the first fractional interval by the second fractional interval to ensure that the two interpolation filters respectively resample the two paths of input signals in the current symbol period.
In one possible implementation, after obtaining the resampled signal, the method further includes:
and detecting a clock error of the resampled signal by using a clock error detector, wherein the clock error is the phase difference between the clock of the resampled signal and a local clock.
In a possible implementation manner, after detecting the clock error of the resampled signal by using the clock error detector, the method further includes:
and filtering high-frequency noise in the clock error by using a loop filter to obtain the phase adjustment step length of the numerical control oscillator.
In one possible implementation, the determining whether the first fractional interval occurs at discontinuous sampling points by using a fractional interval jump detector includes:
calculating a difference between the second fractional interval and the first fractional interval;
and if the absolute value of the difference is larger than a preset threshold value, determining that the first fractional interval occurs at discontinuous sampling points, and enabling the two interpolation filters to resample the input signal based on the second fractional interval.
In one possible implementation, detecting a clock error of the resampled signal by a clock error detector includes:
pre-filtering and shaping the resampled signal by using a pre-filtering module to obtain a shaped resampled signal;
and calculating the reshaped resampled signal by using a preset algorithm in a clock detection module for decision feedback to obtain the clock error.
In a possible implementation manner, the spectral responses of the two pre-filtering modules are specifically:
wherein Hpre(f) Is composed ofThe adopted spectral response of the pre-filtering module is f frequency, G (f) is the spectral response of the raised cosine roll-off filter, and T is a symbol period.
In a possible implementation manner, the preset algorithm specifically includes:
τ(j)＝y_I(k-1)·sign[y_I(k)-y_I(k-2)]+y_Q(k-1)·sign[y_Q(k)-y_Q(k-2)]；
wherein τ (j) is the clock error, k is a natural number representing the number of the current symbol period, y _ I (k) is the I-path sampling signal of the current symbol period, y _ I (k-2) is the I-path sampling signal of the previous two symbol periods, y _ I (k-1) is the I-path sampling signal of the previous symbol period, y _ Q (k) is the Q-path sampling signal output by the current symbol period, y _ Q (k-1) is the Q-path sampling signal output by the previous symbol period, y _ Q (k-2) is the Q-path sampling signal output by the previous two symbol periods, and sign [ ] is the symbol of the calculation result within [ ].
In a third aspect, an embodiment of the present invention further provides a quadrature amplitude modulation QAM signal bit synchronization apparatus, including:
at least one processor, and
a memory coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, and the at least one processor performs the method according to the second aspect by executing the instructions stored by the memory.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, including:
the computer readable storage medium stores computer instructions which, when run on a computer, cause the computer to perform the method according to the second aspect as described above.
Through the technical solutions in one or more of the above embodiments of the present invention, the embodiments of the present invention have at least the following technical effects:
in the embodiment provided by the invention, the fractional interval jump detector is added in the existing Gardner bit synchronization loop, so that the Gardner bit synchronization loop can automatically correct the error interpolation caused by the timing jitter at the discontinuous point of the fractional interval, thereby greatly reducing the error rate and ensuring that the error code performance of the Gardner bit synchronization loop is not sensitive to the timing jitter any more.
Further, in the embodiment provided by the present invention, the clock error detector in the Gardner bit synchronization loop is configured as the pre-filtering module and the decision feedback-based clock error detection module to eliminate the cause of the timing jitter, so that the loop filter in the Gardner bit synchronization loop can use a larger tap coefficient to reduce the timing jitter, and further reduce the requirement of the loop filter on the data bit width, thereby saving chip resources. For example, in 64QAM demodulation, the present invention may increase the loop filter coefficient to 10-6And the bit width of nearly 7 bits is saved by orders of magnitude. Not only saves chip resources, but also can accelerate the convergence speed of the Gardner bit synchronization loop.
Drawings
FIG. 1 is a schematic diagram of a prior art Gardner bit synchronization loop;
fig. 2 is a schematic structural diagram of a quadrature amplitude modulation QAM signal bit synchronization apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another quadrature amplitude modulation QAM signal bit synchronization apparatus according to an embodiment of the present invention;
fig. 4 is a flowchart of bit synchronization of a QAM signal according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a Quadrature Amplitude Modulation (QAM) signal bit synchronization method, a device and a storage medium, which aim to solve the technical problem of higher error rate of demodulating a QAM signal by using a Gardner algorithm in the prior art.
In order to solve the technical problems, the general idea of the embodiment of the present application is as follows:
there is provided a quadrature amplitude modulation QAM signal bit synchronizing apparatus, comprising: a clock error detector and a loop filter; two interpolation filters, which are used for resampling the input signal according to the interpolation base point and the first fractional interval of the previous symbol period in each symbol period to obtain a resampled signal in each symbol period and sending the resampled signal to the clock error detector; the numerical control oscillator is connected between the two interpolation filters and used for calculating an interpolation base point and a second fractional interval of the current symbol period and transmitting the interpolation base point of the current symbol period to the two interpolation filters; the fractional interval jump detector is connected between the two interpolation filters, connected with the numerical control oscillator and used for detecting whether discontinuous sampling points occur in the second fractional interval; and when the discontinuous sampling points of the first fractional interval are determined, correcting the error interpolation of the input signal inserted in the first fractional interval to obtain new resampling points.
In the scheme, the fractional interval jump detector arranged between the two interpolation filters is used for detecting whether discontinuous sampling points occur in the first fractional interval used when the interpolation filters resample the input signal, and if the discontinuous sampling points occur, the error interpolation of the input signal is corrected by using the second fractional interval to obtain new resampling points. Thereby reducing the error rate of the Gardner bit synchronization loop.
In order to better understand the technical solutions of the present invention, the following detailed descriptions of the technical solutions of the present invention are provided with the accompanying drawings and the specific embodiments, and it should be understood that the specific features in the embodiments and the examples of the present invention are the detailed descriptions of the technical solutions of the present invention, and are not limitations of the technical solutions of the present invention, and the technical features in the embodiments and the examples of the present invention may be combined with each other without conflict.
Before the technical solution of the present invention is introduced, some knowledge related to the present invention is briefly introduced.
After the Gardner bit synchronization loop is converged and stabilized, the clock error output by the clock error detector should be 0 theoretically, but due to the influence of self-noise and white gaussian noise of the QAM signal, the clock error will fluctuate around 0 after stabilization, which is the steady-state phase difference jitter, also called timing jitter. Timing jitter is one of the important causes of error in the loop.
Tap coefficient the loop filter in the Gardner bit synchronization loop has two tap coefficients, c1And c2。c1And c2Is measured by the loop bandwidth wnDetermining, by the loop filter, the loop bandwidth wnThe convergence speed and timing jitter of the Gardner bit synchronization loop are controlled. In general wnThe larger, c1And c2The larger the difference, the faster the convergence speed of the Gardner bit synchronization loop and the larger the timing jitter; conversely, the slower the Gardner bit synchronization loop converges, the less the timing jitter. In the engineering implementation, wnTypically up to 10-3。
The interpolation base point is provided for the interpolation filter by a numerically controlled oscillator NCO in a Gardner bit synchronization loop, the interpolation base point determines which 4 input sampling points participate in interpolation calculation, fractional intervals are used for calculating tap coefficients of the interpolation filter in real time, the value of the tap coefficients is between 0 and 1, and the magnitude of clock deviation is represented. In the actual modulation and demodulation process, the crystal oscillators of the transmitting side and the receiving side often have clock difference, the fractional interval oscillates between 0 and 1 at the moment, most of the time fractional interval is continuously changed, but the timing jitter easily causes the jump of the fractional interval at a critical point near 0 or 1, for example, the fraction interval is easily jumped to a position near 1 due to the timing jitter when the fractional interval is close to 0.
In the prior art, in order to reduce the timing jitter, a common method is to reduce the timing jitter by reducing the tap coefficient of the loop filter, but since the convergence rate and the timing jitter are contradictory, the loop capture time is increased, the error rate is increased, and the self-noise cannot be completely eliminated by reducing the loop filter coefficient at a glance, and the timing jitter still has most of residues. In addition, the actual size of the loop filter coefficients in an engineered implementation is typically 10-8On the order of magnitude, this requires a lot of resources to perform fixed point quantization in order to achieve a certain accuracy, which obviously increases the chip area.
In a Gardner bit synchronization loop, one symbol period is the period over which the Gardner bit synchronization loop computes a fractional interval from the clock error. The invention finds that in the Gardner bit synchronization loop, the essence of the feedback loop is to predict the clock error of the QAM signal in the current symbol period by the clock error of the QAM signal in the previous symbol period according to the continuity of the clock error. That is, the interpolation for the current symbol period actually utilizes the fractional interval calculated from the clock error of the QAM signal in the last symbol period. Therefore, at the continuous points of the fractional intervals, the interpolation is normal, and at the discontinuous points of the fractional intervals, the feedback loop cannot correctly predict the clock error of the current QAM signal through the clock error of the QAM signal in the previous symbol period, so that the interpolation is wrong, and the timing jitter easily causes the jump of the fractional intervals at the critical position, which is the main reason of the error caused by the timing jitter. In order to eliminate timing jitter, in the embodiment of the present invention, a fractional interval transition detector is added in an existing Gardner bit synchronization loop, and is used to detect whether a fractional interval used in a current symbol period (i.e. a fractional interval of a previous symbol period, which is referred to as a first fractional interval in the embodiment of the present invention) is a discontinuous point, and if so, a fractional interval calculated by using a clock error of the current symbol period (which is referred to as a second fractional interval in the embodiment of the present invention) is used to resample an input signal of the current symbol period to correct erroneous interpolation, thereby reducing an error rate caused by timing jitter.
Referring to fig. 2, an embodiment of the present invention provides a quadrature amplitude modulation QAM signal bit synchronization apparatus, including:
two interpolation filters 201 for resampling the input signal according to the interpolation base point and the first fractional interval of the previous symbol period in each symbol period to obtain a resampled signal in each symbol period, and sending the resampled signal to the clock error detector 202.
A clock error detector 202 connected between the resampled signal output ends of the two interpolation filters 201, for detecting a clock error between the clock of the input signal and the local clock, and transmitting the clock error to the loop filter 203;
and a loop filter 203 connected between the clock error detector 202 and the dco 204 for filtering high frequency noise in the clock error to obtain a phase adjustment step size of the dco 204.
And a digital controlled oscillator 204 connected between the two interpolation filters 201, for calculating an interpolation base point and a second fractional interval of the current symbol period, and transmitting the interpolation base point of the current symbol period to the two interpolation filters 201.
A fractional interval jump detector 205 connected between the two interpolation filters 201 and connected to the digital controlled oscillator 204 for detecting whether a discontinuous sampling point occurs in the second fractional interval; and when the discontinuous sampling points of the first fraction interval are determined, correcting the error interpolation of the input signal inserted into the first fraction interval by using a second fraction interval to obtain new resampling points.
In fig. 2, after the I-path input signal and the Q-path input signal respectively enter the corresponding interpolation filter 201, the interpolation filter 201 reads an interpolation base point and a first fractional interval of a previous symbol period from a register of the digital controlled oscillator 204 to resample the input signal to output the I-path resampled signal and the Q-path resampled signal, the clock error detector 202 calculates the I-path resampled signal and the Q-path resampled signal to obtain a clock error between a clock of the I-path resampled signal and a local clock, and then filters the clock error through the loop filter 203 to filter high-frequency noise in the clock error, thereby outputting a phase adjustment step size to the digital controlled oscillator 204.
The digitally controlled oscillator 204 may calculate the second fractional interval of the current symbol period by:
first, a first fractional interval N (i-1) is obtained from a register of the dco 204, and then, whether the dco 204 overflows in the next symbol period is determined according to the first fractional interval and the phase adjustment step. Specifically, a difference between the first fractional interval and the phase adjustment step is calculated to be N _ temp (i), and if the difference N _ temp (i) between the first fractional interval and the phase adjustment step is not less than 0, it is determined that the vco 204 will not overflow in the next symbol period, and it is determined that the difference N _ temp (i) is used as the second fractional interval; if the difference N _ temp (i) between the first fractional interval and the phase adjustment step is less than 0, and it is determined that the dco 204 will overflow in the next symbol period, modulo 1 operation is performed on N _ temp (i), the modulo result is taken as the second fractional interval, and the second fractional interval is used to cover the first fractional interval in the register of the dco 204.
After the second fractional interval is calculated by the dco 204, the fractional interval transition detector 105 determines whether the first fractional interval occurs at a discontinuous point according to the second fractional interval and the first fractional interval, and needs to resample the I and Q input signals. Specifically, a second fractional interval is obtained from the numerically controlled oscillator 104, and a difference between the second fractional interval and the first fractional interval is calculated; if the absolute value of the difference between the second fractional interval and the first fractional interval is greater than a preset threshold (e.g., 0.9), it is determined that the first fractional interval occurs at a discontinuous point, and the second fractional interval is sent to the two interpolation filters 201, so that the two interpolation filters 201 resample the I and Q input signals based on the second fractional interval to obtain new I and Q resampled signals. If the absolute value of the difference between the second fractional interval and the first fractional interval is smaller than the preset threshold, it is determined that the first fractional interval occurs at consecutive sampling points, and the I-path and Q-path resample signals are extracted as the optimal sampling points, so that the interpolation filter 201 resamples the I-path and Q-path input signals of the next symbol period, and so on.
Further, referring to fig. 3, the clock error detector 202 may also be composed of two and filter modules and a decision feedback-based clock detection module 2022, the input ends of the two pre-filter modules 2021 are respectively connected to the I-path and Q-path built-in filters, and the decision feedback-based clock detection module 2022 is connected between the output ends of the two pre-filter modules 2021. Before calculating the clock error, the clock detection module 2022 based on decision feedback filters the resampled signals from the I path and the Q path through the two pre-filtering modules 2021, respectively, thereby greatly reducing the timing jitter.
Specifically, the frequency spectrum response adopted by the pre-filtering module 2021 is:
wherein Hpre(f) For the spectral response of the pre-filtering module 2021, f is the frequency, G (f) is the spectral response of the raised cosine roll-off filter, and T is the symbol period.
To Hpre(f) After performing the inverse fourier transform, the time-domain continuous impulse response of the pre-filtering module 2021 can be obtained as:
wherein h ispre(t) is the time-domain continuous impulse response of the pre-filtering module 2021, α is the roll-off factor, and t is the sampling period of the resampled signal. To hpre(t) truncation of the samples to obtain a finite digital impulse response h for the pre-filtering module 2021pre(n) n is a natural number. The pre-filtering module 2021 pre-filters and shapes the I-path and Q-path resampled signals (i.e. the interpolated QAM signals), and the zero-crossing point of the I-path and Q-path input signals (i.e. the QAM signals) will occur at the time between the front and rear symbols, so as to achieve the purpose of reducing the timing jitter.
After the I and Q resampled signals are shaped by the pre-filtering module 2021, the clock error of the clock of the sampled signal and the local clock is detected by the clock module based on decision feedback.
Specifically, the clock module detection based on decision feedback is a clock error obtained by calculating the re-sampled signals of the I path and the Q path after shaping through a preset algorithm.
Specifically, the preset algorithm is as follows:
τ(j)＝y_I(k-1)·sign[y_I(k)-y_I(k-2)]+y_Q(k-1)·sign[y_Q(k)-y_Q(k-2)] (3)
wherein τ (j) is a clock error, k is a number of a natural number representing a current symbol period, y _ I (k) is an I-path sampling signal of the current symbol period, y _ I (k-2) is an I-path sampling signal of a previous symbol period, y _ I (k-1) is an I-path sampling signal of a previous symbol period, y _ Q (k) is a Q-path sampling signal output by the current symbol period, y _ Q (k-1) is a Q-path sampling signal output by the previous symbol period, y _ Q (k-2) is a Q-path sampling signal output by the previous symbol period, and n [ ] is a symbol of a calculation result in [ ] sigjl.
As can be seen from the formula (3), the clock error calculated when the front and rear sampling signals have no symbol conversion is 0, so that the problem that the clock error cannot be correctly obtained when the front and rear sampling signals have no symbol conversion is solved.
The clock error detector 202 in the Gardner bit synchronization loop is arranged to include two pre-filtering modules 2021 and a clock detection module 2022 for decision feedback, so that the pre-filtering module 2021 and the clock error detection module based on decision feedback can be used together to reduce timing jitter to a great extent, and further the loop filter 203 in the Gardner bit synchronization loop can still have very small timing jitter even if a large tap coefficient is used, thereby the limitation on the coefficient order of magnitude of the loop filter 203 is removed, thus not only accelerating loop convergence, but also saving chip resources.
Based on the same inventive concept, an embodiment of the present invention provides a method for Quadrature Amplitude Modulation (QAM) signal synchronization, and the specific implementation of the method may refer to the description of the embodiment of the apparatus, and repeated descriptions are omitted, please refer to fig. 4, where the method includes:
step 401: based on an interpolation base point and a first fractional interval of a previous symbol period, resampling an input signal in the current symbol period by using two interpolation filters respectively to obtain a resampled signal;
step 402: calculating an interpolation base point and a second fractional interval of the current symbol period by using a numerical control oscillator based on the first fractional interval and the current phase adjustment step length;
step 403: and on the basis of the first fractional interval and the second fractional interval, judging whether the first fractional interval occurs at discontinuous sampling points by using a fractional interval jump detector, and if so, replacing the first fractional interval by the second fractional interval to ensure that the two interpolation filters respectively resample the two paths of input signals in the current symbol period.
Optionally, after obtaining the resampled signal, the method further includes:
and detecting a clock error of the resampled signal by using a clock error detector, wherein the clock error is the phase difference between the clock of the resampled signal and a local clock.
Optionally, after detecting the clock error of the resampled signal by using the clock error detector, the method further includes:
and filtering high-frequency noise in the clock error by using a loop filter to obtain the phase adjustment step length of the numerical control oscillator.
Optionally, the determining, by the fractionally spaced hopping detector, whether the first fractionally spaced hopping occurs at discontinuous sampling points includes:
calculating a difference between the second fractional interval and the first fractional interval;
and if the absolute value of the difference is larger than a preset threshold value, determining that the first fractional interval occurs at discontinuous sampling points, and enabling the two interpolation filters to resample the input signal based on the second fractional interval.
Optionally, detecting the clock error of the resampled signal by using a clock error detector includes:
pre-filtering and shaping the resampled signal by using a pre-filtering module to obtain a shaped resampled signal;
and calculating the reshaped resampled signal by using a preset algorithm in a clock detection module for decision feedback to obtain the clock error.
Optionally, the spectral responses of the two pre-filtering modules are specifically:
wherein Hpre(f) For the spectral response of the pre-filtering module, f is the frequency, G (f) is the spectral response of the raised cosine roll-off filter, and T is the symbol period.
Optionally, the preset algorithm specifically includes:
τ(j)＝y_I(k-1)·sign[y_I(k)-y_I(k-2)]+y_Q(k-1)·sign[y_Q(k)-y_Q(k-2)]；
wherein τ (j) is the clock error, k is a natural number representing the number of the current symbol period, y _ I (k) is the I-path sampling signal of the current symbol period, y _ I (k-2) is the I-path sampling signal of the previous two symbol periods, y _ I (k-1) is the I-path sampling signal of the previous symbol period, y _ Q (k) is the Q-path sampling signal output by the current symbol period, y _ Q (k-1) is the Q-path sampling signal output by the previous symbol period, y _ Q (k-2) is the Q-path sampling signal output by the previous two symbol periods, and sign [ ] is the symbol of the calculation result within [ ].
Based on the same inventive concept, an embodiment of the present invention provides an apparatus for modulating a QAM signal with a quadrature amplitude for synchronization, including: at least one processor, and
a memory coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the at least one processor executing the instructions stored by the memory to perform a quadrature amplitude modulation, QAM, signal method as described above.
Based on the same inventive concept, an embodiment of the present invention further provides a computer-readable storage medium, including:
the computer readable storage medium stores computer instructions which, when executed on a computer, cause the computer to perform a quadrature amplitude modulation, QAM, signal method as described above.
In the embodiment provided by the invention, the fractional interval jump detector is added in the existing Gardner bit synchronization loop, so that the Gardner bit synchronization loop can automatically correct the error interpolation caused by the timing jitter at the discontinuous point of the fractional interval, thereby greatly reducing the error rate and ensuring that the error code performance of the Gardner bit synchronization loop is not sensitive to the timing jitter any more.
Further, in the embodiments provided by the present invention, the clock error detector in the Gardner bit synchronization loop is configured as a pre-filtering module and a clock error based on decision feedbackThe detection module is used for eliminating the reason caused by the timing jitter, so that the loop filter in the Gardner bit synchronization loop can reduce the timing jitter by using a larger tap coefficient, the requirement of the loop filter on the data bit width is further reduced, and the chip resource is saved. For example, in 64QAM demodulation, the present invention may increase the loop filter coefficient to 10-6And the bit width of nearly 7 bits is saved by orders of magnitude. Not only saves chip resources, but also can accelerate the convergence speed of the Gardner bit synchronization loop.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An apparatus for bit synchronization of a quadrature amplitude modulation, QAM, signal, comprising a clock error detector and a loop filter, characterized by:
two interpolation filters, which are used for resampling the input signal according to the interpolation base point and the first fractional interval of the previous symbol period in each symbol period, obtaining the resampled signal in each symbol period, and sending the resampled signal to the clock error detector;
the numerical control oscillator is connected between the two interpolation filters, is used for calculating a second fractional interval of the current symbol period, and provides an interpolation base point for the two interpolation filters;
a fractional interval jump detector connected between the two interpolation filters, connected with the numerically controlled oscillator, and used for detecting whether discontinuous sampling points occur in the first fractional interval; and when the discontinuous sampling points occur in the first fraction interval, correcting the error interpolation of the input signal inserted in the first fraction interval by using the second fraction interval to obtain new resampling points.
2. The apparatus of claim 1, wherein the clock error detector is coupled between resampled signal outputs of the two interpolation filters to:
detecting a clock error of a clock of the sampling signal from a local clock and delivering the clock error to the loop filter.
3. The apparatus of claim 2, wherein the loop filter is coupled between the clock error detector and the digitally controlled oscillator to:
and filtering high-frequency noise in the clock error to obtain the phase adjustment step size of the numerical control oscillator.
4. The apparatus of any of claims 1-3, wherein the fractionally-spaced transition detector is to:
calculating a difference between the second fractional interval and the first fractional interval;
and if the absolute value of the difference is larger than a preset threshold value, determining that the first fractional interval occurs at discontinuous sampling points, and enabling the two interpolation filters to resample the input signal based on the second fractional interval.
5. The apparatus of claim 4, wherein the clock error detector comprises:
the clock detection module based on decision feedback is connected with the two pre-filtering modules at two input ends respectively, and the output end of the clock detection module based on decision feedback is connected with the input end of the loop filter;
the two pre-filtering modules are used for performing pre-filtering shaping on the resampled signals;
and the clock detection module for decision feedback is used for calculating the clock error based on a preset algorithm.
6. The apparatus of claim 5, wherein the spectral responses of the two pre-filtering modules are:
wherein Hpre(f) For the spectral response of the pre-filtering module, f is the frequency, G (f) is the spectral response of the raised cosine roll-off filter, and T is the symbol period.
7. The apparatus of claim 5, wherein the predetermined algorithm is:
τ(j)＝y_I(k-1)·sign[y_I(k)-y_I(k-2)]+y_Q(k-1)·sign[y_Q(k)-y_Q(k-2)]；
wherein τ (j) is the clock error, k is a natural number representing the number of the current symbol period, y _ I (k) is the I-path sampling signal of the current symbol period, y _ I (k-2) is the I-path sampling signal of the previous two symbol periods, y _ I (k-1) is the I-path sampling signal of the previous symbol period, y _ Q (k) is the Q-path sampling signal output by the current symbol period, y _ Q (k-1) is the Q-path sampling signal output by the previous symbol period, y _ Q (k-2) is the Q-path sampling signal output by the previous two symbol periods, and sign [ ] is the symbol of the calculation result within [ ].
8. A method of bit synchronization for a quadrature amplitude modulation, QAM, signal, comprising:
based on an interpolation base point and a first fractional interval of a previous symbol period, resampling an input signal in the current symbol period by using two interpolation filters respectively to obtain a resampled signal;
calculating an interpolation base point and a second fractional interval of the current symbol period by using a numerical control oscillator based on the first fractional interval and the current phase adjustment step length;
and judging whether the first fractional interval occurs at discontinuous sampling points by using a fractional interval jump detector based on the first fractional interval and the second fractional interval, and if so, replacing the first fractional interval by the second fractional interval to ensure that the two interpolation filters respectively resample the input signal in the current symbol period.
9. An apparatus for bit synchronization of a quadrature amplitude modulation, QAM, signal, comprising:
at least one processor, and
a memory coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the at least one processor performing the method of claim 8 by executing the instructions stored by the memory.
10. A computer-readable storage medium characterized by:
the computer readable storage medium stores computer instructions which, when executed on a computer, cause the computer to perform the method of claim 8.
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