CN108989260B - Improved all-digital timing synchronization method and device based on Gardner - Google Patents
Improved all-digital timing synchronization method and device based on Gardner Download PDFInfo
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- CN108989260B CN108989260B CN201810860473.7A CN201810860473A CN108989260B CN 108989260 B CN108989260 B CN 108989260B CN 201810860473 A CN201810860473 A CN 201810860473A CN 108989260 B CN108989260 B CN 108989260B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
Abstract
The invention discloses an improved all-digital timing synchronization method and device based on Gardner, wherein the method comprises the following steps: smoothing and filtering the timing error output by the Gardner timing error detector by using a CIC filter; the smoothed and filtered timing error enters a loop filter with the parameters of the loop filter designed in advance for processing; if the number of sampling points in the code element period is larger than a first threshold value, selecting a single code element by a timing controller to pull timing control for one time; if the number of sampling points in the code element period is less than a second threshold value, a timing controller selects a plurality of code elements to pull timing control once so as to realize timing synchronization of the baseband signal entering a receiving end after carrier stripping. The method can effectively reduce the jitter after the signal synchronization, can ensure that the time for the signal to reach the synchronous locking is not too long, and can use the algorithm to carry out timing synchronization no matter the sampling multiplying power is high or low.
Description
Technical Field
The invention relates to the technical field of communication signal processing, in particular to an improved all-digital timing synchronization method and device based on Gardner.
Background
In a digital communication receiver, because a sampling clock of the receiver and a clock of a transmitting end are mutually independent, in order to output a demodulation code element at an accurate sampling judgment moment, a timing synchronization algorithm is required to be adopted to enable the clock of the receiving end and the clock of the transmitting end to be synchronized, and the traditional method is to continuously adjust the sampling clock of the receiving end through a closed loop structure so as to complete clock synchronization. With the continuous development of the FPGA and digital signal processing technologies, the all-digital receiver has been widely used, and a local processing clock of the all-digital receiver is generally fixed as the FPGA master frequency, so that a receiving end cannot easily adjust the local clock to obtain a clock synchronized with the transmitting end, but the clock synchronization is realized by adopting a mode based on timing control, error detection and interpolation estimation.
Common timing synchronization methods are: timing synchronization algorithms such as early-late gate, M & M, Gardner, etc., wherein each symbol of the early-late gate algorithm requires at least three sampling points, if the baseband signal entering the early-late gate timing synchronization has no edge jump for a long time, the error signals obtained in the multiple symbol periods are always 0, and thus the synchronization is lost; each code element of the M & M algorithm only needs one sampling point, but is sensitive to carrier frequency offset and phase offset, and carrier synchronization is required to be completed first and then timing synchronization is required; each code element of the Gardner algorithm needs two sampling points, one of which is the best sampling point and is insensitive to carrier frequency offset and phase offset, and the timing synchronization can be accurately realized without carrier synchronization.
In the related technology, (1) a feedback symbol timing synchronization method based on interpolation filtering is also based on timing error detection performed by a Gardner algorithm, but timing synchronization jitter is large, and high-precision timing synchronization performance can be achieved only by a high signal-to-noise ratio. (2) A high-speed parallel timing synchronization method based on an interpolation method can realize timing synchronization at high-speed transmission rate of hundreds of megabits per second and even gigabits per second, but has large processing calculation amount, large time delay, large jitter after synchronization and high system complexity.
However, in the all-digital receiver, due to the randomness of signal transmission and the influence of noise and interference, the jitter after synchronization is so large that the receiving end cannot correctly recover the demodulated symbols when the typical timing synchronization method is adopted.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, one objective of the present invention is to provide an improved all-digital timing synchronization method based on Gardner, which can effectively improve the reliability, applicability and universality of timing synchronization, has high efficiency and small error, and is simple and easy to implement.
Another object of the present invention is to propose an improved all-digital timing synchronization device based on Gardner.
In order to achieve the above object, an embodiment of an aspect of the present invention provides an improved all-digital timing synchronization method based on Gardner, including the following steps: smoothing and filtering the timing error output by the Gardner timing error detector by using a CIC filter; the smoothed and filtered timing error enters a loop filter with the parameters of the loop filter designed in advance for processing; if the number of sampling points in the code element period is larger than a first threshold value, selecting a single code element by a timing controller to pull timing control for one time; and if the number of sampling points in the code element period is less than a second threshold value, selecting a plurality of code elements through the timing controller to pull timing control once so as to realize timing synchronization of the baseband signals entering a receiving end after carrier stripping, wherein the first threshold value is greater than the second threshold value.
The improved all-digital timing synchronization method based on Gardner can effectively reduce jitter after signal synchronization, ensure that the time for achieving synchronous locking of signals is not too long, and can be used for timing synchronization no matter with high sampling multiplying power or low sampling multiplying power, thereby effectively improving the reliability, applicability and universality of timing synchronization, having high efficiency and small error, and being simple and easy to realize.
In addition, the improved all-digital timing synchronization method based on Gardner according to the above embodiment of the present invention may further have the following additional technical features:
further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, the two sampling points are transition points of an optimal sampling point output and an adjacent symbol, amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and a timing error is extracted from a sampling signal according to the extracted information and information whether the transition point of the adjacent symbol is zero.
Further, in an embodiment of the present invention, two sampling points of the next symbol period are output by interpolation through closed-loop feedback to the interpolation algorithm according to the timing error, and the optimal sampling point is output externally.
Further, in one embodiment of the present invention, the timing error detector is calculated as follows:
wherein y (i) is a value corresponding to the sampling point at the ith symbol,
is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.
Further, in an embodiment of the present invention, the CIC filter includes a delay unit and an adder-subtractor, and the loop filter adopts a second-order active proportional-integral structure.
In order to achieve the above object, another embodiment of the present invention provides an improved all-digital timing synchronization device based on Gardner, including: a smoothing and filtering module for smoothing and filtering the timing error output by the Gardner timing error detector with a CIC filter; the processing module is used for enabling the smoothed and filtered timing error to enter a loop filter with the parameters of the loop filter designed in advance for processing; the first control module is used for selecting a single code element to pull one-time timing control through the timing controller when the number of sampling points in the code element period is greater than a first threshold value; and the second control module is used for selecting a plurality of code elements to pull one-time timing control through the timing controller when the number of sampling points in the code element period is less than a second threshold value so as to realize timing synchronization of the baseband signals entering a receiving end after carrier stripping, wherein the first threshold value is greater than the second threshold value.
The improved all-digital timing synchronization device based on Gardner can effectively reduce jitter after signal synchronization, ensure that the time for achieving synchronous locking of signals is not too long, and carry out timing synchronization by using the algorithm no matter with high sampling multiplying power or low sampling multiplying power, thereby effectively improving the reliability, applicability and universality of timing synchronization, having high efficiency and small error, and being simple and easy to realize.
In addition, the improved all-digital timing synchronization device based on Gardner according to the above embodiment of the present invention may further have the following additional technical features:
further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, the two sampling points are transition points of an optimal sampling point output and an adjacent symbol, amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and a timing error is extracted from a sampling signal according to the extracted information and information whether the transition point of the adjacent symbol is zero.
Further, in an embodiment of the present invention, two sampling points of the next symbol period are output by interpolation through closed-loop feedback to the interpolation algorithm according to the timing error, and the optimal sampling point is output externally.
Further, in one embodiment of the present invention, the timing error detector is calculated as follows:
wherein y (i) is a value corresponding to the sampling point at the ith symbol,
is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.
Further, in an embodiment of the present invention, the CIC filter includes a delay unit and an adder-subtractor, and the loop filter adopts a second-order active proportional-integral structure.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow diagram of an improved all-digital timing synchronization method based on Gardner according to one embodiment of the present invention;
FIG. 2 is a waveform diagram of a baseband signal entering timing synchronization according to one embodiment of the present invention;
FIG. 3 is a diagram of a device connection according to one embodiment of the present invention;
FIG. 4 is a block diagram of a loop filter structure according to one embodiment of the invention;
FIG. 5 is a signal processing flow diagram according to one embodiment of the invention;
FIG. 6 is a diagram of the results of a simulation verification of the present invention based on the System Generator environment, according to one embodiment of the present invention;
FIG. 7 is a signal constellation diagram before timing synchronization and after timing synchronization of the present invention, in accordance with one embodiment of the present invention;
fig. 8 is a schematic diagram of an improved all-digital timing synchronization apparatus based on Gardner according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The improved all-digital timing synchronization method and apparatus based on Gardner according to the embodiments of the present invention will be described with reference to the accompanying drawings, and first, the improved all-digital timing synchronization method based on Gardner according to the embodiments of the present invention will be described with reference to the accompanying drawings.
Fig. 1 is a flow chart of an improved all-digital timing synchronization method based on Gardner according to an embodiment of the present invention.
As shown in fig. 1, the improved all-digital timing synchronization method based on Gardner comprises the following steps:
in step S101, the timing error output by the Gardner timing error detector is smoothed and filtered using a CIC filter.
It will be appreciated that embodiments of the present invention smooth and filter the timing error output by the Gardner timing error detector using a CIC filter. The following briefly describes the implementation principle.
As can be known from the principle of communication systems, a symbol signal sent by a sending end is transmitted through a channel, a baseband signal obtained after carrier stripping when the symbol signal reaches a receiving end has a raised cosine characteristic, the baseband signal after carrier stripping, that is, the baseband signal before timing synchronization, has a waveform diagram as shown in fig. 2, and only carries two kinds of information, namely "0" or "1", at any sampling time.
Further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, the two sampling points are a transition point between an optimal sampling point output and an adjacent symbol, amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and a timing error is extracted from a sampling signal according to the extracted information and information whether the transition point of the adjacent symbol is zero.
Further, in an embodiment of the present invention, two sampling points of the next symbol period are output by interpolation through closed-loop feedback to the interpolation algorithm according to the timing error, and the optimal sampling point is output externally.
Specifically, the embodiment of the present invention implements timing synchronization based on Gardner, which is completely independent of carrier synchronization, and the basic idea of the algorithm is as follows: outputting two sampling points of interpolation for each code element period by an interpolation method, wherein one sampling point is output as an optimal sampling point of the code element, the other sampling point is a transition point of an adjacent code element, extracting amplitude and polarity change information of the optimal sampling points of the two adjacent code elements, and adding information of whether the transition point of the adjacent code element is zero, so that a timing error can be extracted from a sampling signal, and meanwhile, the timing error is fed back to an interpolation algorithm through a closed loop to adjust the two sampling points of the next code element period output by interpolation, and the optimal sampling point is output externally.
And as shown in fig. 3, the apparatus designed according to the method of the embodiment of the present invention is composed of five parts: interpolation filter, timing error detector, CIC filter, loop filter, and timing controller.
Further, in one embodiment of the present invention, the timing error detector is calculated as follows:
wherein y (i) is a value corresponding to the sampling point at the ith symbol,
is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.
Specifically, the interpolation filter uses a polynomial interpolation function to realize interpolation, and is realized by adopting a simple and efficient Farrow structure, so that the interpolation filter is particularly suitable for realizing a hardware circuit and simplifying the operation complexity. The specific implementation method comprises the following steps: and for each code element, taking four adjacent sampling points of the corresponding point according to the control quantity of the timing controller, and then calculating two sampling point values of the code element on the basis of the decimal interval control quantity output by the timing controller by utilizing a Lagrange interpolation formula based on a sample set of the four sampling points, wherein one sampling point is the optimal sampling point output at last, and the other sampling point is the middle sampling point value of the optimal sampling points of the two adjacent code elements.
Wherein, the timing error detector has the following calculation formula:
wherein y (i) is a value corresponding to the sampling point at the ith symbol,
the corresponding value of the middle sampling point of the ith code element and the (i-1) th code element is output to be zero when no timing error exists; when the timing is advanced, the output is negative; when the timing is lagging, the output is positive.
Further, in one embodiment of the invention, the CIC filter includes a delay and an adder-subtractor.
Specifically, in the embodiment of the present invention, an error output of the timing error detector is first passed through a CIC filter with a simple structure, and the error is smoothed and averaged, so as to reduce the influence of error jitter on synchronization. The CIC filter used in the algorithm device is realized only by a delayer and an adder-subtractor, has low complexity, occupies extremely low hardware resources and is easy to realize.
In step S102, the smoothed and filtered timing error is subjected to loop filter processing in which loop filter parameters are designed in advance.
It will be appreciated that the smoothed and filtered timing error is fed into the loop filter processing, while the loop filter parameters are properly designed.
Further, in one embodiment of the present invention, the loop filter employs a second-order active proportional-integral structure.
Specifically, the loop filter of the embodiment of the present invention adopts a simple second-order active proportional-integral structure, and an implementation structure thereof is shown in fig. 4.
The performance of the loop filter is adjusted by adjusting the values of the proportionality constant C1 and the integral constant C2, and the calculation formulas of C1 and C2 are as follows:
where is the damping coefficient, T represents the frequency control word update time period of the loop NCO, KdFor loop gain, for phase discriminator gain KpWith a Numerically Controlled Oscillator (NCO) gain K0Product of, ωnFor the loop damped oscillation frequency, the calculation formula is as follows:
where B denotes the noise bandwidth of the loop filter.
In an actual communication system, the loop filter parameters are reasonably designed, so that not only is the error jitter of a synchronous tracking loop small, but also the time for achieving synchronization and locking is short, and the method can be applied to the signal timing synchronization process of any system sampling clock and code element rate in a large range and has universality.
The loop filter designed by the embodiment of the invention has the following parameters:
the damping coefficient is generally 0.707, the loop bandwidth B is 0.001 of the code element rate, the integral time T is the reciprocal of the system sampling clock, and the gain K of the phase discriminatorpNCO gain with a value of 1
Wherein f issFor a system sampling clock, N is the number of bits of an NCO phase accumulator, and thus all the parameters are substituted into a formula 2 and a formula 3 after being subjected to value taking, and proper loop parameters C1 and C2 are calculated, and the system sampling clock can be slightly adjusted according to actual engineering requirements.
In step S103, if the number of sampling points in the symbol period is greater than the first threshold, a single symbol is selected by the timing controller to pull timing control once.
It will be appreciated that the timing controller selects a single symbol to pull timing control once when the number of samples in a symbol period is sufficiently large.
Specifically, the timing controller mainly comprises a numerically controlled oscillator and a decimal interval counter, the numerically controlled oscillator is used as an accumulator,continuously subtracting the timing error of the current code element output, and interpolating the base point m when the overflow moment is generatedkThe position of (a); the decimal interval counter counts decimal intervals ukAnd m iskAnd is output to an interpolation filter for interpolation, thereby adjusting the sampling position of the next symbol.
The embodiment of the invention improves the timing controller: determining the number of sampling points n in a code element period according to a system sampling clock and a code element rate, if the number of sampling points in the code element period is too small, selecting M (M is more than 1) code element periods to pull timing control once, namely taking a modulus of M when a register of a numerical control oscillator overflows as the value of a current accumulator, outputting a current interpolation base point, fixing the interval between the interpolation base points of the following M-1 code elements to be n, and calculating a decimal interval u once in the M code element periodskAnd then output to the interpolation filter for interpolation. The timing controller of the embodiment of the invention can reduce the phase jitter caused by the synchronization error and improve the synchronization performance; meanwhile, when the device is implemented by hardware, the timing controller returns the value to the timing controller after judging whether the numerical control oscillator overflows so as to limit the sampling of low multiplying power by the delay required by next accumulation, and the timing controller can also be pulled by M code elements once, so that the application range of the timing controller disclosed by the embodiment of the invention is expanded to the condition of low sampling multiplying power.
In step S104, if the number of sampling points in the symbol period is less than a second threshold, the timing controller selects a plurality of symbols to pull timing control once, so as to implement timing synchronization of the baseband signal after carrier stripping at the receiving end, where the first threshold is greater than the second threshold.
It will be appreciated that the timing controller selects a number of symbols to pull timing control once when the number of samples in a symbol period is small.
The improved all-digital timing synchronization method based on Gardner will be further explained with reference to the attached drawings.
As shown in fig. 5, the processing flow of the embodiment of the present invention specifically includes:
(1) when the sampling rate of the system is more than 3 times of the signal bandwidth, the system is regarded as an oversampling processing system. The number of sample points n in the symbol period can be calculated based on known information such as the system sample rate, signal bandwidth, signal pattern, etc.
(2) Setting initial values for registers in a loop filter register, a digitally controlled oscillator register in a timing controller and a decimal interval counter.
(3) According to the set initial value, the timing controller outputs an initial control quantity: interpolating the base point and the decimal interval value, starting an interpolation filter to perform interpolation estimation on the next code element, and outputting two interpolation sampling points.
(4) The timing error detector receives the interpolation sampling points output by the interpolation filter, calculates the timing error at the moment, outputs the timing error to the CIC filter, smoothes the timing error in a section of code element length, and obtains the average timing error.
(5) The parameters of the loop filter for timing synchronization are reasonably designed, and the loop parameters required by the signal timing synchronization of any system sampling clock and the code element rate in a large range can be designed according to the design rule of the parameters of the loop filter provided by the algorithm.
(6) The timing controller receives an output error value of the loop filter, the timing controller can be improved to perform M code element traction one-time timing control, M can be set according to a multiplying power relation between a system sampling clock and a code element rate, M can be set to be 1 when the multiplying power is higher, and M is set to be an integer larger than 1 when the multiplying power is lower.
(7) After a period of synchronization process, the timing error reaches a convergence state and tends to be stable, so that stable tracking of the received signal is achieved, and the optimal decision signal of the signal is output.
In a specific embodiment of the present invention, assuming that a QPSK signal symbol rate is 28.6MHz, a System sampling clock is 300MHz, the number of sampling points in each symbol period of a baseband signal is not an integer, the whole is about 10, the length of a CIC filter is set to 3 × n sampling points, a loop filter is calculated as C1 ═ 0.01035 and C2 ═ 1.32e-6 according to design rules, a timing controller is set to 3 symbol-drawn timing controls, a Xilinx model is constructed for the algorithm apparatus under a System Generator environment, and a simulation result is obtained as shown in fig. 6, where din _ i and din _ q are inputs of the timing synchronization module and are baseband QPSK signals, dout _ i and dout _ q are optimal sampling point values output after timing synchronization, dout _ i _1b and dout _ q _1b are optimal sampling points after timing synchronization and are demodulated samples of optimal sampling points after timing synchronization, and ted is a timing error curve, samp _ en is a synchronous extraction sequence, and it can be seen from fig. 7 that the system processing delay is small, and the error jitter is small after the synchronization reaches stable tracking.
The optimal sampling point value after the timing synchronization in the System Generator is realized is output to Matlab, baseband signal constellations before and after the timing synchronization are drawn as shown in figure 7, and the constellation diagrams show that the device works stably, has good synchronization performance, and the recovered demodulation code element is accurate and reliable, is very close to an ideal QPSK constellation diagram, and has correct judgment result.
The embodiment of the invention has the following advantages that:
(1) aiming at an oversampling processing system, according to known information such as system processing sampling rate, signal bandwidth, received signal pattern and the like, the number of sampling points in each code element period is determined, when the number of sampling points in the code element period which is calculated theoretically is not an integer, timing synchronization processing of the algorithm is not influenced, at the moment, the number of sampling points in the code element period is taken as the nearest integer, namely, the algorithm can process the timing synchronization process of any code element rate in a certain range.
(2) The error result of the timing error detector in the device of the invention enters the CIC filter for smooth filtering and averaging and then is input to the loop filter, thereby effectively reducing the error caused by the timing error jitter to synchronization and enhancing the anti-interference capability.
(3) The design rule of the loop filter parameters is provided, which is generally used in the signal timing synchronization process of any system sampling clock and code element rate in a large range, and the problem that the loop parameters need to be redesigned when the sampling clock or the code rate and the like are changed randomly in the actual engineering is avoided; meanwhile, the parameters of the loop filter are reasonably designed, so that the synchronization convergence time is ensured to be short, and the synchronization error jitter is not too large.
(4) The timing controller is improved: according to the number of sampling points in a code element period, M code elements are set to pull one-time timing control, the problem of strict requirements of real-time feedback values on time delay after a timing control accumulation and subtraction device overflows under the condition that the rate ratio of a system sampling clock to the code elements is low multiplying power can be solved, the jitter of timing errors after synchronous locking can be effectively reduced, and the synchronization precision is further improved.
According to the improved all-digital timing synchronization method based on Gardner provided by the embodiment of the invention, the jitter of the phase error after timing synchronization is realized is small, the synchronization error curve is stable, and the anti-interference capability and the anti-noise performance are stronger; the realization structure is simple, the most basic logic devices such as a register, a multiplier, a comparator, an adder, a multi-path selector and the like can be completely realized, and the consumption resource is low; the algorithm processing platform is not limited, and platforms such as an FPGA, a DSP and the like are easy to realize; the timing synchronization algorithm has strong universality, is suitable for the conditions of high sampling multiplying power and low sampling multiplying power, and once loop filter parameters are configured according to design rules, the loop parameters can be automatically recalculated when the sampling clock or code element rate of the system is randomly changed, so that the efficiency is improved.
Next, an improved all-digital timing synchronization apparatus based on Gardner according to an embodiment of the present invention will be described with reference to the accompanying drawings.
Fig. 8 is a schematic structural diagram of an improved all-digital timing synchronization device based on Gardner according to an embodiment of the present invention.
As shown in fig. 8, the improved all-digital timing synchronization apparatus 10 based on Gardner comprises: a smoothing and filtering module 100, a processing module 200, a first control module 300, and a second control module 400.
Wherein the smoothing and filtering module 100 is configured to smooth and filter the timing error output by the Gardner timing error detector using a CIC filter. The processing module 200 is used to enter the smoothed and filtered timing error into a loop filter process that pre-designs loop filter parameters. The first control module 300 is configured to select a single symbol to pull timing control once through the timing controller when the number of sampling points in a symbol period is greater than a first threshold. The second control module 400 is configured to select, by the timing controller, a plurality of code elements to pull timing control once when the number of sampling points in a code element period is less than a second threshold, so as to implement timing synchronization of a baseband signal entering a receiving end after carrier stripping, where the first threshold is greater than the second threshold. The device 10 of the embodiment of the invention can effectively reduce the jitter after signal synchronization, can ensure that the time for the signal to achieve synchronous locking is not too long, and can use the algorithm to carry out timing synchronization no matter with high sampling multiplying power or low sampling multiplying power, thereby effectively improving the reliability, applicability and universality of timing synchronization, having high efficiency and small error, and being simple and easy to realize.
Further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, the two sampling points are a transition point between an optimal sampling point output and an adjacent symbol, amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and a timing error is extracted from a sampling signal according to the extracted information and information whether the transition point of the adjacent symbol is zero.
Further, in an embodiment of the present invention, two sampling points of the next symbol period are output by interpolation through closed-loop feedback to the interpolation algorithm according to the timing error, and the optimal sampling point is output externally.
Further, in one embodiment of the present invention, the timing error detector is calculated as follows:
wherein y (i) is a value corresponding to the sampling point at the ith symbol,
is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.
Further, in an embodiment of the present invention, the CIC filter includes a delay and an adder-subtractor, and the loop filter adopts a second-order active proportional-integral structure.
It should be noted that the foregoing explanation of the embodiment of the improved all-digital timing synchronization method based on Gardner also applies to the improved all-digital timing synchronization apparatus based on Gardner of this embodiment, and is not repeated herein.
According to the improved all-digital timing synchronization device based on Gardner provided by the embodiment of the invention, the phase error jitter after the timing synchronization is realized is small, the synchronization error curve is stable, and the improved all-digital timing synchronization device has stronger anti-interference capability and anti-noise performance; the realization structure is simple, the most basic logic devices such as a register, a multiplier, a comparator, an adder, a multi-path selector and the like can be completely realized, and the consumption resource is low; the algorithm processing platform is not limited, and platforms such as an FPGA, a DSP and the like are easy to realize; the timing synchronization algorithm has strong universality, is suitable for the conditions of high sampling multiplying power and low sampling multiplying power, and once loop filter parameters are configured according to design rules, the loop parameters can be automatically recalculated when the sampling clock or code element rate of the system is randomly changed, so that the efficiency is improved.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. An improved all-digital timing synchronization method based on Gardner, which is characterized by comprising the following steps:
smoothing and filtering the timing error output by the Gardner timing error detector by using a CIC filter;
the smoothed and filtered timing error enters a loop filter with the parameters of the loop filter designed in advance for processing;
if the number of sampling points in the code element period is larger than a first threshold value, selecting a single code element by a timing controller to pull timing control for one time; and
and if the number of sampling points in the code element period is less than a second threshold value, selecting a plurality of code elements through the timing controller to pull timing control once so as to realize timing synchronization of the baseband signals entering a receiving end after carrier stripping, wherein the first threshold value is greater than the second threshold value.
2. The improved all-digital timing synchronization method based on Gardner as claimed in claim 1, wherein two sampling points of interpolation are outputted for each symbol period by interpolation method, the two sampling points are the transition points of the optimal sampling point output and the adjacent symbol, the amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and the timing error is extracted from the sampling signal according to the extracted information and the information whether the transition point of the adjacent symbol is zero.
3. The improved all-digital Gardner-based timing synchronization method according to claim 2, wherein two sampling points of the next symbol period are interpolated and outputted according to the timing error by adjusting the closed-loop feedback to the interpolation algorithm, and the optimal sampling point is outputted externally.
4. The improved all-digital Gardner-based timing synchronization method according to claim 1, wherein said timing error detector is calculated as follows:
wherein y (i) is a value corresponding to the sampling point at the ith symbol,
is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.
5. The improved all-digital Gardner-based timing synchronization method according to any of claims 1-4, wherein said CIC filter comprises a delay and an adder-subtractor, and said loop filter employs a second-order active proportional-integral structure.
6. An improved all-digital timing synchronization device based on Gardner, comprising:
a smoothing and filtering module for smoothing and filtering the timing error output by the Gardner timing error detector with a CIC filter;
the processing module is used for enabling the smoothed and filtered timing error to enter a loop filter with the parameters of the loop filter designed in advance for processing;
the first control module is used for selecting a single code element to pull one-time timing control through the timing controller when the number of sampling points in the code element period is greater than a first threshold value; and
and the second control module is used for selecting a plurality of code elements to pull one-time timing control through the timing controller when the number of sampling points in the code element period is less than a second threshold value so as to realize timing synchronization of the baseband signals entering a receiving end after carrier stripping, wherein the first threshold value is greater than the second threshold value.
7. The improved all-digital timing synchronization device based on Gardner according to claim 6, wherein two sampling points of interpolation are outputted for each symbol period by interpolation method, the two sampling points are the transition points of the optimal sampling point output and the adjacent symbol, the amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and the timing error is extracted from the sampling signal according to the extracted information and the information whether the transition point of the adjacent symbol is zero.
8. The improved all-digital Gardner-based timing synchronization device according to claim 7, wherein two sampling points of the next symbol period are interpolated and outputted according to said timing error by adjusting the feedback to the interpolation algorithm in a closed loop, and the optimal sampling point is outputted externally.
9. The improved all-digital Gardner-based timing synchronization apparatus according to claim 6, wherein said timing error detector is calculated as follows:
wherein y (i) is a value corresponding to the sampling point at the ith symbol,
is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.
10. The improved Gardner-based all-digital timing synchronization device according to any of claims 6-9, wherein said CIC filter comprises a delay and an adder-subtractor, and said loop filter employs a second order active proportional-integral structure.
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| CN109768852B (en) * | 2019-02-27 | 2021-08-13 | 东南大学 | Method, device and storage medium for realizing precise symbol synchronization processing based on computer software system |
| CN110557195B (en) * | 2019-08-30 | 2020-08-28 | 北京邮电大学 | Timing error detection method and device based on coherent optical communication |
| CN113162713B (en) * | 2020-11-26 | 2022-11-01 | 武汉大学 | Variable symbol rate timing recovery method and system based on Gardner algorithm |
| CN112867135B (en) * | 2020-12-31 | 2022-07-01 | 京信网络系统股份有限公司 | Timing error estimation apparatus, method, medium, and communication device |
| CN115102816B (en) * | 2022-06-16 | 2023-11-03 | 上海道生物联技术有限公司 | FSK-based phase transition method and system for mixed modulation signals |
| CN115189862B (en) * | 2022-07-06 | 2023-12-29 | 中国电子科技集团公司第五十四研究所 | High-precision synchronous data synchronous clock recovery method |
| CN115348000B (en) * | 2022-10-19 | 2022-12-13 | 北京航空航天大学 | Symbol synchronization method and device of single sampling point per symbol based on wiener coefficient solution |
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