CN108306839A - A kind of demodulator circuit and construction method applied to GFSK receivers - Google Patents
A kind of demodulator circuit and construction method applied to GFSK receivers Download PDFInfo
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- CN108306839A CN108306839A CN201810040139.7A CN201810040139A CN108306839A CN 108306839 A CN108306839 A CN 108306839A CN 201810040139 A CN201810040139 A CN 201810040139A CN 108306839 A CN108306839 A CN 108306839A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
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- Computer Networks & Wireless Communication (AREA)
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Abstract
The present invention provides a kind of demodulator circuit applied to GFSK receivers, including interpolation filter, the interpolation filter is used to phase signal obtaining the signal of one times of character rate；Timing Error Detector, the signal that the Timing Error Detector is used to be inputted according to interpolation filter obtain timing error information；Loop filter, the loop filter is for handling timing error information and inputting interpolation controller, interpolation controller control interpolation filter is to baseband signal into row interpolation, finally the sampling clock of interpolater is allowed to converge on symbol clock, to complete the sign synchronization of transmitting terminal and receiving terminal, the present invention can be completed at the same time sign synchronization, the function of carrier wave frequency deviation compensation and symbol judgement, have the characteristics that simple in structure, functional.
Description
Technical field
The present invention relates to GFSK receivers fields, and in particular to a kind of demodulator circuit and structure applied to GFSK receivers
Method.
Background technology
Often there is symbol time offset in the signal that wireless digital receiver receives in communication process.Therefore it needs logical
Symbol Synchronization Circuit is crossed to recover best sampled point.All-digital receiver can use fixed sample frequency, sampling clock
Mutual indepedent with symbol clock, the timing error that is obtained by Timing synchronization circuitry controls interpolation filter, is allowed to output symbol
Number optimum sampling point.
In general, synchronous circuit is by interpolation filter (Interpolator), Timing Error Detector CTiming
ErrorDetector), four parts such as loop filter (LPF) and digital controlled oscillator (NC0) are constituted.
Sampled signal extracts clocking error after interpolation, by Timing Error Detector, is filtered off using loop filter
Digital controlled oscillator is sent to generate the delay of a fractional value to control interpolation after radio-frequency component so that the data of interpolation can obtain most
The time domain of good decimal place deviates.The timing error that the timing loop obtains start when can oscillation on large scale, with it is synchronous into
Row, error amount are finally stablized near a fixed value.When loop-locking, the output valve meeting of the integral branch of loop filter
Converge on the error amount of transmitting-receiving two-end symbol clock.
Timing Error Detection algorithm common at present has door algorithm, Muller-Mueller algorithms and Gardner sooner or later
Algorithm etc..Wherein door algorithm works in 3 times of character rates sooner or later, so hardware spending is big；Gardner algorithms work in 2 times of symbols
Number rate, and it also can be normal there are carrier wave frequency deviation the case where, but structure is all more complicated.
Invention content
In order to solve above-mentioned insufficient defect, the present invention provides a kind of demodulator circuits and structure applied to GFSK receivers
Construction method, the phase signal that the present invention obtains the baseband signal of oversampled signals after difference phase demodulation are same as demodulation
The input of loop is walked, phase signal obtains the signal of one times of character rate after interpolation filter, then accidentally its feeding timing
Difference detector obtains timing error information.Timing error enters interpolation controller, interpolation controller by loop filter processing
Interpolation filter is controlled to baseband signal into row interpolation, the sampling clock of interpolater is finally allowed to converge on symbol clock, to
Complete the sign synchronization of transmitting terminal and receiving terminal.It is influenced when by carrier wave frequency deviation, phase signal has been superimposed a DC component.
So containing the estimating circuit of DC component in loop, adjustment decision threshold is removed using the estimated value of DC component, to ensure
Decision device can correctly recover initial data, and the present invention can be completed at the same time sign synchronization, carrier wave frequency deviation compensation and symbol
The function of judgement has the characteristics that simple in structure, functional.
The present invention provides a kind of demodulator circuit applied to GFSK receivers, including interpolation filter, the interpolation filter
Wave device is used to phase signal obtaining the signal of one times of character rate；Timing Error Detector, the Timing Error Detector are used
Timing error information is obtained in the signal inputted according to interpolation filter；Loop filter, the loop filter is for handling
Timing error information simultaneously inputs interpolation controller, interpolation controller control interpolation filter to baseband signal into row interpolation,
Finally the sampling clock of interpolater is allowed to converge on symbol clock, to complete the sign synchronization of transmitting terminal and receiving terminal.
Above-mentioned demodulator circuit, wherein further include decision device and the estimating circuit of DC component, the DC component is estimated
Meter circuit removes adjustment decision threshold using the estimated value of DC component, to ensure that decision device can correctly recover initial data.
The another side of the present invention, additionally provides a kind of construction method applied to GFSK receiver demodulator circuits, including with
Lower step：
Step (1)：Interpolation calculating is carried out to phase signal；
Step (2)：Value after calculating interpolation is timed control information detection；
Step (3)：Timing error information is filtered using loop filter；
Step (4)：Digital controlled oscillator is sent into the output of loop filter and does accumulation operations；
Step (5)：When digital controlled oscillator, which exports, to be overflowed, decimal time delay spacing u is obtained, and calculate corresponding interpolation system
Number, interpolation filter finally allows the sampling clock of interpolater to converge on symbol clock to input signal into row interpolation at this time, from
And complete the sign synchronization of transmitting terminal and receiving terminal.
Above-mentioned construction method, wherein further include step (6)：When being influenced by carrier wave frequency deviation, phase signal superposition
One DC component, locks carrier wave frequency deviation, and converge on a stationary value by DC component estimating circuit.
Above-mentioned construction method, wherein step (6) further includes：By decision device the output of DC component estimating circuit
As the dynamic decision thresholding of decision device, hard decision is carried out to the output of interpolation filter, 0/1 bit stream is demodulated, with true
Initial data can correctly be recovered by protecting decision device.
Above-mentioned construction method, wherein in the step (1)：The computational methods of interpolation can select linear interpolation or vertical
Square interpolation.
Above-mentioned construction method, wherein in the step (2), the mode of timing error information detection is：
Ted (n)=x (n) * d (n-1)-x (n-1) * d (n), wherein x (n)：N-th of output signal of interpolation device, d (n)：
N-th of output signal of decision device.
Above-mentioned construction method, wherein in the step (3), loop filter is filtered using proportional integration.
Above-mentioned construction method, wherein
The DC component estimating circuit is：Err (n)=x (n)-dc (n-1)-d (n), dc (n)=(1-alpha) * dc
(n-1)+err(n)*alpha.Wherein, x (n)：N-th of output signal of interpolation device, d (n)：N-th of output letter of decision device
Number, dc (n-1) is the direct current component value estimated at the n-1 moment.Alpha is used to control the bandwidth of DC component estimating circuit.
The present invention has the following advantages：1, the present invention obtains the baseband signal of oversampled signals after difference phase demodulation
Phase signal, as the input of demodulation synchronization loop, phase signal obtains one times of character rate after interpolation filter
Signal, then it is sent into Timing Error Detector and obtains timing error information.Timing error is entered by loop filter processing
Interpolation controller, interpolation controller control interpolation filter to baseband signal into row interpolation, finally allow the sampling clock of interpolater
It converges on symbol clock, to complete the sign synchronization of transmitting terminal and receiving terminal.It is influenced when by carrier wave frequency deviation, phase letter
Number a DC component has been superimposed it.So containing the estimating circuit of DC component in loop, the estimated value of DC component is utilized
Adjustment decision threshold is removed, to ensure that decision device can correctly recover initial data；2, the present invention can be completed at the same time symbol
Synchronous, carrier wave frequency deviation compensation and symbol judgement function, has the characteristics that simple in structure, functional.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in whole attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is a kind of theory structure schematic diagram of demodulator circuit applied to GFSK receivers in the present invention.
Fig. 2 is in the present invention when being influenced by carrier wave frequency deviation, and phase signal has been superimposed a DC component, by straight
Flow component estimating circuit locks carrier wave frequency deviation, and converges on the schematic diagram of a stationary value.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical scheme of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
Shown in reference picture 1, Fig. 2, the present invention provides a kind of demodulator circuits applied to GFSK receivers, including interpolation to filter
Wave device, the interpolation filter are used to phase signal obtaining the signal of one times of character rate；Timing Error Detector, it is described fixed
When error detector be used for the signal that is inputted according to interpolation filter and obtain timing error information；Loop filter, the loop
For filter for handling timing error information and inputting interpolation controller, the interpolation controller controls interpolation filter to base band
Signal finally allows the sampling clock of interpolater to converge on symbol clock into row interpolation, to complete transmitting terminal and receiving terminal
Sign synchronization further includes further preferably decision device and the estimating circuit of DC component, the estimating circuit profit of the DC component
Adjustment decision threshold is removed with the estimated value of DC component, to ensure that decision device can correctly recover initial data.The present invention's
Operation principle is：By input of the baseband signal of over-sampling after difference phase demodulation as Symbol Synchronization Circuit road, phase signal
The signal of one times of character rate is obtained after interpolation filter, then it is sent into Timing Error Detector and obtains timing error letter
Breath.Timing error enters interpolation controller by loop filter processing, and interpolation controller, which controls interpolation filter, believes base band
Number into row interpolation, the sampling clock of interpolater is finally allowed to converge on symbol clock, to complete the symbol of transmitting terminal and receiving terminal
Number synchronization.When being influenced by carrier wave frequency deviation, phase signal has been superimposed a DC component.So increasing direct current in loop
The estimating circuit of component removes adjustment decision threshold, to ensure that decision device can be recovered correctly using the estimated value of DC component
Initial data.
The present invention also provides a kind of construction methods applied to GFSK receiver demodulator circuits, include the following steps：
Step (1)：Interpolation calculating is carried out to phase signal, the wherein computational methods of interpolation can select linear interpolation or vertical
Square interpolation.
Step (2)：Value after calculating interpolation is timed control information detection, and wherein timing error information detects
Mode be：
Ted (n)=x (n) * d (n-1)-x (n-1) * d (n), wherein x (n)：N-th of output signal of interpolation device, d (n)：
N-th of output signal of decision device.
Step (3)：Timing error information is filtered using loop filter, loop filter is accumulated using ratio
Divide filtering；
Step (4)：Digital controlled oscillator is sent into the output of loop filter and does accumulation operations.
Step (5)：When digital controlled oscillator, which exports, to be overflowed, decimal time delay spacing u is obtained, and calculate corresponding interpolation system
Number, interpolation filter finally allows the sampling clock of interpolater to converge on symbol clock to input signal into row interpolation at this time, from
And complete the sign synchronization of transmitting terminal and receiving terminal.
Step (6)：When being influenced by carrier wave frequency deviation, phase signal has been superimposed a DC component, passes through direct current point
Amount estimating circuit locks carrier wave frequency deviation, and converges on a stationary value, and further preferably, DC component is estimated by decision device
Dynamic decision thresholding of the output of circuit as decision device is counted, hard decision is carried out to the output of interpolation filter, demodulates 0/1
Bit stream, to ensure that decision device can correctly recover initial data.
In the present invention, DC component estimating circuit is：Err (n)=x (n)-dc (n-1)-d (n), dc (n)=(1-
alpha)*dc(n-1)+err(n)*alpha.Wherein, x (n)：N-th of output signal of interpolation device, d (n)：The n-th of decision device
A output signal, dc (n-1) are the direct current component value estimated at the n-1 moment, and alpha is for controlling DC component estimating circuit
Bandwidth.With reference to shown in Fig. 2, when being influenced by carrier wave frequency deviation, phase signal has been superimposed a DC component, passes through direct current
Component estimating circuit locks carrier wave frequency deviation, and converges on a stationary value.
Sign synchronization, carrier wave frequency deviation compensates and symbol judgement relative in currently existing scheme, completing at the same time by the present invention
In the case of function, have the characteristics that it is simple in structure, functional, and by the estimated value of DC component go adjustment decision gate
Limit, to ensure that decision device can correctly recover initial data.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (9)
1. a kind of demodulator circuit applied to GFSK receivers, which is characterized in that including interpolation filter, the interpolation filter
For phase signal to be obtained the signal of one times of character rate；Timing Error Detector, the Timing Error Detector are used for root
The signal inputted according to interpolation filter obtains timing error information；Loop filter, the loop filter is for handling timing
Control information simultaneously inputs interpolation controller, and the interpolation controller controls interpolation filter to baseband signal into row interpolation, finally
The sampling clock of interpolater is allowed to converge on symbol clock, to complete the sign synchronization of transmitting terminal and receiving terminal.
2. a kind of demodulator circuit applied to GFSK receivers as described in claim 1, which is characterized in that further include decision device
With the estimating circuit of the estimating circuit of DC component, the DC component adjustment decision gate is gone using the estimated value of DC component
Limit, to ensure that decision device can correctly recover initial data.
3. a kind of construction method applied to GFSK receiver demodulator circuits, which is characterized in that include the following steps：
Step (1)：Interpolation calculating is carried out to phase signal；
Step (2)：Value after calculating interpolation is timed control information detection；
Step (3)：Timing error information is filtered using loop filter；
Step (4)：Digital controlled oscillator is sent into the output of loop filter and does accumulation operations；
Step (5)：When digital controlled oscillator, which exports, to be overflowed, decimal time delay spacing u is obtained, and calculate corresponding interpolation coefficient,
Interpolation filter finally allows the sampling clock of interpolater to converge on symbol clock to input signal into row interpolation at this time, to
Complete the sign synchronization of transmitting terminal and receiving terminal.
4. a kind of construction method applied to GFSK receiver demodulator circuits as claimed in claim 3, which is characterized in that also wrap
Include step (6)：When being influenced by carrier wave frequency deviation, phase signal has been superimposed a DC component, is estimated by DC component
Circuit locks carrier wave frequency deviation, and converges on a stationary value.
5. a kind of construction method applied to GFSK receiver demodulator circuits as claimed in claim 4, which is characterized in that step
(6) further include：By decision device using the output of DC component estimating circuit as the dynamic decision thresholding of decision device, interpolation is filtered
The output of wave device carries out hard decision, 0/1 bit stream is demodulated, to ensure that decision device can correctly recover initial data.
6. a kind of construction method applied to GFSK receiver demodulator circuits as claimed in claim 5, which is characterized in that described
In step (1)：The computational methods of interpolation can select linear interpolation or cube interpolation.
7. a kind of construction method applied to GFSK receiver demodulator circuits as claimed in claim 6, which is characterized in that described
In step (2), the mode of timing error information detection is：
Ted (n)=x (n) * d (n-1)-x (n-1) * d (n), wherein x (n)：N-th of output signal of interpolation device, d (n)：Judgement
N-th of output signal of device.
8. a kind of construction method applied to GFSK receiver demodulator circuits as claimed in claim 7, which is characterized in that described
In step (3), loop filter is filtered using proportional integration.
9. a kind of construction method applied to GFSK receiver demodulator circuits as claimed in claim 8, which is characterized in that described
DC component estimating circuit is：Err (n)=x (n)-dc (n-1)-d (n) dc (n)=(1-alpha) * dc (n-1)+err (n) *
Alpha, wherein x (n)：N-th of output signal of interpolation device, d (n)：N-th of output signal of decision device, dc (n-1) are n-1
The direct current component value that moment estimates, alpha are used to control the bandwidth of DC component estimating circuit.
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| CN108989260A (en) * | 2018-08-01 | 2018-12-11 | 清华大学 | The digital time synchronization method of modified and device based on Gardner |
| CN109462421A (en) * | 2018-10-22 | 2019-03-12 | 北京睿信丰科技有限公司 | Signal timing recovery method and recovery device, signal demodulating method and demodulating system |
| CN111447161A (en) * | 2020-04-03 | 2020-07-24 | 杭州易百德微电子有限公司 | Decision method and decision module |
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Application publication date: 20180720 |