CN108337011A - The construction method of Symbol Synchronization Circuit in GFSK receivers - Google Patents
The construction method of Symbol Synchronization Circuit in GFSK receivers Download PDFInfo
- Publication number
- CN108337011A CN108337011A CN201810040800.4A CN201810040800A CN108337011A CN 108337011 A CN108337011 A CN 108337011A CN 201810040800 A CN201810040800 A CN 201810040800A CN 108337011 A CN108337011 A CN 108337011A
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- Prior art keywords
- interpolation
- construction method
- synchronization circuit
- symbol synchronization
- gfsk
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The present invention provides the construction methods of the Symbol Synchronization Circuit in GFSK receivers, include the following steps：Step (1)：After removing DC component to phase signal, then carry out interpolation calculating；Step (2)：It is timed control information detection based on above-mentioned interpolation calculating；Step (3)：The timing error information detected is fed back into interpolation filter into row interpolation；Step (4)：Interpolation filter constantly adjusts the clock of sampling, to complete the synchronization to sending and receiving both ends symbol clock in GFSK receivers, the present invention first by baseband signal do difference phase demodulation processing, then by frame synchronization, go DC component frequency deviation compensate after again using it as the input of sign synchronization loop.Timing error constantly adjusts new sampled value by feeding back to interpolation filter after loop filter, and the sampling clock of interpolater is finally allowed to converge on symbol clock, to make the sign synchronization of transmitting terminal and receiving terminal.
Description
Technical field
The present invention relates to the Fast Symbol Synchronization fields in GFSK receivers, and in particular to the symbol in GFSK receivers is same
The construction method of step circuit.
Background technology
Often there is symbol time offset in the signal that wireless digital receiver receives in communication process.Therefore it needs logical
Symbol Synchronization Circuit is crossed to recover best sampled point.All-digital receiver can use fixed sample frequency, sampling clock
Mutual indepedent with symbol clock, the timing error that is obtained by Timing synchronization circuitry controls interpolation filter, is allowed to output symbol
Number optimum sampling point.
In general, Symbol Synchronization Circuit is by interpolation filter (Interpolator), Timing Error Detector CTiming
Error Detector), four parts such as loop filter (LPF) and digital controlled oscillator (NC0) are constituted.
Sampled signal extracts clocking error after interpolation, by Timing Error Detector, then filters off height through loop filter
Digital controlled oscillator is sent to generate the delay of a fractional value to control interpolation after frequency ingredient so that the data of interpolation can obtain most preferably
Decimal place time domain offset.The timing error that the timing loop obtains when starting can oscillation on large scale, with synchronous progress,
Error amount is finally stablized near a fixed value.When loop-locking, the output valve of the integral branch of loop filter can be received
It holds back in the error amount of transmitting-receiving two-end symbol clock.
Timing Error Detection algorithm common at present has door algorithm sooner or later, Muller-Mueller algorithms and Gardner
Algorithm etc..Wherein door algorithm works in 3 times of character rates sooner or later, so hardware spending is big；MM algorithms work in 1 times of symbol speed
Rate, but require first to complete carrier phase synchronization；And Gardner algorithms work in 2 times of character rates, and it is there are carrier waves
The case where frequency deviation, also can be normal, so the algorithm is most common inside above-mentioned three kinds of algorithms.
Articles of the Gardner at him《ABPSK_QPSKTiming-ErrorDetector for Sampled
Receivers》In propose Timing Error Detection algorithm.For continuous 3 sampled points of the sampled signal of twice of symbol rate, accidentally
The size of difference is determined by intermediate sampled point, and the direction of error is determined by the difference of former and later two sampled points.It is summarised as following
Formula：Timing_error=x (n-1/2) [x (n)-x (n-l)], wherein x (n), x (n-1/2) and x (n-1) are continuous respectively
3 sampled points, indicate r-th of symbol timing error.
In existing GFSK receivers scheme, it can pass through at difference phase demodulation first after receiving the GFSK signals of base band
Then reason utilizes sync byte to complete frame synchronization, theoretic optimum sampling point is finally obtained while completing frame synchronization, make
For the synchronised clock of symbol data.But since the precision of transmitting terminal and the clock of receiving terminal is all inevitably floated by temperature
The influence of shifting, so in practical applications, the optimum sampling point that frame synchronization obtains can not alignment symbology period always centre
Position can lead to the reduction of receiver demodulation performance with the accumulation of sampling clock error.
Invention content
In order to solve above-mentioned insufficient defect, the present invention provides the structure sides of the Symbol Synchronization Circuit in GFSK receivers
Method, the present invention by doing the processing of difference phase demodulation to baseband signal, then pass through frame synchronization, the frequency deviation of DC component are gone to compensate first
Afterwards again using it as the input of sign synchronization loop.Phase signal misses after interpolation filter is handled, then using it as timing
The input of difference detection.To asking to obtain the numerical value obtained per continuous three interpolations, by the difference of former and later two values as error transfer factor
Direction, size of the intermediate value as error transfer factor.Timing error is right by feeding back to interpolation filter after loop filter
New sampled value constantly adjusts, and finally allows the sampling clock of interpolater to converge on symbol clock, to make transmitting terminal and receiving terminal
Sign synchronization.
The present invention provides the construction methods of the Symbol Synchronization Circuit in GFSK receivers, include the following steps：
Step (1)：After removing DC component to phase signal, then carry out interpolation calculating；
Step (2)：It is timed control information detection based on above-mentioned interpolation calculating；
Step (3)：The timing error information detected is fed back into interpolation filter into row interpolation；
Step (4)：Interpolation filter constantly adjusts the clock of sampling, to complete to sending and connecing in GFSK receivers
Receive the synchronization of both ends symbol clock.
Above-mentioned construction method, wherein in the step (1)：By being obtained after carrying out difference phase demodulation processing to baseband signal
To phase signal.
Above-mentioned construction method, wherein in the step (1), traditional wave crest wave may be used in the estimation of DC component
The paddy detection estimation technique obtains, and the method that interpolation calculates can select linear interpolation or cube interpolation.
Above-mentioned construction method, wherein in the step (2), the mode of timing error information detection is：
Ted=phi (n-1/2) * [phi (n)-phi (n-1)], wherein phi (n) believe for the phase obtained after difference phase demodulation
Number.
Above-mentioned construction method, wherein in the step (3)：The loop filter uses the side of proportional integration filtering
Formula is filtered.
Above-mentioned construction method, wherein the step (3) is specially：The timing error information detected is passed through into loop
Filter feedback is to interpolation filter into row interpolation.
Above-mentioned construction method, wherein the step (3) is specially：By loop filter to above-mentioned timing error
Information, which is filtered and the output of filtered data is sent to digital controlled oscillator, does accumulation operations, then calculates corresponding insert
Value coefficient.
Above-mentioned construction method, wherein the calculating process of wherein interpolation coefficient is：When digital controlled oscillator, which exports, to be overflowed,
Obtain decimal time delay spacing u, and calculate corresponding interpolation coefficient, at this moment interpolation filter to input signal into row interpolation.
Above-mentioned construction method, wherein for the numerical value that every continuous three interpolations obtain, made by the difference of former and later two values
For the direction of error transfer factor, size of the intermediate value as error transfer factor.The Timing Error Detection requires former and later two symbols to send out
After raw zero passage, timing error after could detecting.
The present invention has the following advantages：1, the present invention after carrying out difference phase demodulation processing to baseband signal by obtaining phase letter
Number, after phase signal removes DC component, after being handled using interpolation filter, then using it as the defeated of Timing Error Detection
Enter.Because the interpolater carries out interpolation for the phase signal of real number field, than traditional interpolater for complex signal
Reduce hardware complexity.For the numerical value that every continuous three interpolations obtain, by the difference of former and later two values as error transfer factor
Direction, size of the intermediate value as error transfer factor.After the Timing Error Detection requires former and later two symbols that zero passage occurs,
Timing error after capable of detecting.The initial data of GFSK transmitting terminals is usually constructed with by whitening processing, it is possible to ensure front and back symbol
Between number there is frequent zero passage phenomenon to occur.Simultaneously before carrying out zero passage detection, the direct current point of carrier wave frequency deviation introducing is eliminated
Amount, so timing error device can not be influenced by carrier wave frequency deviation.The timing error detected after loop filter by feeding back
It finally completes to constantly be adjusted to the sampling clock of new sampled value to interpolation filter and sends and receives both ends symbol clock
Synchronization；2, there is no include in the loop, so reducing the complexity of entire synchronization loop difference phase demodulation module by the present invention
Degree is conducive to the optimization adjustment of sign synchronization loop loop filter parameter in practical application.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in whole attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is the theory structure schematic diagram of the construction method of the Symbol Synchronization Circuit in GFSK receivers in the present invention.
Fig. 2 is the symbol clock error amount schematic diagram that Symbol Synchronization Circuit detects in the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical scheme of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
Shown in reference picture 1, Fig. 2, the present invention provides the construction methods of the Symbol Synchronization Circuit in GFSK receivers, including
Following steps：
Step (1)：After removing DC component to phase signal, then interpolation calculating is carried out, including by believing base band
The estimation for number carrying out obtaining after difference phase demodulation processing phase signal and DC component may be used traditional Wave crest and wave trough and detect
The estimation technique obtains, and the method that interpolation calculates can select linear interpolation or cube interpolation.
Step (2)：It is timed control information detection based on above-mentioned interpolation calculating, wherein timing error information detects
Mode is：
Ted=phi (n-1/2) * [phi (n)-phi (n-1)], wherein phi (n) believe for the phase obtained after difference phase demodulation
Number.
Step (3)：The timing error information detected is fed back into interpolation filter into row interpolation, further, will be detected
To timing error information interpolation filter is fed back into row interpolation by loop filter, further preferably, filtered by loop
Wave device, which is filtered above-mentioned timing error information and the output of filtered data is sent to digital controlled oscillator, is cumulative behaviour
To make, then calculates corresponding interpolation coefficient, wherein loop filter is filtered by the way of proportional integration filtering, with
And the calculating process of interpolation coefficient is：When digital controlled oscillator, which exports, to be overflowed, decimal time delay spacing u is obtained, and is calculated corresponding
Interpolation coefficient, at this moment interpolation filter to input signal into row interpolation；
Step (4)：Interpolation filter constantly adjusts the clock of sampling, to complete to sending and connecing in GFSK receivers
Receive the synchronization of both ends symbol clock, that is to say, that completed frame synchronization before sign synchronization, interpolater is recovered
Sampled data can be routed directly to the demodulator circuit of rear class, with reference to shown in Fig. 2, for the numerical value that every continuous three interpolations obtain,
Direction by the difference of former and later two values as error transfer factor, size of the intermediate value as error transfer factor.The timing error is examined
After survey requires former and later two symbols that zero passage occurs, timing error after could detecting.
The present invention relative in existing GFSK receivers scheme, receive can pass through first after the GFSK signals of base band it is poor
Divide phase demodulation processing, then sync byte is utilized to complete frame synchronization, is finally obtained while completing frame synchronization theoretic best
Sampled point, the synchronised clock as symbol data.But all inevitably due to the precision of transmitting terminal and the clock of receiving terminal
Subject to temperature drift, so in practical applications, the optimum sampling point that frame synchronization obtains can not alignment symbology always
The centre position in period can lead to the reduction of receiver demodulation performance with the accumulation of sampling clock error.And the present invention passes through
By the baseband signal of GFSK after the processing of difference phase demodulation, after the frequency deviation compensation for removing DC component, it is same to be re-used as symbol
Walk the input of loop.Phase signal is after interpolation filter post-processes, then using it as the input of Timing Error Detection.To asking
The numerical value obtained per continuous three interpolations, the direction by the difference of former and later two values as error transfer factor are obtained, intermediate value is made
For the size of error transfer factor.Timing error constantly adjusts new sampled value by feeding back to interpolation filter after loop filter,
It, can be to avoid above-mentioned problem to complete the synchronization to sending and receiving both ends symbol clock in GFSK receivers；And this
There is no include in the loop, so reducing the complexity of entire synchronization loop, to be conducive to reality difference phase demodulation module for invention
The optimization adjustment of sign synchronization loop loop filter parameter in the application of border, and interpolater is the phase for real number field
Signal carries out interpolation, also reduces hardware complexity than traditional interpolater for complex signal.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (9)
- The construction method of Symbol Synchronization Circuit in 1.GFSK receivers, which is characterized in that include the following steps：Step (1)：After removing DC component to phase signal, then carry out interpolation calculating；Step (2)：It is timed control information detection based on above-mentioned interpolation calculating；Step (3)：The timing error information detected is fed back into interpolation filter into row interpolation；Step (4)：Interpolation filter constantly adjusts the clock of sampling, to complete to sending and receiving two in GFSK receivers Hold the synchronization of symbol clock.
- 2. the construction method of the Symbol Synchronization Circuit in GFSK receivers as described in claim 1, which is characterized in that the step Suddenly in (1)：By obtaining phase signal after carrying out difference phase demodulation processing to baseband signal.
- 3. the construction method of the Symbol Synchronization Circuit in GFSK receivers as described in claim 1, which is characterized in that the step Suddenly in (1), the estimation of DC component may be used traditional Wave crest and wave trough detection estimation technique and obtain, and the method that interpolation calculates can be with Select linear interpolation or cube interpolation.
- 4. the construction method of the Symbol Synchronization Circuit in GFSK receivers as claimed in claim 3, which is characterized in that the step Suddenly in (2), the mode of timing error information detection is：Ted=phi (n-1/2) * [phi (n)-phi (n-1)], wherein phi (n) are obtained phase signal after difference phase demodulation.
- 5. the construction method of the Symbol Synchronization Circuit in GFSK receivers according to any one of claims 1-4, feature exist In the step (3) is specially：The timing error information detected is fed back to interpolation filter by loop filter to carry out Interpolation.
- 6. the construction method of the Symbol Synchronization Circuit in GFSK receivers as claimed in claim 5, which is characterized in that the step Suddenly in (3)：The loop filter is filtered by the way of proportional integration filtering.
- 7. the construction method of the Symbol Synchronization Circuit in GFSK receivers as claimed in claim 5, which is characterized in that the step Suddenly (3) are specially：Above-mentioned timing error information is filtered by loop filter and send the output of filtered data Enter to digital controlled oscillator and do accumulation operations, then calculates corresponding interpolation coefficient.
- 8. the construction method of the Symbol Synchronization Circuit in GFSK receivers as claimed in claim 7, which is characterized in that wherein insert The calculating process of value coefficient is：When digital controlled oscillator, which exports, to be overflowed, decimal time delay spacing u is obtained, and calculates corresponding insert Value coefficient, at this moment interpolation filter to input signal into row interpolation.
- 9. the construction method of the Symbol Synchronization Circuit in GFSK receivers as claimed in claim 8, which is characterized in that for every The numerical value that continuous three interpolations obtain, the direction by the difference of former and later two values as error transfer factor, intermediate value is as error The size of adjustment, after which requires former and later two symbols that zero passage occurs, timing error after could detecting.
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| CN201810040800.4A CN108337011A (en) | 2018-01-16 | 2018-01-16 | The construction method of Symbol Synchronization Circuit in GFSK receivers |
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| CN201810040800.4A CN108337011A (en) | 2018-01-16 | 2018-01-16 | The construction method of Symbol Synchronization Circuit in GFSK receivers |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111935046A (en) * | 2020-10-12 | 2020-11-13 | 湖南国科锐承电子科技有限公司 | Low-complexity frequency shift keying signal symbol rate estimation method |
| CN112134825A (en) * | 2020-09-21 | 2020-12-25 | 易兆微电子(杭州)股份有限公司 | Low-complexity high-performance GFSK baseband timing synchronization method |
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| US20030043898A1 (en) * | 2001-09-05 | 2003-03-06 | Acer Laboratories, Inc. | Read channel apparatus and method for an optical storage system |
| US20050141660A1 (en) * | 2003-12-01 | 2005-06-30 | Lg Electronics Inc. | Symbol timing recovery and broadcast receiver using the same |
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| CN112134825A (en) * | 2020-09-21 | 2020-12-25 | 易兆微电子(杭州)股份有限公司 | Low-complexity high-performance GFSK baseband timing synchronization method |
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Application publication date: 20180727 |