CN101448315B - Frame clock synchronization method and device - Google Patents
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Abstract
本发明实施例公开了一种帧时钟同步方法和设备，该方法包括：根据接收的全球定位系统GPS信息，生成和GPS时钟同步的GPS秒脉冲；利用所述GPS秒脉冲调整晶体振荡器，使所述晶体振荡器输出的时钟信号和所述GPS秒脉冲保持同步；对所述晶体振荡器输出的时钟信号进行分频，所述分频后的时钟信号为帧时钟。本发明实施例根据接收的GPS信息，通过对晶体振荡器输出的时钟信号的调整，生成与GPS秒脉冲同步的帧时钟，达到了帧时钟同步的效果。
The embodiment of the present invention discloses a frame clock synchronization method and device. The method includes: generating a GPS second pulse synchronized with the GPS clock according to the received GPS information; using the GPS second pulse to adjust the crystal oscillator so that The clock signal output by the crystal oscillator is synchronized with the GPS second pulse; the clock signal output by the crystal oscillator is frequency-divided, and the frequency-divided clock signal is a frame clock. According to the received GPS information, the embodiment of the present invention generates a frame clock synchronized with the GPS second pulse by adjusting the clock signal output by the crystal oscillator, thereby achieving the effect of frame clock synchronization.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of frame clock synchronizing method and equipment.
Background technology
In the prior art, be asynchronous mutually between the BTS (Base Transceiver Station, base transceiver station) among the GSM (Global System for Mobile communications, global system for mobile communications).In asynchronous network, co-channel interference or adjacent the interference frequently are uncontrollable, can't realize DFCA (Dynamic Frequency and Channel Allocation, dynamic frequency and channel allocation) function; Simultaneously, asynchronous network can cause ICC (Interference Cancellation Combining, the Interference Cancellation merging) performance of technology and SAIC (Single Antana Interference Cancellation, single antenna Interference Cancellation) technology significantly descends.For solving above-mentioned performance issue, need the air interface synchronization between the realization BTS.Owing in GSM, be unit transmission data, need to use the frame clock to indicate the beginning of each frame data transmission with the frame.Realize the frame clock synchronization between the BTS, promptly realized the air interface synchronization between the BTS.
GPS (Global Positioning System, global positioning system) be one by 24 satellite systems that satellite is formed covering the whole world, can guarantee at any time, a bit can observe 4 satellites simultaneously arbitrarily on the earth, to guarantee that satellite can collect the longitude and latitude and the height of this observation station, so that realize functions such as navigation, location, time service.
The inventor is in practice process, and there are the following problems at least to find prior art:
In the method for synchronous of the whole network BTS frame clock of the prior art, abnormal protection is perfect inadequately, and implementation is loaded down with trivial details.
Summary of the invention
The embodiment of the invention provides a kind of frame clock synchronizing method and equipment, has improved the method for frame clock synchronization.
The embodiment of the invention proposes a kind of frame clock synchronizing method, comprising:
According to the global position system GPS information that receives, generate and the synchronous GPS pulse per second (PPS) of gps clock;
Utilize described GPS pulse per second (PPS) to adjust crystal oscillator, the clock signal of described crystal oscillator output and described GPS pulse per second (PPS) are kept synchronously;
Clock signal to described crystal oscillator output is carried out frequency division, and the clock signal behind the described frequency division is the frame clock, and described frame clock and described GPS pulse per second (PPS) are synchronous;
Obtain the phase difference between described frame clock and the described GPS pulse per second (PPS), according to described phase difference, adjust the phase place of described frame clock, make described frame clock consistent with phase place between the described GPS pulse per second (PPS), the phase place of the described frame clock of described adjustment comprises:
If the phase difference between frame clock and the GPS pulse per second (PPS) less than first phase threshold, every the clock cycle of first setting-up time to the frame clock adjustment first setting number crystal oscillator, is zero up to phase difference then; If the phase difference between frame clock and the GPS pulse per second (PPS) is greater than first phase threshold, and less than second phase threshold, then the frame clock was adjusted for second clock cycle of setting the number crystal oscillator every second setting-up time; If, then adjusting the rising edge of frame clock greater than second phase threshold, the phase difference between frame clock and the GPS pulse per second (PPS) aligns with the rising edge of GPS pulse per second (PPS).
The embodiment of the invention also proposes a kind of veneer, is used for and global position system GPS star card connection, comprising: central processor CPU, frame clock synchronization apparatus, crystal oscillator and bus, wherein,
Described CPU is connected with institute frame clock synchronization apparatus by described bus, and described frame clock synchronization apparatus is connected with described crystal oscillator by described bus;
Described frame clock synchronization apparatus, be used to receive the GPS pulse per second (PPS) that described GPS star card sends, utilize described GPS pulse per second (PPS), adjust described crystal oscillator by described CPU, make the clock signal and the described GPS pulse per second (PPS) of described crystal oscillator output synchronous, obtain the clock signal of described crystal oscillator output then, to the described clock signal frequency division that obtains, the clock signal after the described frequency division is the frame clock;
Obtain the phase difference between described frame clock and the described GPS pulse per second (PPS), according to described phase difference, adjust the phase place of described frame clock, make described frame clock consistent with phase place between the described GPS pulse per second (PPS), the phase place of the described frame clock of described adjustment comprises:
If the phase difference between frame clock and the GPS pulse per second (PPS) less than first phase threshold, every the clock cycle of first setting-up time to the frame clock adjustment first setting number crystal oscillator, is zero up to phase difference then; If the phase difference between frame clock and the GPS pulse per second (PPS) is greater than first phase threshold, and less than second phase threshold, then the frame clock was adjusted for second clock cycle of setting the number crystal oscillator every second setting-up time; If, then adjusting the rising edge of frame clock greater than second phase threshold, the phase difference between frame clock and the GPS pulse per second (PPS) aligns with the rising edge of GPS pulse per second (PPS);
Described crystal oscillator is used for according to certain frequency clock signal.
The technical scheme of the embodiment of the invention has the following advantages, because according to the GPS information that receives, the adjustment by to the clock signal of crystal oscillator output generates and the synchronous frame clock of GPS pulse per second (PPS), thereby, reached the effect of frame clock synchronization.
Description of drawings
A kind of frame clock synchronizing method flow chart that Fig. 1 provides for the embodiment of the invention one;
The frame clock that Fig. 2 provides for the embodiment of the invention one and the phase relation schematic diagram of GPS pulse per second (PPS);
A kind of frame clock synchronizing method flow chart that Fig. 3 provides for the embodiment of the invention two;
A kind of single plate structure schematic diagram that Fig. 4 provides for the embodiment of the invention three.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Embodiment one
As shown in Figure 1, a kind of frame clock synchronizing method flow chart for the embodiment of the invention one provides may further comprise the steps:
For example, by the gps antenna of the gps signal receiver on the BTS, can receive the GPS information of satellite transmits, this GPS information comprises information such as GPS absolute time and gps clock.GPS information according to gps antenna receives can generate the GPS pulse per second (PPS) synchronous with gps clock, and the cycle of GPS pulse per second (PPS) is 1 second.The time interval that receives GPS information can be each second once.
Crystal oscillator is adjusted in the GPS pulse per second (PPS) that utilizes step 101 to obtain, and the clock signal of crystal oscillator output and GPS pulse per second (PPS) are kept synchronously.
Under a kind of scene, a kind of synchronous method comprises: utilize the GPS pulse per second (PPS) as clock signal, the high level signal that generates the duration and be a plurality of GPS pulse per second (PPS) cycles is as the high level window.
The high level window as enable signal, is obtained the actual number of the clock signal that crystal oscillator exports in the high level window; Obtain the actual number of the clock signal of output in the high level window and the difference between the preset value, change the frequency of the clock signal of crystal oscillator output according to difference, make the actual number of the clock signal that crystal oscillator exports in the high level window equal preset value, crystal oscillator after adjusting frequency, the clock signal of crystal oscillator output will keep synchronously with the GPS pulse per second (PPS) in the ordinary course of things.
Above-mentioned crystal oscillator can be the 13MHz crystal oscillator, but be not limited thereto.13MHz crystal oscillator in the gsm system generally adopts OCXO (Oven Controlled Crystal Oscillator, Oven voltage Control Oscillator), and the impossible absolutely accurate of the frequency of the clock signal of output has certain deviation.Therefore, the mode that can count by pulse per second (PPS) to GPS, generate the high level window of a lasting high level signal, the duration of this high level window is with corresponding to the count value of GPS pulse per second (PPS), when the count value to the GPS pulse per second (PPS) was 260 times, the duration of this high level window was 260 seconds; Can use the enable signal of this high level window that continues 260 seconds as counter, clock signal counting to the output of 13MHz crystal oscillator, after counting was finished in 260 seconds, automatically latch count value, obtain the count value of the clock signal of 13MHz crystal oscillator output in 260 seconds, obtain the difference between the preset value of the clock signal number that this count value and crystal oscillator exported in 260 seconds according to the count value of obtaining, can judge the frequency of the clock signal that the 13MHz crystal oscillator is exported and the difference of pulse per second (PPS), and the stability of the frequency of 13MHz crystal oscillator clock signal, by changing difference and obtain the controlled quentity controlled variable that changes the 13MHz crystal oscillator frequency, the actual number that above-mentioned difference equals the clock signal of output in the high level window deducts the difference between the preset value.If this difference is then obtained the FREQUENCY CONTROL amount of the clock signal that reduces crystal oscillator output for just; If this difference for negative, is then obtained the controlled quentity controlled variable of the frequency of the clock signal that increases crystal oscillator output.The controlled quentity controlled variable of this 13MHz crystal oscillator is input to the control end of 13MHz crystal oscillator, changes the frequency of the clock signal of 13MHz crystal oscillator output, keep synchronously up to clock signal that makes the output of 13MHz crystal oscillator and GPS pulse per second (PPS).
The controlled quentity controlled variable of above-mentioned crystal oscillator can be voltage-controlled value, when controlled quentity controlled variable is voltage-controlled value, the control end of above-mentioned crystal oscillator is voltage-controlled end, need (Digital to Analog Converter through DAC, digital to analog converter) voltage-controlled value is carried out digital-to-analogue conversion, the control voltage that is converted to is input to the voltage-controlled end of crystal oscillator, and the voltage-controlled value before the conversion is a digital quantity, and the control voltage after the conversion is analog quantity.
By being carried out frequency division, the clock signal of crystal oscillator output handles, clock signal after the frequency division and GPS pulse per second (PPS) keep synchronously, thereby can be with the clock signal after the frequency division as the frame clock, be the integral multiple relation between the frequency of the clock signal of the frequency of frame clock and crystal oscillator output.Because the clock signal of crystal oscillator output is by after the adjustment of step 102, holding frequency is stable, and it is synchronous with the GPS pulse per second (PPS), therefore, the frame clock that this step generates is also synchronous with the GPS pulse per second (PPS), at set intervals, the rising edge of frame clock aligns with the rising edge of GPS pulse per second (PPS), and the mode of alignment can be referring to as Fig. 2.Can make the frame clock on the different B TS all synchronous by above-mentioned flow process, thereby reach synchronous purpose between the frame clock on the different B TS with the GPS pulse per second (PPS).
The technical scheme of the embodiment of the invention has following beneficial effect, and according to the GPS information that receives, the adjustment by to the clock signal of crystal oscillator output generates and the synchronous frame clock of GPS pulse per second (PPS), has reached the effect of frame clock synchronization.
Embodiment two
As shown in Figure 3, a kind of frame clock synchronizing method flow chart for the embodiment of the invention two provides may further comprise the steps:
For example, by the gps antenna of the gps signal receiver on the BTS, can receive the GPS information of satellite transmits, this GPS information comprises information such as GPS absolute time and gps clock.GPS information according to gps antenna receives can generate the GPS pulse per second (PPS) synchronous with gps clock, and the cycle of GPS pulse per second (PPS) is 1 second.
Utilize GPS pulse per second (PPS) that step 201 obtains as clock signal, GPS pulse per second (PPS) number is counted the high level signal of high level window for continuing of generation, the duration of this high level signal is with corresponding to the count value of GPS pulse per second (PPS) number.Because the cycle of GPS pulse per second (PPS) is 1 second, the duration length of high level signal equates with the count value of GPS pulse per second (PPS) number.
Behind step 202 generation high level window, can use the enable signal of this high level window as the counter of crystal oscillator, the clock signal number that crystal oscillator is exported under this high level window is counted.Because the counter of crystal oscillator is timing under the situation of high level at enable signal, at enable signal is to stop timing under the low level situation, therefore, the gate time of the counter of crystal oscillator is the duration of high level window, can obtain the actual number of the clock signal that crystal oscillator exports in the high level window.
Because crystal oscillator has self intrinsic output signal frequency, can obtain the clock signal number that crystal oscillator is exported according to this frequency under the high level window, so this preset value theoretical value that can obtain for natural frequency and the high level window calculation according to crystal oscillator.Use this preset value and crystal oscillator counter count value relatively after, obtain under the high level window count value and the difference of crystal oscillator between the preset value of the clock signal number of exporting under the high level window to the clock signal number, for example, this difference actual number of equaling the clock signal of output in the high level window deducts the difference between the preset value.If this difference is obtained the FREQUENCY CONTROL amount of the clock signal that reduces crystal oscillator output for just; If this difference for negative, is obtained the controlled quentity controlled variable of the frequency of the clock signal that increases crystal oscillator output.Utilize controlled quentity controlled variable to change the frequency of the clock signal of crystal oscillator output, actual number up to the clock signal that crystal oscillator is exported in the high level window equals preset value, when difference is after zero, the clock signal of crystal oscillator output and GPS pulse per second (PPS) are kept synchronously.
The controlled quentity controlled variable of above-mentioned crystal oscillator can be voltage-controlled value, when controlled quentity controlled variable is voltage-controlled value, the control end of above-mentioned crystal oscillator is voltage-controlled end, need voltage-controlled value to be carried out digital-to-analogue conversion through DAC, the control voltage that is converted to is input to the voltage-controlled end of crystal oscillator, voltage-controlled value before the conversion is a digital quantity, and the control voltage after the conversion is analog quantity.
Handle by the frequency division to the clock signal of crystal oscillator output, the clock signal of resulting crystal oscillator output is the frame clock synchronous with the GPS pulse per second (PPS).As shown in Figure 2, be the integral multiple relation between the frequency of the clock signal of the frequency of frame clock and crystal oscillator output.Because the clock signal of crystal oscillator output keeps stable, and synchronous with the GPS pulse per second (PPS), therefore, the frame clock that this step generates is also synchronous with the GPS pulse per second (PPS), and at set intervals, the rising edge of frame clock aligns with the rising edge of GPS pulse per second (PPS).
Under a kind of application scenarios, present embodiment also can further comprise the steps.
After utilizing step 205 delta frame clock, can obtain the phase difference between frame clock and the GPS pulse per second (PPS) by comparing the phase relation of frame clock and GPS pulse per second (PPS).Crystal oscillator is generally OCXO in the embodiment of the invention, and the clock signal of output may be inaccurate, has certain deviation.If deviation does not appear in the clock signal of crystal oscillator output, then at set intervals, the rising edge of frame clock aligns with the rising edge of GPS pulse per second (PPS), and the time interval between the adjacent rising edge alignment constantly is to homoperiodic, and this is to being made as homoperiodic 3 seconds; If deviation appears in the clock signal of crystal oscillator output, then at the rising edge of frame clock when the next one after the rising edge of GPS pulse per second (PPS) aligns arrived to homoperiodic, there is certain phase difference between the rising edge of the rising edge of frame clock and GPS pulse per second (PPS), phase difference between the rising edge of the frame clock of this moment and the rising edge of GPS pulse per second (PPS) is the phase difference between frame clock and the GPS pulse per second (PPS).
In order to keep the stability of frame clock, guarantee the synchronous of frame clock and GPS pulse per second (PPS), can be after frame clock and GPS pulse per second (PPS) initial synchronisation, detect frame clock and GPS pulse per second (PPS) at set intervals, obtain the phase difference between frame clock and the GPS pulse per second (PPS), for example, sense cycle can be 30 seconds.
Obtain phase difference between frame clock and the GPS pulse per second (PPS) according to step 206, can adjust the phase place of frame clock.The phase place of above-mentioned adjustment frame clock specifically comprises: whether the phase difference that determining step 206 obtains is greater than zero; If the phase difference of frame clock and GPS pulse per second (PPS) greater than zero, is then adjusted the phase place of frame clock, make that the phase difference of frame clock and GPS pulse per second (PPS) is zero.
According to the phase difference between frame clock and the GPS pulse per second (PPS), can delta frame clock adjustment information, this frame clock adjustment information comprises adjustment order of frame clock and frame clock adjusted value; According to frame clock adjustment information, can adjust the phase place of frame clock, realize closed-loop control to the phase difference between frame clock and the GPS pulse per second (PPS), making the phase difference between frame clock and the GPS pulse per second (PPS) is zero, the adjustment time can be 30 seconds.Phase difference between direct corresponding frame clock of this frame clock adjustment information and the GPS pulse per second (PPS).
The phase place of above-mentioned adjustment frame clock can comprise: if the phase difference between frame clock and the GPS pulse per second (PPS) less than first phase threshold, every the clock cycle of first setting-up time to the frame clock adjustment first setting number crystal oscillator, is zero up to phase difference then; If the phase difference between frame clock and the GPS pulse per second (PPS) is greater than first phase threshold, and less than second phase threshold, then the frame clock was adjusted for second clock cycle of setting the number crystal oscillator every second setting-up time; If, then adjusting the rising edge of frame clock greater than second phase threshold, the phase difference between frame clock and the GPS pulse per second (PPS) aligns with the rising edge of GPS pulse per second (PPS).Under a kind of concrete application scenarios, the crystal oscillator in the embodiment of the invention can be the 13MHz crystal oscillator, and first phase threshold is the clock cycle of 144 13MHz crystal oscillators, and first setting-up time is a frame clock cycle, and the first setting number is one; Second phase threshold is the clock cycle of 30000 13MHz crystal oscillators, and second setting-up time is 10 seconds, and the second setting number is 48, and the clock cycle of 48 13MHz crystal oscillators is 48/13us, i.e. 1 bit of eating dishes without rice or wine in the gsm system.
In conjunction with above-mentioned principle, step to the phase place of adjusting the frame clock is described further: if detect in 30 seconds the phase difference between the frame clock and GPS pulse per second (PPS) less than the clock cycle of 144 13MHz crystal oscillators, can be in ensuing 30 seconds, the clock periodicity of the 13MHz crystal oscillator of a frame clock cycle correspondence is adjusted one in each frame clock cycle, up to phase difference is zero, this adjustment mode can be for increasing or reduce the phase place of frame clock, and is corresponding with the phase difference between frame clock and the GPS pulse per second (PPS); If detect in 30 seconds the phase difference between the frame clock and GPS pulse per second (PPS) greater than the clock cycle of 144 13MHz crystal oscillators, and less than the clock cycle of 30000 13MHz crystal oscillators, can every 10 seconds by the BIT that eats dishes without rice or wine to a gsm system of frame clock fine setting, adjust continuously 3 times; If detect in 30 seconds the phase difference between the frame clock and GPS pulse per second (PPS) greater than the clock cycle of 30000 13MHz crystal oscillators; the rising edge that can directly adjust the frame clock aligns with the rising edge of GPS pulse per second (PPS); this adjustment can be in morning 2～4 be carried out, and avoids the influence to normal traffic.
The technical scheme of the embodiment of the invention has the following advantages, because according to the GPS information that receives, by adjustment to the clock signal of crystal oscillator output, the delta frame clock, and the phase difference between detection frame clock and the GPS pulse per second (PPS), the phase place of the frame clock that generates according to this phase difference adjustment makes the frame clock of generation and GPS pulse per second (PPS) synchronous, reaches the effect of the frame clock synchronization among the different B TS.
Embodiment three
As shown in Figure 4, a kind of single plate structure schematic diagram for the embodiment of the invention three provides comprises: CPU (Central Process Unit, central processing unit) 310, frame clock synchronization apparatus 320, crystal oscillator 330 and bus, wherein,
Frame clock synchronization apparatus 320, be used to receive the GPS pulse per second (PPS) that GPS star card produces, utilize the stability of GPS pulse per second (PPS), adjust crystal oscillator 330 by CPU 310, make the clock signal and the GPS pulse per second (PPS) of crystal oscillator 330 outputs synchronous, obtain the clock signal of crystal oscillator 330 outputs then, to the clock signal frequency division that obtains, the clock signal after the frequency division is the frame clock.
For example, the GPS star cartoon on the BTS is crossed the GPS information that gps antenna receives satellite transmits, generates the GPS pulse per second (PPS), and this GPS information comprises information such as GPS absolute time and gps clock.The cycle of GPS pulse per second (PPS) is 1 second, the time interval that GPS information is received in the clamping of GPS star can be each second once.
Frame clock synchronization apparatus 320 is used for the GPS pulse per second (PPS) that receives is counted, and generates the high level window, the high level signal of this high level window for continuing, and the duration of this high level window is with corresponding to the count value of GPS pulse per second (PPS).Frame clock synchronization apparatus 320 also is used to use the enable signal of the high level window of generation as the counter of crystal oscillator 330 is counted in the GPS pulse per second (PPS), to the clock signal counting of crystal oscillator 330 outputs.
Frame clock synchronization apparatus 320, being used for that also the clock signal of crystal oscillator 330 outputs is carried out frequency division handles, generating the synchronous frame clock of exporting with crystal oscillator 330 of clock signal, is the integral multiple relation between the frequency of the clock signal of the frequency of frame clock and crystal oscillator 330 outputs.Because the clock signal holding frequency of crystal oscillator 330 outputs is stable, and synchronous with the GPS pulse per second (PPS), therefore, the frame clock that frame clock synchronization apparatus 320 generates is also synchronous with the GPS pulse per second (PPS), at set intervals, the rising edge of frame clock aligns with the rising edge of GPS pulse per second (PPS).Above-mentioned frame clock synchronization apparatus 320 can be the FPGA of EP1C4 model, also can be programmable logic device PLD, be not limited to the above device of enumerating.
Above-mentioned crystal oscillator 330 can be the 13MHz crystal oscillator, but be not limited thereto.13MHz crystal oscillator in the gsm system generally adopts OCXO, and the impossible absolutely accurate of the frequency of the clock signal of output has certain deviation.Therefore, the mode that frame clock synchronization apparatus 320 can be counted by the pulse per second (PPS) to GPS, the high level window of the high level signal that to generate a duration be several pulse per second (PPS) cycles, the duration of this high level window is with corresponding to the count value of GPS pulse per second (PPS), for example, when the count value to the GPS pulse per second (PPS) was 260 times, the duration of this high level window was 260 seconds; Frame clock synchronization apparatus 320 can use the enable signal of this high level window that continues 260 seconds as counter, clock signal counting to the output of 13MHz crystal oscillator, after counting was finished in 260 seconds, automatically latch count value, CPU310 obtains the count value of the clock signal of 13MHz crystal oscillator output in 260 seconds.CPU 310 reads and handles the count value of the clock signal of the 13MHz crystal oscillator output of latching, judge the accuracy of the frequency of the clock signal that the 13MHz crystal oscillator is exported, generate the controlled quentity controlled variable of the frequency that changes the 13MHz crystal oscillator, and this controlled quentity controlled variable is input to the input of 13MHz crystal oscillator, adjust the frequency of the clock signal of 13MHz crystal oscillator output, itself and GPS pulse per second (PPS) are kept synchronously.
The model of CPU 310 can be MPC860, but is not limited thereto.
In order to keep the stability of frame clock, guarantee the synchronous of frame clock and GPS pulse per second (PPS), CPU 310 can be after frame clock and GPS pulse per second (PPS) initial synchronisation, at set intervals by and the interface of frame clock synchronization apparatus 320 read phase difference between frame clock and the GPS pulse per second (PPS), can be 30 seconds the blanking time of reading phase difference.
Preferably, above-mentioned veneer also can comprise:
The controlled quentity controlled variable of crystal oscillator 330 can be voltage-controlled value, and when controlled quentity controlled variable was voltage-controlled value, the control end of above-mentioned crystal oscillator 330 was voltage-controlled end.The voltage-controlled value of the crystal oscillator 330 that frame clock synchronization apparatus 320 will obtain from CPU 310 is input to the input of DAC 340, voltage-controlled value by 340 pairs of crystal oscillators 330 of DAC is carried out digital-to-analogue conversion, the control voltage that is converted to is input to the voltage-controlled end of crystal oscillator 330, voltage-controlled value before the conversion is a digital quantity, and the control voltage after the conversion is analog quantity.
Preferably, above-mentioned frame clock synchronization apparatus 320 under a kind of application scenarios, can comprise: first counting module 321, high level window module 322, second counting module 323, notification module 324, frequency regulation block 325 and frequency division module 326, wherein,
High level window module 322, being used for generating the duration according to first counting module 321 is that the high level signal in a plurality of GPS pulse per second (PPS) cycles is as the high level window.
Correspondingly, above-mentioned CPU 310, be used to read the count value of second counting module 323, obtain count value and the difference of crystal oscillator 330 between the preset value of the clock signal number of exporting under the high level window to the clock signal number, utilize this difference to adjust the frequency of the clock signal of crystal oscillator 330 outputs, make the frequency of the clock signal of crystal oscillator 330 outputs keep stable.
Preferably, above-mentioned frame clock synchronization apparatus 320, also can further comprise: detection module 327, phase difference acquisition module 328 and phase difference adjusting module 329, detection module 327 is connected with phase difference acquisition module 328, phase difference acquisition module 328 is connected with phase difference adjusting module 329, wherein
Phase difference acquisition module 328 is used to obtain frame clock that frequency division module 326 obtains and the phase difference between the GPS pulse per second (PPS).
Phase difference adjusting module 329 is used to adjust the phase place of the frame clock behind frequency division module 326 frequency divisions, makes the phase place of the frame clock behind frequency division module 326 frequency divisions consistent with phase place between the GPS pulse per second (PPS).
The phase difference that detection module 327 detects between frame clock and the GPS pulse per second (PPS), phase difference between frame clock and GPS pulse per second (PPS) is during less than first phase threshold, phase difference adjusting module 329 is zero every the clock cycle of first setting-up time to the frame clock adjustment first setting number crystal oscillator 330 up to phase difference.
Under a kind of concrete application scenarios, above-mentioned crystal oscillator 330 can be the 13MHz crystal oscillator, and first phase threshold is the clock cycle of 144 13MHz crystal oscillators, and first setting-up time is a frame clock cycle, and the first setting number is one.
If detection module 327 detects in 30 seconds the phase difference between the frame clock and GPS pulse per second (PPS) less than the clock cycle of 144 13MHz crystal oscillators, phase difference adjusting module 329 can be in ensuing 30 seconds, the clock periodicity of the 13MHz crystal oscillator of a frame clock cycle correspondence is adjusted one in each frame clock cycle, up to phase difference is zero, this adjustment mode can be for increase or reduce the clock cycle of a 13MHz crystal oscillator in the clock cycle at a frame, and is corresponding with the phase difference between frame clock and the GPS pulse per second (PPS).
Above-mentioned CPU 310 also is used for phase difference between frame clock and GPS pulse per second (PPS) greater than first phase threshold, and during less than second phase threshold, every second setting-up time frame clock is adjusted for second clock cycle of setting the number crystal oscillator.
Above-mentioned crystal oscillator 330, can be the 13MHz crystal oscillator, first phase threshold is the clock cycle of 144 13MHz crystal oscillators, second phase threshold is the clock cycle of 30000 13MHz crystal oscillators, second setting-up time is 10 seconds, the second setting number is 48, and the clock cycle of 48 13MHz crystal oscillators is 48/13us, i.e. 1 bit of eating dishes without rice or wine in the gsm system.
If detection module 327 detects in 30 seconds the phase difference between the frame clock and GPS pulse per second (PPS) greater than the clock cycle of 144 13MHz crystal oscillators, and less than the clock cycle of 30000 13MHz crystal oscillators, CPU 310 can be every 10 seconds by writing the counter in the frequency division module 326, the BIT that eats dishes without rice or wine to a gsm system of frame clock fine setting adjusts 3 times continuously.Counter in the frequency division module 326 is used for the clock periodicity of 13MHz crystal oscillator being counted in the clock cycle at a frame.By writing the count value that this counter changes this counter, can adjust the frame clock of frequency division module 326 outputs.
Above-mentioned CPU 310, when also being used for phase difference between frame clock and GPS pulse per second (PPS) greater than second phase threshold, the rising edge of adjusting the frame clock aligns with the rising edge of GPS pulse per second (PPS).
Above-mentioned second phase threshold is the clock cycle of 30000 13MHz crystal oscillators; if detection module 327 detects in 30 seconds the phase difference between the frame clock and GPS pulse per second (PPS) greater than the clock cycle of 30000 13MHz crystal oscillators; the rising edge that CPU 310 can directly adjust the frame clock aligns with the rising edge of GPS pulse per second (PPS); this adjustment can be in morning 2～4 be carried out, and avoids the influence to normal traffic.
The technical scheme of the embodiment of the invention has the following advantages, because according to the GPS information that receives, by adjustment to the clock signal of crystal oscillator output, the delta frame clock, and the phase difference between detection frame clock and the GPS pulse per second (PPS), the phase place of the frame clock that generates according to this phase difference adjustment makes the frame clock of generation and GPS pulse per second (PPS) synchronous, reaches the effect of the frame clock synchronization among the different B TS.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential general hardware platform, can certainly pass through hardware, but the former is better execution mode under a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium, comprise that some instructions are with so that a station terminal equipment (can be mobile phone, personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be looked protection scope of the present invention.
Claims (8)
1. a frame clock synchronizing method is characterized in that, comprising:
According to the global position system GPS information that receives, generate and the synchronous GPS pulse per second (PPS) of gps clock;
Utilize described GPS pulse per second (PPS) to adjust crystal oscillator, the clock signal of described crystal oscillator output and described GPS pulse per second (PPS) are kept synchronously;
Clock signal to described crystal oscillator output is carried out frequency division, and the clock signal behind the described frequency division is the frame clock;
Obtain the phase difference between described frame clock and the described GPS pulse per second (PPS), according to described phase difference, adjust the phase place of described frame clock, make described frame clock consistent with phase place between the described GPS pulse per second (PPS), the phase place of the described frame clock of described adjustment comprises:
If the phase difference between frame clock and the GPS pulse per second (PPS) less than first phase threshold, every the clock cycle of first setting-up time to the frame clock adjustment first setting number crystal oscillator, is zero up to phase difference then; If the phase difference between frame clock and the GPS pulse per second (PPS) is greater than first phase threshold, and less than second phase threshold, then the frame clock was adjusted for second clock cycle of setting the number crystal oscillator every second setting-up time; If, then adjusting the rising edge of frame clock greater than second phase threshold, the phase difference between frame clock and the GPS pulse per second (PPS) aligns with the rising edge of GPS pulse per second (PPS).
2. the method for claim 1 is characterized in that, the described GPS pulse per second (PPS) adjustment crystal oscillator that utilizes makes the clock signal of crystal oscillator output and GPS pulse per second (PPS) keep comprising synchronously:
Utilize described GPS pulse per second (PPS) as clock signal, the high level signal that generates the duration and be a plurality of described GPS pulse per second (PPS) cycles is as the high level window;
Described high level window as enable signal, is obtained the actual number of the clock signal that described crystal oscillator exports in described high level window;
Obtain the actual number of the clock signal of output in the described high level window and the difference between the preset value, change the frequency of the clock signal of described crystal oscillator output according to described difference, make the actual number of the clock signal that described crystal oscillator exports in described high level window equal described preset value.
3. method as claimed in claim 2 is characterized in that, the actual number that described difference equals the clock signal of output in the described high level window deducts the difference between the described preset value.
4. method as claimed in claim 3 is characterized in that, the described actual number of the clock signal of output in the described high level window and the difference between the preset value obtained changes the frequency of the clock signal of described crystal oscillator output according to described difference, comprising:
If described difference is obtained the FREQUENCY CONTROL amount of the clock signal that reduces described crystal oscillator output for just; If described difference for negative, is obtained the controlled quentity controlled variable of the frequency of the clock signal that increases described crystal oscillator output;
Utilize described controlled quentity controlled variable to change the frequency of the clock signal of described crystal oscillator output.
5. the method for claim 1 is characterized in that, the phase place of described adjustment frame clock specifically comprises:
Every a default time cycle, whether the phase difference that detects described frame clock and described GPS pulse per second (PPS) is greater than zero;
If the phase difference of described frame clock and described GPS pulse per second (PPS) greater than zero, is adjusted the phase place of described frame clock, make that the phase difference of described frame clock and described GPS pulse per second (PPS) is zero.
6. a veneer is used for and global position system GPS star card connection, it is characterized in that, comprising: central processor CPU, frame clock synchronization apparatus, crystal oscillator and bus, wherein,
Described CPU is connected with institute frame clock synchronization apparatus by described bus, and described frame clock synchronization apparatus is connected with described crystal oscillator by described bus;
Described frame clock synchronization apparatus, be used to receive the GPS pulse per second (PPS) that described GPS star card sends, utilize described GPS pulse per second (PPS), adjust described crystal oscillator by described CPU, make the clock signal and the described GPS pulse per second (PPS) of described crystal oscillator output synchronous, obtain the clock signal of described crystal oscillator output then, to the described clock signal frequency division that obtains, clock signal after the described frequency division is the frame clock, obtains the phase difference between described frame clock and the described GPS pulse per second (PPS), according to described phase difference, adjust the phase place of described frame clock, make described frame clock consistent with phase place between the described GPS pulse per second (PPS), the phase place of the described frame clock of described adjustment comprises:
If the phase difference between frame clock and the GPS pulse per second (PPS) less than first phase threshold, every the clock cycle of first setting-up time to the frame clock adjustment first setting number crystal oscillator, is zero up to phase difference then; If the phase difference between frame clock and the GPS pulse per second (PPS) is greater than first phase threshold, and less than second phase threshold, then the frame clock was adjusted for second clock cycle of setting the number crystal oscillator every second setting-up time; If, then adjusting the rising edge of frame clock greater than second phase threshold, the phase difference between frame clock and the GPS pulse per second (PPS) aligns with the rising edge of GPS pulse per second (PPS);
Described crystal oscillator is used for according to certain frequency clock signal.
7. as veneer as described in the claim 6, it is characterized in that described frame clock synchronization apparatus comprises: first counting module, high level window module, second counting module, notification module, frequency regulation block and frequency division module, wherein,
Described first counting module is used for the GPS pulse per second (PPS) number of described reception is counted;
Described high level window module, being used for generating the duration according to described first counting module is that the high level signal in a plurality of described GPS pulse per second (PPS) cycles is as the high level window;
Described second counting module, the high level window that is used for described high level window module is generated be as enable signal, obtains the actual number of the clock signal that described crystal oscillator exports in described high level window;
Notification module is used to notify described CPU to obtain numerical value and difference between the preset value that described second counting module obtains and the controlled quentity controlled variable of obtaining the frequency that changes described crystal oscillator clock signal according to described difference;
Frequency regulation block, be used to receive the controlled quentity controlled variable that described CPU obtains according to the notice of described notification module, change the frequency of the clock signal of described crystal oscillator output by described controlled quentity controlled variable, make the actual number of the clock signal that described crystal oscillator exports in described high level window equal preset value;
Described frequency division module is used for the clock signal of described crystal oscillator output is carried out frequency division, and the clock signal behind the described frequency division is the frame clock.
8. as veneer as described in the claim 7, it is characterized in that described frame clock synchronization apparatus also comprises: detection module, phase difference acquisition module and phase difference adjusting module,
Described detection module is connected with described phase difference acquisition module, and described phase difference acquisition module is connected with described phase difference adjusting module, wherein,
Described phase difference acquisition module is used to obtain frame clock behind the described frequency division module frequency division and the phase difference between the described GPS pulse per second (PPS);
Described phase difference adjusting module is used to adjust the phase place of the frame clock behind the described frequency division module frequency division, makes the phase place of the frame clock behind the described frequency division module frequency division consistent with phase place between the described GPS pulse per second (PPS), comprising:
If the phase difference between frame clock and the GPS pulse per second (PPS) less than first phase threshold, every the clock cycle of first setting-up time to the frame clock adjustment first setting number crystal oscillator, is zero up to phase difference then; If the phase difference between frame clock and the GPS pulse per second (PPS) is greater than first phase threshold, and less than second phase threshold, then the frame clock was adjusted for second clock cycle of setting the number crystal oscillator every second setting-up time; If, then adjusting the rising edge of frame clock greater than second phase threshold, the phase difference between frame clock and the GPS pulse per second (PPS) aligns with the rising edge of GPS pulse per second (PPS);
Described detection module, be used for every a default time cycle, detect phase difference that described phase difference acquisition module obtains whether greater than zero, if the phase difference that described phase difference acquisition module obtains greater than zero, notifies described phase difference adjusting module to adjust phase difference.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101879720A CN101448315B (en) | 2008-12-31 | 2008-12-31 | Frame clock synchronization method and device |
| PCT/CN2009/076118 WO2010072180A1 (en) | 2008-12-27 | 2009-12-28 | Method and device for frame synchronization |
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| CN2008101879720A CN101448315B (en) | 2008-12-31 | 2008-12-31 | Frame clock synchronization method and device |
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