CN108521324B - Synchronous clock device - Google Patents
Synchronous clock device Download PDFInfo
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- CN108521324B CN108521324B CN201810228186.4A CN201810228186A CN108521324B CN 108521324 B CN108521324 B CN 108521324B CN 201810228186 A CN201810228186 A CN 201810228186A CN 108521324 B CN108521324 B CN 108521324B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
Abstract
The invention discloses a synchronous clock device, comprising: the positioning module receives a positioning signal from a positioning service system and generates a synchronous signal source based on the positioning signal; a digital frequency synthesizer for locking the synchronous signal source; the constant temperature crystal oscillator provides an original system clock signal for the digital frequency synthesizer; the field programmable gate array outputs a predicted frequency adjusting word for driving the DDS in the digital frequency synthesizer within a time period when the positioning signal is lost until the positioning signal is retrieved again; before a synchronous signal source is not received, providing preset frequency adjusting words for driving the DDS for the DDS, and outputting first frequency adjusting words for driving the DDS under the action of the synchronous signal source in a time period when the synchronous signal source exists; the digital frequency synthesizer outputs a first target clock signal according to the frequency adjustment word. The technical problem that in the prior art, a synchronous clock device outputs clock signals inaccurately after a GPS module is lost is solved.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to a synchronous clock device.
Background
For a wireless communication system in a TDD (Time-division duplex) mode, accurate clock synchronization is very important for realizing functions and improving performance of the system. The synchronization of the system mainly comprises the synchronization between the base station and the controller, between the base stations and the terminal. For example: for a TD-LTE (Time Division Long term evolution) base station, all base stations need to satisfy the requirements of Time synchronization accuracy of 3us and frequency accuracy of 0.05 ppm.
The scheme related to the synchronization technology at present is that a GPS module is used to receive a 1PPS signal on a satellite, then the 1PPS signal on the satellite and a 1PPS signal generated by frequency division of a local OCXO (Oven Controlled Crystal Oscillator) are subjected to digital frequency and phase discrimination processing inside a digital chip, an internal accumulator is used to perform sliding average processing to output the data according to the principle of filtering inside a phase-locked loop, the output data is used to convert the data into a correction value required by DAC input, the DAC controls a voltage-Controlled terminal of the local OCXO to adjust the clock frequency of the OCXO after outputting the data, and the 1PPS signal received by the GPS module is used to correct the offset of the local OCXO Crystal Oscillator along with time and temperature through the digital phase-locked loop. The last operating value is maintained when the GPS signal is lost, so that the output clock signal is less and less accurate due to the drift with time and temperature after the positioning signal is lost because the last operating value is maintained when the GPS signal is lost.
Disclosure of Invention
The embodiment of the invention provides a synchronous clock device, and solves the technical problem that the synchronous clock device outputs an inaccurate clock signal after a GPS module is lost in the prior art.
The embodiment of the invention provides a synchronous clock device, which comprises:
the positioning module is used for receiving a positioning signal from a positioning service system and generating a synchronous signal source based on the positioning signal;
a digital frequency synthesizer for locking the synchronous signal source;
the oven controlled crystal oscillator OCXO is used for providing an original system clock signal for the digital frequency synthesizer;
the field programmable gate array is used for outputting a prediction frequency adjusting word for driving a direct digital frequency synthesizer DDS in the digital frequency synthesizer within the time period that the positioning signal is lost until the positioning signal is retrieved again;
before the synchronous signal source is not received, providing a preset frequency adjusting word for driving the DDS for the DDS, and outputting a first frequency adjusting word for driving the DDS under the action of the synchronous signal source in a time period when the synchronous signal source exists;
the digital frequency synthesizer is further configured to output a first target clock signal according to the preset frequency adjusting word before the synchronous signal source is not received, output the first target clock signal according to the first frequency adjusting word in a time period when the synchronous signal source exists, and output the first target clock signal according to the predicted frequency adjusting word in a time period when the synchronous signal source is unavailable.
Optionally, the positioning module includes:
a receiver unit of the M positioning service systems, configured to receive respective positioning signals of the M positioning service systems simultaneously, where M is an integer greater than 1;
and the signal selection unit is used for selecting one positioning signal from the positioning signals of the M positioning service systems according to a priority selection strategy and determining the positioning signal as the synchronous signal source.
Optionally, the receiver unit of the M kinds of location service systems includes: the GPS signal receiving unit and the Beidou signal receiving unit;
the GPS signal receiving unit is used for receiving a GPS positioning signal;
the Beidou signal receiving unit is used for receiving a Beidou positioning signal;
the signal selection unit is used for defaulting to use the GPS positioning signal as a synchronous signal source, when the received GPS positioning signal is unavailable, the signal selection unit is switched to the Beidou positioning signal as the synchronous signal source until the signal quality of the GPS positioning signal is replied to be more than a preset value, and when the signal quality of the GPS positioning signal exceeds the maximum signal sensitivity of the Beidou positioning signal received by the Beidou signal receiving unit, the signal selection unit is switched back to use the GPS positioning signal as the synchronous signal source, and if the GPS positioning signal and the Beidou positioning signal are unavailable, the signal selection unit enters a holding stage until the condition of exiting the holding stage is met.
Optionally, the digital frequency synthesizer further includes:
the phase frequency detector is used for carrying out phase frequency detection on the synchronous signal source to generate the deviation value of the synchronous signal source;
the loop filter is used for filtering the deviation value to obtain a post-filtering deviation value;
a frequency adjustment word processor for generating the first frequency adjustment word according to the post-filtering offset amount processing;
the internal phase-locked loop is used for carrying out frequency conversion on an original system clock signal provided by the OCXO to generate a target system clock signal, and the target system clock signal is provided for the phase frequency detector so that the phase frequency detector carries out phase frequency detection and phase detection processing on the synchronous signal source based on the target system clock signal;
the DDS is used for: generating a mixed clock signal according to the preset frequency adjusting word and the target system clock signal before the positioning signal is not received; outputting the mixed clock signal according to the first frequency adjustment word and the target system clock signal during a time period when the positioning signal is present, and outputting the mixed clock signal according to a predicted frequency adjustment word and the target system clock signal during a time period when the positioning signal is unavailable.
And the clock distribution output part is used for distributing the mixed clock signal output by the DDS to obtain the first target clock signal output outwards and the second target clock signal provided for the field programmable gate array.
Optionally, when the synchronous signal source exists, the field programmable gate array learns the drift behavior of the OCXO based on a kalman filter algorithm model to obtain learning data;
in the time period when the synchronous signal source is lost, the field programmable gate array performs drift prediction on the OCXO according to the learning data to obtain a drift prediction result;
and the field programmable gate array controls to output the predicted frequency adjusting word according to the drift prediction result, and drives the DDS according to the predicted frequency adjusting word until the synchronous signal source is retrieved again.
Optionally, the field programmable gate array includes: the device comprises a first low-pass filter, a second low-pass filter, a subtracter, a third low-pass filter, a first moving average unit, a second moving average unit, a Kalman time aging model, a Kalman temperature drift model, filter delay compensation and an adder, wherein the first low-pass filter is connected with the subtracter through a first filter;
when the synchronous signal source exists, learning the drifting behavior of the OCXO based on a Kalman filtering algorithm model to obtain learning data, specifically:
the first low-pass filter is configured to: after the internal phase-locked loop is stabilized, filtering out a total change value of the frequency of the OCXO along with the change of time and temperature from the first frequency adjusting word read by the DDS one by one second;
the second low-pass filter is configured to: filtering out a first drift value of the aging of the frequency of the OCXO over time from the total change value;
the subtracter is used for subtracting the first drift value from the total change value to obtain a second drift value of the frequency of the OCXO along with the change of the temperature;
the third low-pass filter is configured to filter the second drift value;
the first moving average unit is configured to perform moving average calculation on the first drift value to obtain a first averaged drift value;
the second moving average unit is configured to perform moving average calculation on the second drift value to obtain a second averaged drift value;
the Kalman time aging model is used for training based on the first average post-drift value to obtain first part learning data;
the Kalman temperature drift model is used for training based on the second averaged drift value to obtain a second part of learning data;
and carrying out drift prediction on the OCXO according to the learning data to obtain a drift prediction result, which specifically comprises the following steps:
cutting off the process of reading the first frequency adjustment word from the DDS when the synchronization signal source is lost;
the filter delay compensation is used for carrying out delay compensation on the second part of learning data to obtain learning data after delay compensation;
the adder is used for superposing the learning data after the delay compensation, the first part of learning data and the initially obtained first frequency adjusting word to obtain the drift prediction result;
optionally, the synchronous clock device further includes:
and the temperature sensor is used for controlling the input of a temperature reference to the Kalman temperature drift model, so that the Kalman temperature drift model trains the first average post-drift value according to the reference temperature.
Optionally, the kalman time aging model is specifically configured to: and training the second averaged drift value by taking the second target clock signal as a time reference.
Optionally, the frequency of the target system clock signal is specifically: 1 PPS;
the frequency of the first target clock signal is specifically: 10M;
the frequency of the second target clock signal is specifically: 1 PPS;
the frequency of the synchronous signal source is specifically: 1 PPS.
Optionally, the training time of the kalman time aging model based on the first average post-drift value is 2 hours;
the training time of the Kalman temperature drift model based on the second average post-drift value is 2 hours.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:
the field programmable gate array is arranged and used for outputting a predicted frequency adjusting word for driving a direct digital frequency synthesizer DDS in the digital frequency synthesizer in a time period when the positioning signal is lost until the positioning signal is retrieved again, the digital frequency synthesizer outputs a first target clock signal outwards according to the preset frequency adjusting word before a synchronous signal source is not received, outputs the first target clock signal outwards according to the first frequency adjusting word in the time period when the synchronous signal source exists, and outputs the first target clock signal outwards according to the predicted frequency adjusting word in the time period when the synchronous signal source is unavailable. Therefore, the predicted frequency adjusting word is given by the field programmable gate array in the time period when the positioning signal is lost, so that the digital frequency synthesizer can accurately output the first target clock signal according to the predicted frequency adjusting word in the time period when the positioning signal is lost, but the last operation value is kept after the GPS signal is lost, and the accuracy of the synchronous clock is improved.
Furthermore, because the GPS positioning signal and the Beidou positioning signal are received simultaneously, one is selected as the synchronous signal source according to the signal quality and the priority, the stability and the reliability of the synchronous signal source are improved, and the reliability of the synchronous clock device is further improved.
Furthermore, an improved Kalman filtering correction algorithm (a Kalman time aging model and a Kalman temperature drift model) is provided as a keeping algorithm model in a keeping stage, and 100-point moving average is performed on input stages of the Kalman time aging model and the Kalman temperature drift model to reduce the variance of jitter of input signals, so that the accuracy and the stability of Kalman filtering correction are improved, and the accuracy and the stability of a synchronous clock device in the keeping stage are further improved.
Furthermore, the bandwidth of the phase-locked loop is reduced step by switching a DPLL configuration table inside the integrated digital frequency synthesizer, so that the internal phase-locked loop can be quickly locked into a very low bandwidth under the condition of no lock loss, the inherent jitter of the 1PPS can be quickly reduced to a very small range by the system, and the synchronization performance is improved, thereby avoiding the defect that the long time is needed for the locking of the OCXO to a stable bandwidth when the drift condition of the OCXO is corrected by the 1PPS of a GPS and a method for controlling a voltage control end of the OCXO by a DAC in the prior art.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a synchronous clock apparatus according to an embodiment of the present invention;
fig. 2 is a block diagram of the field programmable gate array of fig. 1.
Detailed Description
In order to better understand the above technical solutions, embodiments of the present invention will be described in detail below with reference to the drawings and specific embodiments.
Referring to fig. 1, an embodiment of the present invention provides a synchronous clock apparatus, including: the system comprises a positioning module 1, a digital frequency synthesizer 2, an oven controlled crystal oscillator 3, an FPGA (Field-Programmable Gate Array) 4 and a temperature sensor 5.
The positioning module 1 is used for receiving a positioning signal from a positioning service system and generating a synchronous signal source based on the positioning signal; a digital frequency synthesizer 2 for locking the synchronous signal source; an oven controlled crystal oscillator 3 for providing an original system clock signal to the digital frequency synthesizer 2; a field programmable gate array 4, configured to output a predicted frequency adjustment word for driving a DDS (Direct Digital Synthesizer) 205 in the Digital frequency Synthesizer 2 in a time period when the positioning signal is lost until the positioning signal is retrieved again; before the synchronous signal source is not received, providing a preset frequency adjusting word for driving the direct digital frequency synthesizer 205 to the direct digital frequency synthesizer 205, and outputting a first frequency adjusting word for driving the direct digital frequency synthesizer 205 under the action of the synchronous signal source in a time period when the synchronous signal source exists; the digital frequency synthesizer 2 is further configured to output a first target clock signal according to the preset frequency adjusting word before the synchronous signal source is not received, output the first target clock signal according to the first frequency adjusting word in a time period when the synchronous signal source exists, and output the first target clock signal according to a predicted frequency adjusting word in a time period when the synchronous signal source is unavailable.
Specifically, referring to fig. 2, the positioning module 1 includes: a receiver unit of the M positioning service systems, configured to receive respective positioning signals of the M positioning service systems simultaneously, where M is an integer greater than 1; and the signal selection unit is used for selecting one positioning signal from the positioning signals of the M positioning service systems according to a priority selection strategy and determining the positioning signal as the synchronous signal source.
In a specific implementation process, the receiver unit of the M positioning service systems includes: the GPS signal receiving unit and the Beidou signal receiving unit; the GPS signal receiving unit is used for receiving a GPS positioning signal and the Beidou signal receiving unit is used for receiving a Beidou positioning signal; the signal selection unit is used for defaulting to use the GPS positioning signal as a synchronous signal source, when the received GPS positioning signal is unavailable, the signal selection unit is switched to the Beidou positioning signal as the synchronous signal source until the signal quality of the GPS positioning signal is replied to be more than a preset value, and when the signal quality of the GPS positioning signal exceeds the maximum signal sensitivity of the Beidou positioning signal received by the Beidou signal receiving unit, the signal selection unit is switched back to use the GPS positioning signal as the synchronous signal source, and if the GPS positioning signal and the Beidou positioning signal are unavailable, the signal selection unit enters a holding stage until the condition of exiting the holding stage is met.
Specifically, the preset value may be set to-148 dBm. It should be noted that the GPS positioning signal is not available, and may be: if the signal quality is below-148 dBm, then the GPS positioning signal is deemed unavailable. The loss of the GPS positioning signal specifically comprises the following steps: the GPS signal receiving unit cannot receive the GPS positioning signal.
Specifically, after the holding stage is entered, the signal quality of the GPS positioning signal and the signal quality of the Beidou positioning signal are still detected in real time, the GPS positioning signal or the Beidou positioning signal is collected and available within 12 hours of the holding stage, the waiting time is 10 minutes, if the signal quality of the collected GPS positioning signal or the signal quality of the Beidou positioning signal continues within 10 minutes and the signal quality stably rises, the holding stage is exited, and if the holding stage is entered for more than 12 hours, the system once receives the GPS positioning signal or the Beidou positioning signal, the holding stage is exited.
The stable rise of the signal quality may be: the situation that the signal quality of the collected GPS positioning signal is not reduced occurs, or the situation that the signal quality of the collected Beidou positioning signal is not reduced occurs.
Through the process, the positioning module 1 receives the positioning signals from the antenna end, and selects proper positioning signals as synchronous signal sources input to the digital frequency synthesizer 2 according to the priorities of the GPS positioning signals and the Beidou positioning signals and the quality of the GPS positioning signals and the Beidou positioning signals.
Further, the selection of the synchronization signal source can be specified based on manual operation of a user, and the selection is not necessarily performed according to the priority of the synchronization signal source.
With continued reference to fig. 2, the digital frequency synthesizer 2 includes: a phase frequency detector 201, a loop filter 202, a frequency adjusting processor 203, an internal phase locked loop 204, a direct digital frequency synthesizer 205, and a clock distribution output part 206.
The phase frequency detector 201 is configured to perform phase frequency detection on the synchronous signal source to generate a deviation amount of the synchronous signal source.
Specifically, the frequency of the synchronization signal source generated by the positioning module 1 is 1PPS, and the synchronization signal source is used as a reference input of the phase frequency detector 201, and the synchronization signal source of the 1PPS performs phase frequency detection processing in the phase frequency detector 201 with a target system clock signal generated by feedback of the direct digital frequency synthesizer 205. Specifically, the signal frequency of the target system clock signal is the same as the signal frequency of the synchronization signal source, and specifically, the signal frequency of the target system clock signal is 1 PPS.
And the loop filter 202 is configured to perform filtering processing on the deviation amount to obtain a post-filtering deviation amount.
And the frequency adjusting word processor 203 is configured to generate the first frequency adjusting word according to the post-filtering offset amount processing.
And the internal phase-locked loop 204 is configured to perform frequency conversion on an original system clock signal provided by the oven controlled crystal oscillator 3 to generate a target system clock signal, and the target system clock signal is provided to the phase frequency detector 201, so that the phase frequency detector 201 performs phase frequency detection on the synchronous signal source based on the target system clock signal.
More specifically, the mixed clock signal of the direct digital frequency synthesizer 205 is fed back to the feedback frequency divider 207, and the target system clock signal having a signal frequency of 1PPS is obtained by frequency division from the mixed clock signal of the direct digital frequency synthesizer 205 by the feedback frequency divider and supplied to the phase frequency detector 201.
A direct digital frequency synthesizer 205 for: generating a mixed clock signal according to the preset frequency adjusting word and the target system clock signal before the positioning signal is not received; outputting the mixed clock signal according to the first frequency adjustment word and the target system clock signal during a time period when the positioning signal is present, and outputting the mixed clock signal according to a predicted frequency adjustment word and the target system clock signal during a time period when the positioning signal is unavailable.
A clock distribution output part 206, configured to distribute the mixed clock signal output by the direct digital frequency synthesizer 205 to obtain the first target clock signal output outwards and the second target clock signal provided to the field programmable gate array 4.
In a specific implementation, the first target clock signal has a frequency of 10M, and the second target clock signal has a frequency of 1 PPS.
Specifically, the internal Phase-Locked Loop 204 is a DPLL (Digital Phase Locked Loop).
In the implementation, since reducing the jitter of the 1PPS sync signal source to a sufficiently low value requires locking the DPLL loop in an extremely low bandwidth, for the locking requirement, the DPLL is constrained by the DPLL attribute table carried inside the chip of the digital frequency synthesizer 2, which constrains the electrical and frequency characteristics of the original system clock signal input to the digital frequency synthesizer 2, the phase-locked loop bandwidth, the phase margin, and the parameters of the phase frequency detector 201.
The digital frequency synthesizer 2 is provided with 8 equal-sized attribute tables, and the user can freely define each feature of the DPLL through the attribute tables. In order to enable the DPLL loop to lock within an extremely low phase-locked loop bandwidth, the phase-locked loop bandwidth is reduced step by changing the phase-locked loop bandwidth based on 8 tables of attributes inside the digital frequency synthesizer 2. The specific method comprises the following steps: the characteristics of the input signals of the 8 attribute tables are constrained to be original system clock signals of the same reference, the other relevant characteristics of the DPLL are the same, only one item of the phase-locked loop bandwidth of the DPLL is changed, and the DPLL loop bandwidth is reduced step by step. At the initial start-up of the synchronous clock device, since the rapid capture and locking of the DPLL loop need to be completed, the loop is constrained with a high bandwidth value, and the loop bandwidth is reduced after the DPLL loop is stabilized.
The bandwidth of the DPLL loop is gradually locked from 0.05Hz to 0.007Hz by the above method. When the locking bandwidth is larger than 0.01Hz, the bandwidth of the loop is switched only 10 minutes after locking, but if the loop is out of lock for 10 minutes due to switching, the loop returns to the previous bandwidth value to continue tracking the loop. When the loop is already lower than 0.001Hz, because the bandwidth of the DPLL loop is already very low at this time, if the bandwidth is switched too fast, which easily causes the lock loss of the DPLL loop, the method of reducing the loop bandwidth after the loop is locked for 20 minutes is adopted, and the DPLL loop returns to the previous bandwidth value to continue tracking the previous bandwidth loop after the lock loss of the DPLL loop caused by the switching is up to 20 minutes, and the above operation is performed until the DPLL loop is finally locked within the bandwidth of 0.007 Hz.
By the method for switching the bandwidth of the phase-locked loop, the phase-locked loop can be flexibly and stably locked in a very small bandwidth, so that the inherent jitter of the GPS positioning signal of 1PPS can be reduced more efficiently, and the synchronization performance is improved.
The clock is stably locked under the extremely low bandwidth within a short time, the quality and the stability of the output clock of the synchronous clock device are improved, and the flexibility and the reliability of the synchronous clock are improved.
Specifically, when the synchronous signal source exists, the field programmable gate array 4 learns the drifting behavior of the oven controlled crystal oscillator 3 based on a kalman filter algorithm model to obtain learning data; in the time period when the synchronous signal source is lost, the field programmable gate array 4 carries out drift prediction on the constant temperature crystal oscillator 3 according to the learning data to obtain a drift prediction result; the field programmable gate array 4 controls to output the predicted frequency adjusting word according to the drift prediction result, and the field programmable gate array 4 drives the direct digital frequency synthesizer 205 according to the predicted frequency adjusting word until the synchronous signal source is retrieved again.
It should be noted that the three of the predicted frequency adjustment word, the first frequency adjustment word, and the preset frequency adjustment word are only used for distinguishing which component provides the frequency adjustment word, and are not used for distinguishing the frequency adjustment word.
Specifically, in order to correct the frequency drift of the oven controlled crystal oscillator 3, in combination with the foregoing embodiments, an embodiment is provided in which the field programmable gate array 4 performs correction based on a kalman filter algorithm model, which is specifically described as follows:
referring to fig. 2, the field programmable gate array 4 includes: a first low-pass filter 401, a second low-pass filter 402, a subtractor 403, a third low-pass filter 404, a first moving average unit 405, a second moving average unit 406, a kalman time aging model 407, a kalman temperature drift model 408, a filter delay compensation 409, and an adder 410.
When the synchronous signal source exists, learning the drifting behavior of the oven controlled crystal oscillator 3 based on a Kalman filtering algorithm model to obtain learning data, specifically: the first low-pass filter 401 is configured to filter out a total variation value of the frequency of the oven controlled crystal oscillator 3 with time and temperature from the first frequency adjustment word read by the direct digital frequency synthesizer 205 second by second after the internal phase-locked loop 204 is stabilized; the second low-pass filter 402 is used for filtering out a first drift value of the frequency of the oven controlled crystal oscillator 3 aged along with time from the total change value;
the subtracter 403 is configured to subtract the first drift value from the total change value to obtain a second drift value of the frequency of the oven controlled crystal oscillator 3 along with the temperature change; the third low-pass filter 404 is configured to filter the second drift value; the first moving average unit 405 is configured to perform moving average calculation on the first drift value to obtain a first averaged drift value; the second moving average unit 406 is configured to perform moving average calculation on the filtered second drift value to obtain a second averaged drift value; the kalman time aging model 407 is configured to perform training based on the first averaged post-drift value to obtain a first part of learning data; the kalman temperature drift model 408 is configured to perform training based on the second averaged drift value to obtain a second part of learning data.
And carrying out drift prediction on the constant temperature crystal oscillator 3 according to the learning data to obtain a drift prediction result, which specifically comprises the following steps: cutting off the reading of the first frequency adjustment word from the direct digital frequency synthesizer 205 when the synchronization signal source is lost; the filter delay compensation 409 is used for performing delay compensation on the second part of learning data to obtain learning data after delay compensation; the adder 410 is configured to superimpose the learning data after the delay compensation, the first part of learning data, and the first frequency adjustment word obtained initially, so as to obtain the drift prediction result.
And the temperature sensor 5 is configured to control to input a temperature reference to the kalman temperature drift model 408, so that the kalman temperature drift model 408 performs training of the first averaged drift value according to the reference temperature.
The kalman time aging model 407 is specifically configured to: and training the second averaged drift value by taking the second target clock signal as a time reference.
The frequency of the target system clock signal is specifically: 1 PPS; the frequency of the first target clock signal is specifically: 10M; the frequency of the second target clock signal is specifically: 1 PPS; the frequency of the synchronous signal source is specifically: 1 PPS.
The training time of the kalman time aging model 407 based on the first average post-drift value is 2 hours; the length of time that the kalman temperature drift model 408 is trained based on the second averaged post-drift value is 2 hours.
Due to the quality problem of the synchronous signal source, the synchronous signal source provided by the positioning module 1 cannot be directly used as a synchronous clock source of the system, and after the locking of the synchronous signal source of the 1PPS is completed through the digital frequency synthesizer 2, the jitter amplitude of the synchronous signal source of the 1PPS can be well reduced.
Because the GPS signal is used as a synchronous clock source, the GPS signal is lost due to the instability of the received positioning signal, and therefore, for the system keeping process after the positioning signal is lost, when the GPS signal exists, the drift behavior of the local constant temperature crystal oscillator 3 along with the time and the temperature is learned through the Kalman filtering algorithm model, and after the GPS signal is lost, the drift condition of the constant temperature crystal oscillator 3 is predicted through the Kalman filtering algorithm model according to the previous learning data so as to control the output of the direct digital frequency synthesizer 205. Since there are two main kinds of drift behaviors of the oven crystal oscillator 3, one is a drift condition of the frequency of the oven crystal oscillator 3 with temperature change, and the other is an aging drift condition of the frequency of the oven crystal oscillator 3 with time change.
Wherein, the frequency drift along with time is a slow change, and the frequency drift along with temperature is a fast change. Therefore, the specific algorithm scheme is that after the DPLL is stabilized at the bandwidth of 0.007Hz, the first frequency adjustment word of the direct digital frequency synthesizer 205 is read from the digital frequency synthesizer 2 second by second, then the read first frequency adjustment word is sequentially sent to the field programmable gate array 4, the total variation value of the frequency with time and temperature is filtered out by the first low pass filter 401 of 600uHz in the field programmable gate array 4, then the first drift value of the frequency with time aging is filtered out from the total variation value by the second low pass filter 402 of 20uHz, and the two results are subtracted to obtain the second drift value of the frequency with temperature variation. After the above operations, the drift of the frequency of the oven controlled crystal oscillator 3 with time and temperature is filtered, and then the first drift value of the aging frequency with time is sent to the first moving average unit 405 with 100 points for the moving average calculation of 100 points for the first drift value pair to obtain the drift value after the first average, and the second drift value of the frequency changing with temperature is sent to the third low pass filter 404 with 600uHz for filtering the second drift value. And the filtered second drift value enters a 100-point second moving average unit 406, and the 100-point moving average calculation is performed on the filtered second drift value to obtain a second averaged post-drift value. Therefore, the variance of the input jitter of the Kalman time aging model 407 and the Kalman temperature drift model 408 is further reduced, so that the time length of the module training and learning drift process is reduced, and the instability of the system is reduced.
The first average post-drift value after the moving average calculation of 100 points is trained in a kalman time aging model 407 with time as a variable, so as to obtain a first part of learning data. Wherein the time is based on 1 second for training. And training a second average post-drift value obtained by calculating the moving average of 100 points in a Kalman temperature drift model 408 with the temperature as a variable to obtain a second part of learning data. Wherein the temperature is trained on the basis of 0.1 ℃. The training of the entire kalman time aging model 407 and the kalman temperature drift model 408 runs for 2 hours. When training is completed, if the locating signal is lost, the reading of the first frequency adjustment word of the direct digital frequency synthesizer 205 from the digital frequency synthesizer 2 is cut off. And directly performing linear estimation output on the Kalman time aging model 407 and the Kalman temperature drift model 408 respectively through loop returning, delaying the second part of learning data by 3600s, overlapping the second part of learning data with the first part of learning data and the initial first frequency adjusting word, and outputting the output to directly drive the direct digital frequency synthesizer 205 of the digital frequency synthesizer 2 for output.
Further, the 1PPS signal generated by the digital frequency synthesizer 2 is used as a time reference for the time drift of the kalman time aging model 407 in the fpga 4, so as to complete the operations of reading and writing the frequency adjustment word of the direct digital frequency synthesizer 205 by seconds, and the operations of synchronizing the data frame with the time reference of the system internal clock timing.
The temperature sensor 5 attached to the board card is adopted to repeatedly read the temperature of the current board card and average the temperature sensor 5 by 100 points, so that the influence of the jitter of the reading value of the temperature sensor 5 on the accuracy of the Kalman temperature drift model 408 is eliminated. The temperature sensor 5 is input to the kalman temperature drift model 408 in units of 0.1 degrees celsius.
In a preferred embodiment, if the positioning signal is lost during the training process in the kalman time aging model 407 and the kalman temperature drift model 408, the 100-point sliding average of the frequency adjustment word of the direct digital frequency synthesizer 205 recorded in the presence of the synchronization signal source of 1PPSD is used as the final holding result until the positioning signal is finally retrieved.
If the GPS signal is lost during the incomplete realization of the 100-point moving average, the last calculated value of the 100-point moving average is taken as the value of the frequency adjustment word of the direct digital frequency synthesizer 205 of the hold stage.
Specifically, the positioning module 1 receives a Beidou positioning signal and a GPS positioning signal from an antenna end, selects a proper positioning signal as a synchronous signal source according to priority and signal quality of the Beidou positioning signal and the GPS positioning signal, the positioning module 1 transmits the received 1PPS of the synchronous signal source to the digital frequency synthesizer 2 as input, the DPLL outputs a regulating word according to a preset frequency when not receiving the 1PPS of the synchronous signal source, and at the moment, the digital frequency synthesizer 2 works in a free running mode. When a synchronous signal source of 1PPS is effective, the DPLL operates according to the maximum DPLL bandwidth of 0.05Hz, when a DPLL loop is stably locked for 10 minutes, the DPLL is switched to the bandwidth of 0.03Hz, the DPLL also waits for locking and stably switches the bandwidth of 0.02Hz for 10 minutes, the same operation is carried out until the bandwidth reaches 0.01Hz, when the bandwidth is less than 0.01Hz, the DPLL operates according to the rule that the bandwidth is stably locked for 20 minutes and then is reduced by one gear, and if the DPLL loop is unlocked for a long time after the bandwidth is switched, the DPLL loop is switched to the previous bandwidth. After the bandwidth is locked at 0.0067Hz by the rule and the loop is stable for 20 minutes, the field programmable gate array 4 starts to read the preset frequency adjusting word of the digital frequency synthesizer 2 second by second. And the preset frequency adjusting word is sent into the field programmable gate array 4 for filtering processing, and numerical values changing along with temperature and time are respectively filtered out. And the two groups of separated data are sequentially subjected to 100-point moving average processing to further reduce the mean square value of the jitter of the signal. And then, sending the data subjected to the moving average processing into a Kalman filter for training, wherein the training time is 2 hours. After the training is completed, if the positioning signal is lost, the output result of the kalman temperature drift model 408 is delayed by 3600s, and is superimposed with the output of the kalman time aging model 407 and the initial first frequency adjustment word, and then the predicted frequency adjustment word for driving the digital frequency synthesizer 2 is output. If the positioning signal is lost in the training process, the first frequency adjustment word of 100-point moving average in the presence of the positioning signal is used as a running value and input into the digital frequency synthesizer 2.
Specifically, the digital frequency synthesizer 2 is specifically an AD9548 digital frequency synthesizer.
Specifically, the digital frequency synthesizer 2 with model AD9548 generates a 1PPS signal as a time reference for the time drift of the kalman time aging model 407, and performs the reading and writing operations of the frequency adjustment word of the direct digital frequency synthesizer 205 on a second-by-second basis.
The temperature sensor 5 chip attached to the board card is used as a temperature collector, the temperature of the current board card is repeatedly read, and 100-point sliding average is carried out on the temperature sensor 5, so that the influence of jitter of the reading value of the temperature sensor 5 on the accuracy of the Kalman temperature drift model 408 is eliminated. The temperature sensor 5 is input to the kalman temperature drift model 408 in units of 0.1 degrees celsius.
If the 1PPS synchronous signal source is lost in the training process of the Kalman time aging model 407 and the Kalman temperature drift model 408, the result of calculating the 100-point sliding average value of the first frequency adjusting word in the direct digital frequency synthesizer 205 recorded when the 1PPS synchronous signal source exists is used as a final predicted frequency adjusting word, and the predicted frequency adjusting word is kept until the positioning signal is finally retrieved again. If the locating signal is lost in the process that the 100-point moving average is not completely realized, the last calculated value of the 100-point moving average is adopted as the predicted frequency adjustment word of the holding stage.
One or more embodiments provided by the embodiments of the present invention specifically achieve the following technical effects or advantages:
the field programmable gate array is arranged and used for outputting a predicted frequency adjusting word for driving a direct digital frequency synthesizer DDS in the digital frequency synthesizer in a time period when the positioning signal is lost until the positioning signal is retrieved again, the digital frequency synthesizer outputs a first target clock signal outwards according to the preset frequency adjusting word before a synchronous signal source is not received, outputs the first target clock signal outwards according to the first frequency adjusting word in the time period when the synchronous signal source exists, and outputs the first target clock signal outwards according to the predicted frequency adjusting word in the time period when the synchronous signal source is unavailable. Therefore, the predicted frequency adjusting word is given by the field programmable gate array in the time period when the positioning signal is lost, so that the digital frequency synthesizer can accurately output the first target clock signal according to the predicted frequency adjusting word in the time period when the positioning signal is lost, but the last operation value is kept after the GPS signal is lost, and the accuracy of the synchronous clock is improved.
Furthermore, because the GPS positioning signal and the Beidou positioning signal are received simultaneously, one is selected as the synchronous signal source according to the signal quality and the priority, the stability and the reliability of the synchronous signal source are improved, and the reliability of the synchronous clock device is further improved.
Furthermore, an improved Kalman filtering correction algorithm (a Kalman time aging model and a Kalman temperature drift model) is provided as a keeping algorithm model in a keeping stage, and 100-point moving average is performed on input stages of the Kalman time aging model and the Kalman temperature drift model to reduce the variance of jitter of input signals, so that the accuracy and the stability of Kalman filtering correction are improved, and the accuracy and the stability of a synchronous clock device in the keeping stage are further improved.
Furthermore, the bandwidth of the phase-locked loop is reduced step by switching a DPLL configuration table inside the integrated digital frequency synthesizer, so that the internal phase-locked loop can be quickly locked into a very low bandwidth under the condition of no lock loss, the inherent jitter of the 1PPS can be quickly reduced to a very small range by the system, and the synchronization performance is improved, thereby avoiding the defect that the long time is needed for the locking of the OCXO to a stable bandwidth when the drift condition of the OCXO is corrected by the 1PPS of a GPS and a method for controlling a voltage control end of the OCXO by a DAC in the prior art.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A synchronous clock apparatus, comprising:
the positioning module is used for receiving a positioning signal from a positioning service system and generating a synchronous signal source based on the positioning signal;
a digital frequency synthesizer with a DPLL attribute table therein, the digital frequency synthesizer constraining characteristics of a DPLL based on the DPLL attribute table to lock the synchronous signal source;
the oven controlled crystal oscillator OCXO is used for providing an original system clock signal for the digital frequency synthesizer;
the field programmable gate array is used for controlling and outputting a predicted frequency adjusting word for driving a direct digital frequency synthesizer DDS in the digital frequency synthesizer according to a drift prediction result in a time period when the positioning signal is lost until the positioning signal is retrieved again; wherein the field programmable gate array comprises: the device comprises a first low-pass filter, a second low-pass filter, a subtracter, a third low-pass filter, a first moving average unit, a second moving average unit, a Kalman time aging model, a Kalman temperature drift model, filter delay compensation and an adder, wherein the first low-pass filter is connected with the subtracter through a first filter;
when the synchronous signal source exists, the first low-pass filter is used for filtering out a total change value of the frequency of the OCXO along with time and temperature change from a first frequency adjusting word read by the DDS one by one after an internal phase-locked loop is stabilized; the second low-pass filter is used for filtering out a first drift value of the aging of the frequency of the OCXO along with time from the total change value; the subtracter is used for subtracting the first drift value from the total change value to obtain a second drift value of the frequency of the OCXO along with the change of the temperature; the third low-pass filter is configured to filter the second drift value; the first moving average unit is configured to perform moving average calculation on the first drift value to obtain a first averaged drift value; the second moving average unit is configured to perform moving average calculation on the second drift value to obtain a second averaged drift value; the Kalman time aging model is used for training based on the first average post-drift value to obtain first part learning data; the Kalman temperature drift model is used for training based on the second averaged drift value to obtain a second part of learning data;
cutting off the process of reading the first frequency adjustment word from the DDS when the synchronization signal source is lost; the filter delay compensation is used for carrying out delay compensation on the second part of learning data to obtain learning data after delay compensation; the adder is used for superposing the learning data after the delay compensation, the first part of learning data and a first frequency adjusting word obtained initially to obtain the drift prediction result;
before the synchronous signal source is not received, providing a preset frequency adjusting word for driving the DDS for the DDS, and outputting a first frequency adjusting word for driving the DDS under the action of the synchronous signal source in a time period when the synchronous signal source exists;
the digital frequency synthesizer is further configured to output a first target clock signal according to the preset frequency adjusting word before the synchronous signal source is not received, output the first target clock signal according to the first frequency adjusting word in a time period when the synchronous signal source exists, and output the first target clock signal according to the predicted frequency adjusting word in a time period when the synchronous signal source is unavailable.
2. The synchronous clock apparatus of claim 1, wherein the positioning module comprises:
a receiver unit of the M positioning service systems, configured to receive respective positioning signals of the M positioning service systems simultaneously, where M is an integer greater than 1;
and the signal selection unit is used for selecting one positioning signal from the positioning signals of the M positioning service systems according to a priority selection strategy and determining the positioning signal as the synchronous signal source.
3. The synchronized clock apparatus of claim 2, wherein the receiver units of the M location services systems comprise: the GPS signal receiving unit and the Beidou signal receiving unit;
the GPS signal receiving unit is used for receiving a GPS positioning signal;
the Beidou signal receiving unit is used for receiving a Beidou positioning signal;
the signal selection unit is used for defaulting to use the GPS positioning signal as a synchronous signal source, when the received GPS positioning signal is unavailable, the signal selection unit is switched to the Beidou positioning signal as the synchronous signal source until the signal quality of the GPS positioning signal is replied to be more than a preset value, and when the signal quality of the GPS positioning signal exceeds the maximum signal sensitivity of the Beidou positioning signal received by the Beidou signal receiving unit, the signal selection unit is switched back to use the GPS positioning signal as the synchronous signal source, and if the GPS positioning signal and the Beidou positioning signal are unavailable, the signal selection unit enters a holding stage until the condition of exiting the holding stage is met.
4. The synchronous clock apparatus of claim 2, wherein the digital frequency synthesizer further comprises:
the phase frequency detector is used for carrying out phase frequency detection on the synchronous signal source to generate the deviation value of the synchronous signal source;
the loop filter is used for filtering the deviation value to obtain a post-filtering deviation value;
a frequency adjustment word processor for generating the first frequency adjustment word according to the post-filtering offset amount processing;
the internal phase-locked loop is used for carrying out frequency conversion on an original system clock signal provided by the OCXO to generate a target system clock signal, and the target system clock signal is provided for the phase frequency detector so that the phase frequency detector carries out phase frequency detection and phase detection processing on the synchronous signal source based on the target system clock signal;
the DDS is used for: generating a mixed clock signal according to the preset frequency adjusting word and the target system clock signal before the positioning signal is not received; outputting the mixed clock signal according to the first frequency adjustment word and the target system clock signal during a time period in which the positioning signal is present, and outputting the mixed clock signal according to a predicted frequency adjustment word and the target system clock signal during a time period in which the positioning signal is unavailable;
and the clock distribution output part is used for distributing the mixed clock signal output by the DDS to obtain the first target clock signal output outwards and the second target clock signal provided for the field programmable gate array.
5. The synchronous clock apparatus of claim 4, wherein the synchronous clock apparatus further comprises:
and the temperature sensor is used for controlling the input of a temperature reference to the Kalman temperature drift model, so that the Kalman temperature drift model trains the first average post-drift value according to the reference temperature.
6. The synchronous clock apparatus of claim 5,
the Kalman time aging model is specifically configured to: and training the second averaged drift value by taking the second target clock signal as a time reference.
7. The synchronous clock apparatus of claim 4,
the frequency of the target system clock signal is specifically: 1 PPS;
the frequency of the first target clock signal is specifically: 10M;
the frequency of the second target clock signal is specifically: 1 PPS;
the frequency of the synchronous signal source is specifically: 1 PPS.
8. The synchronous clock apparatus of claim 1, wherein the kalman time aging model is trained based on the first average post-drift value for a duration of 2 hours;
the training time of the Kalman temperature drift model based on the second average post-drift value is 2 hours.
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| CN111245593B (en) * | 2020-01-03 | 2021-04-20 | 北京邮电大学 | Time synchronization method and device based on Kalman filtering |
| CN113460124B (en) * | 2020-03-30 | 2022-12-09 | 比亚迪股份有限公司 | Train running time processing method and device, computer equipment and storage medium |
| CN112782725A (en) * | 2020-12-30 | 2021-05-11 | 华清瑞达（天津）科技有限公司 | High-precision GPS synchronization maintaining module |
| CN112821976B (en) * | 2020-12-31 | 2023-03-24 | 锐捷网络股份有限公司 | Method and device for maintaining local clock synchronization |
| CN113078900B (en) * | 2021-03-30 | 2022-07-15 | 中国核动力研究设计院 | System and method for improving performance of clock source of DCS platform of nuclear power plant |
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| US8675690B2 (en) * | 2011-04-19 | 2014-03-18 | Honeywell International Inc. | Low latency and self-adjusting frame synchronization algorithm for data streaming applications |
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