CN108521324A - Synchronous clock device - Google Patents
Synchronous clock device Download PDFInfo
- Publication number
- CN108521324A CN108521324A CN201810228186.4A CN201810228186A CN108521324A CN 108521324 A CN108521324 A CN 108521324A CN 201810228186 A CN201810228186 A CN 201810228186A CN 108521324 A CN108521324 A CN 108521324A
- Authority
- CN
- China
- Prior art keywords
- signal
- frequency
- source
- drift
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 title abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 24
- 230000009471 action Effects 0.000 claims abstract description 4
- DMBHHRLKUKUOEG-UHFFFAOYSA-N diphenylamine Chemical group C=1C=CC=CC=1NC1=CC=CC=C1 DMBHHRLKUKUOEG-UHFFFAOYSA-N 0.000 claims description 32
- 230000032683 aging Effects 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 21
- 230000008859 change Effects 0.000 claims description 18
- 238000012545 processing Methods 0.000 claims description 18
- 238000001914 filtration Methods 0.000 claims description 16
- 230000006399 behavior Effects 0.000 claims description 14
- 238000012549 training Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- 230000035945 sensitivity Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Abstract
The invention discloses a synchronous clock device, comprising: the positioning module receives a positioning signal from a positioning service system and generates a synchronous signal source based on the positioning signal; a digital frequency synthesizer for locking the synchronous signal source; the constant temperature crystal oscillator provides an original system clock signal for the digital frequency synthesizer; the field programmable gate array outputs a predicted frequency adjusting word for driving the DDS in the digital frequency synthesizer within a time period when the positioning signal is lost until the positioning signal is retrieved again; before a synchronous signal source is not received, providing preset frequency adjusting words for driving the DDS for the DDS, and outputting first frequency adjusting words for driving the DDS under the action of the synchronous signal source in a time period when the synchronous signal source exists; the digital frequency synthesizer outputs a first target clock signal according to the frequency adjustment word. The technical problem that in the prior art, a synchronous clock device outputs clock signals inaccurately after a GPS module is lost is solved.
Description
Technical field
The present invention relates to wireless communication field more particularly to a kind of Synchronization Clocks.
Background technology
For the wireless communication system under TDD (Time-divisionDuplex, time division duplex) pattern, accurately
Clock synchronizes the realization to the function of system and the promotion of performance is most important.Synchronizing for system includes mainly base station and control
It is synchronous between base station and terminal between base station and base station between device.Such as：For TD-LTE (Time Division Long
TermEvolution, timesharing long term evolution) for base station, all base stations are required for meeting timing tracking accuracy being 3us, frequency
Precision is 0.05ppm.
It is at present to receive the 1PPS signals on satellite by GPS module, then defended by this about the scheme of simultaneous techniques
1PPS signals on star and local OCXO (Oven Controlled Crystal Oscillator, constant-temperature crystal oscillator)
The 1PPS signals that constant-temperature crystal oscillator frequency dividing generates carry out digital frequency discrimination phase demodulation processing inside digit chip, pass through internal accumulator
It carries out sliding average processing and copies filtering principle output inside phaselocked loop, which, which is used for filling, changes into needed for DAC inputs
Corrected value, the voltage-controlled end that local OCXO is controlled after DAC is exported adjust the clock frequency of OCXO, pass through the digital phase-locked loop
Road, the 1PPS signals to be got off using GPS receiver come correct local OCXO crystal oscillators at any time with the offset of temperature.Work as GPS signal
The operating value that last time is then kept after loss, due to then keeping the operating value of last time after GPS signal is lost so that
After positioning signal is lost, output clock signal can be more and more inaccurate due to the offset at any time with temperature.
Invention content
The embodiment of the present invention solves Synchronization Clock in the prior art and exists by providing a kind of Synchronization Clock
GPS module exports the technical problem of clock signal inaccuracy after losing.
A kind of Synchronization Clock provided in an embodiment of the present invention, including：
Locating module is generated based on the positioning signal and is synchronized for receiving the positioning signal from positioning service system
Signal source；
Digital frequency synthesizer, for locking the source of synchronising signal；
Constant-temperature crystal oscillator OCXO, for providing original system clock signal to the digital frequency synthesizer；
Field programmable gate array, within the period that the positioning signal is lost, number described in output driving to be frequently
The pre- measured frequency of Direct Digital Synthesizer DDS adjusts word in rate synthesizer, until giving the positioning signal for change again；
Wherein, before not receiving the source of synchronising signal, the predeterminated frequency for driving the DDS is provided to the DDS
Adjust word, within there are the period of the source of synchronising signal, the DDS described in output driving under the action of the source of synchronising signal
First frequency adjust word；
The digital frequency synthesizer is additionally operable to before not receiving the source of synchronising signal, according to the default frequency
Rate adjusts word and exports first object clock signal outward, within there are the period of the source of synchronising signal, according to described first
Frequency adjusts word and exports the first object clock signal outward, and within the source of synchronising signal not available period,
Word, which is adjusted, according to the pre- measured frequency exports the first object clock signal outward.
Optionally, the locating module includes：
The receiver unit of M kind positioning service systems, for receiving the respective positioning of M kinds positioning service system simultaneously
Signal, M are the integer more than 1；
Signal behavior unit, for being believed from the respective positioning of the M kinds positioning service system according to priority selection strategy
A positioning signal is selected in number, is determined as the source of synchronising signal.
Optionally, the receiver unit of the M kinds positioning service system includes：GPS signal receiving unit and Big Dipper signal
Receiving unit；
The GPS signal receiving unit, for receiving GPS positioning signal；
The Big Dipper signal receiving unit, for receiving Big Dipper positioning signal；
The signal behavior unit, for giving tacit consent to using the GPS positioning signal as source of synchronising signal, in the institute received
State GPS positioning signal it is unavailable when, the Big Dipper positioning signal is switched to as source of synchronising signal, until the GPS positioning is believed
Number signal quality return back to default value or more, and the signal quality of the GPS positioning signal connects more than the Big Dipper signal
When receiving the peak signal sensitivity of the Big Dipper positioning signal received by unit, then it is described to switch back into the GPS positioning signal
Source of synchronising signal enters the holding stage until full if the GPS positioning signal and the Big Dipper positioning signal are unavailable
Foot exits the condition in holding stage.
Optionally, the digital frequency synthesizer further includes：
Phase frequency detector generates the source of synchronising signal for carrying out frequency and phase discrimination processing to the source of synchronising signal
Departure；
Loop filter, for being filtered to the departure, departure after being filtered；
Frequency adjusts word processing device, and word is adjusted for generating the first frequency according to departure processing after the filtering；
Internal phaselocked loop, the original system clock signal for providing the OCXO carry out frequency conversion, generate goal systems
Clock signal, the goal systems clock signal are supplied to the phase frequency detector so that the phase frequency detector is based on described
Goal systems clock signal carries out frequency and phase discrimination processing to the source of synchronising signal；
The DDS, is used for：Word and the mesh are adjusted according to the predeterminated frequency before not receiving the positioning signal
Mark system clock signal generates mix clock signal；Within there are the period of the positioning signal, according to the first frequency
It adjusts word and the goal systems clock signal exports the mix clock signal, in the positioning signal not available period
It is interior, word is adjusted according to pre- measured frequency and the goal systems clock signal exports the mix clock signal.
Clock distribution output par, c, the mix clock signal for exporting the DDS are allocated, and obtain output outward
The first object clock signal, and be supplied to the second target clock signal of the field programmable gate array.
Optionally, in the presence of the source of synchronising signal, the field programmable gate array is based on Kalman filtering algorithm
Model learns the drift behavior of the OCXO, obtains learning data；
Within the period that the source of synchronising signal is lost, the field programmable gate array is according to the learning data pair
The OCXO carries out drift forecasting, obtains drift forecasting result；
The field programmable gate array adjusts word, root according to the drift forecasting output control output pre- measured frequency
DDS described in word drive is adjusted according to the pre- measured frequency, until giving the source of synchronising signal for change again.
Optionally, the field programmable gate array includes：First low-pass filter, the second low-pass filter, subtracter,
Third low-pass filter, the first sliding average unit, the second sliding average unit, Kalman's time Ageing Model, Kalman's temperature
Spend drift model, filter compensation of delay, adder；
In the presence of the source of synchronising signal, the drift behavior of the OCXO is carried out based on Kalman filtering algorithm model
Study, obtains learning data, specially：
First low-pass filter, is used for：After the internal stabilized, the institute that is read from the DDS by the second
First frequency is stated to adjust in word, filter out the frequency of the OCXO at any time with total changing value of temperature change；
Second low-pass filter, is used for：The frequency aging at any time of the OCXO is filtered out from total changing value
The first drift value；
The subtracter, for total changing value to be subtracted first drift value, obtain the frequency of the OCXO with
Second drift value of temperature change；
The third low-pass filter, for being filtered to second drift value；
It is flat to obtain first for carrying out sliding average calculating to first drift value for the first sliding average unit
Drift value after；
It is flat to obtain second for carrying out sliding average calculating to second drift value for the second sliding average unit
Drift value after；
Kalman's time Ageing Model is trained for being based on the described first average rear drift value, obtains first
Part learning data；
Kalman's temperature drift model is trained for being based on the described second average rear drift value, obtains second
Part learning data；
Drift forecasting is carried out to the OCXO according to the learning data, obtains drift forecasting as a result, being specially：
When the source of synchronising signal is lost, cuts off from the DDS and read the process that the first frequency adjusts word；
The filter compensation of delay obtains delay and mends for carrying out compensation of delay to the second part learning data
Repay rear learning data；
The adder is used for learning data after the compensation of delay and first part's learning data, Yi Jisuo
It states the first frequency adjusting word initially obtained to be overlapped, obtains the drift forecasting result；
Optionally, the Synchronization Clock further includes：
Temperature sensor, for controlling input temp benchmark to Kalman's temperature drift model so that the karr
Graceful temperature drift model carries out the training of the described first average rear drift value with the fiducial temperature.
Optionally, Kalman's time Ageing Model, is specifically used for：Using second target clock signal as time base
Standard carries out the training to the described second drift value after average.
Optionally, the frequency of the goal systems clock signal is specially：1PPS；
The frequency of the first object clock signal is specially：10M；
The frequency of second target clock signal is specially：1PPS；
The frequency of the source of synchronising signal is specially：1PPS.
Optionally, Kalman's time Ageing Model based on the described first drift value after average be trained when it is a length of
2 hours；
Kalman's temperature drift model based on the described second drift value after average be trained when it is 2 hours a length of.
The one or more technical solutions provided in the embodiment of the present invention, have at least the following technical effects or advantages：
By being provided with field programmable gate array, it is used within the period that the positioning signal is lost, output driving
The pre- measured frequency of Direct Digital Synthesizer DDS adjusts word in digital frequency synthesizer, until give positioning signal for change again,
Digital frequency synthesizer adjusts word before not receiving source of synchronising signal, according to predeterminated frequency and exports first object clock outward
Signal adjusts word according to first frequency and exports first object clock signal outward within the period there are source of synchronising signal, with
And within the source of synchronising signal not available period, word is adjusted according to pre- measured frequency and exports first object clock signal outward.From
And can ensure that within the period that positioning signal is lost, providing pre- measured frequency by field programmable gate array adjusts word, makes
Digital frequency synthesizer is obtained within the period that positioning signal is lost, first can accurately be exported by adjusting word according to pre- measured frequency
Target clock signal, rather than GPS signal then keeps the operating value of last time after losing, therefore improve the standard of synchronised clock
True property.
Further, it due to receiving GPS positioning signal and Big Dipper positioning signal simultaneously, is selected according to signal quality and priority
It is source of synchronising signal to select one, which thereby enhances the stability and reliability of source of synchronising signal, and then improves synchronised clock dress
The reliability set.
Further, pass through the improved Kalman filter correcting algorithm of proposition (Kalman's time Ageing Model+Kalman's temperature
Spend drift model) holding algorithm model as the holding stage, also in Kalman's time Ageing Model, Kalman's temperature drift mould
The input stage of type does 100 sliding averages to reduce the variance of the shake of input signal, to improve Kalman Filtering correction
Stability and veracity, and then improve Synchronization Clock keep the stage accuracy and stability.
Further, by switching the DPLL allocation lists inside integrated digital frequency synthesizer, phase-locked loop is reduced step by step
Width enables internal phaselocked loop to be rapidly locked in extremely low bandwidth in the case of not losing lock, enables a system to rapidly
The intrinsic shake of 1PPS is reduced to very low range, net synchronization capability is improved, so as to avoid the 1PPS of GPS is passed through in the prior art
And stable bandwidth is locked to for OCXO when drift situation of the method at the voltage-controlled end of DAC controls OCXO to correct OCXO
Need the defect taken a long time.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, others are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is the structural schematic diagram of Synchronization Clock provided in an embodiment of the present invention；
Fig. 2 is the structure diagram of field programmable gate array in Fig. 1.
Specific implementation mode
The embodiment of the present invention is by providing a kind of Synchronization Clock, in order to better understand the above technical scheme, below
Figure of description and specific embodiment will be combined, and the above described technique is demenstrated in detail.
Refering to what is shown in Fig. 1, the embodiment of the present invention provides a kind of Synchronization Clock, including：Locating module 1, numerical frequency
Synthesizer 2, constant-temperature crystal oscillator 3, FPGA (Field-Programmable Gate Array, field programmable gate array)
4, temperature sensor 5.
Locating module 1 is generated based on the positioning signal and is synchronized for receiving the positioning signal from positioning service system
Signal source；Digital frequency synthesizer 2, for locking the source of synchronising signal；Constant-temperature crystal oscillator 3, for the number
Frequency synthesizer 2 provides original system clock signal；Field programmable gate array 4, for when the positioning signal is lost
Between in section, DDS (Direct Digital Synthesizer, Direct Digital in digital frequency synthesizer 2 described in output driving
Formula frequency synthesizer) 205 pre- measured frequency adjusts word, until give the positioning signal for change again；Wherein, described in not receiving
Before source of synchronising signal, is provided to the Direct Digital Synthesizer 205 and drive the Direct Digital Synthesizer
205 predeterminated frequency adjusts word, defeated under the action of the source of synchronising signal within there are the period of the source of synchronising signal
Go out to drive the first frequency of the Direct Digital Synthesizer 205 to adjust word；The digital frequency synthesizer 2, is additionally operable to
Word is adjusted according to the predeterminated frequency before not receiving the source of synchronising signal and exports first object clock signal outward,
There are adjust word according to the first frequency in the period of the source of synchronising signal to export the first object clock letter outward
Number, within the source of synchronising signal not available period, when exporting the first object outward according to pre- measured frequency adjusting word
Clock signal.
Specifically, refering to what is shown in Fig. 2, locating module 1 includes：The receiver unit of M kind positioning service systems, for simultaneously
The respective positioning signal of M kinds positioning service system is received, M is the integer more than 1；Signal behavior unit, for according to excellent
First grade selection strategy selects a positioning signal from the respective positioning signal of M kinds positioning service system, is determined as described
Source of synchronising signal.
In specific implementation process, the receiver unit of the M kinds positioning service system includes：GPS signal receiving unit
With Big Dipper signal receiving unit；The GPS signal receiving unit receives list for receiving Big Dipper signal described in GPS positioning signal
Member, for receiving Big Dipper positioning signal；The signal behavior unit is believed for giving tacit consent to using the GPS positioning signal as synchronous
Number source switches to the Big Dipper positioning signal as source of synchronising signal when the GPS positioning signal received is unavailable,
Until the signal quality of the GPS positioning signal returns back to default value or more, and the signal quality of the GPS positioning signal is super
When crossing the peak signal sensitivity of the Big Dipper positioning signal received by the Big Dipper signal receiving unit, then switch back into described
GPS positioning signal is the source of synchronising signal, if the GPS positioning signal and the Big Dipper positioning signal are unavailable,
Into the holding stage until meeting the condition for exiting the holding stage.
Specifically, default value could be provided as -148dBm.It should be noted that GPS positioning signal is unavailable, it can
Think：If signal quality is less than -148dBm, then it is assumed that GPS positioning signal is unavailable.GPS positioning dropout, specially：
GPS signal receiving unit does not receive GPS positioning signal.
Specifically, after entering the holding stage, the still signal quality of detection GPS positioning signal and Big Dipper positioning in real time
The signal quality of signal entered in 12 hours holding stages, collects GPS positioning signal or Big Dipper positioning signal and can be used
When, wait for 10 minutes, if collected GPS positioning signal signal quality or Big Dipper positioning signal signal quality 10
Minute in continue and signal quality stablize rise, then exit the holding stage, if into the holding stage exceed 12 hours, system one
Denier receives GPS positioning signal or Big Dipper positioning signal, then exits the holding stage.
Rise it should be noted that signal quality is stablized, can refer to：Collected GPS positioning signal signal matter
Amount the case where not declining occur or the signal quality of collected Big Dipper positioning signal the case where not declining occur.
By the above process, it realizes locating module 1 and receives positioning signal from antenna end, and believed according to GPS positioning
Number with the priority and GPS positioning signal of Big Dipper positioning signal and the suitable positioning of Big Dipper positioning signal signal quality selection
Signal is as the source of synchronising signal for being input to digital frequency synthesizer 2.
It further, can the specified selection source of synchronising signal of the manual operation based on user, it is not necessary to according to the excellent of synchronisation source
First grade is selected.
Shown in Fig. 2, digital frequency synthesizer 2 includes：Phase frequency detector 201, loop filter 202, frequency
Adjust word processing device 203, internal phaselocked loop 204, Direct Digital Synthesizer 205, clock distribution output par, c 206.
Phase frequency detector 201 generates the source of synchronising signal for carrying out frequency and phase discrimination processing to the source of synchronising signal
Departure.
Specifically, the frequency of the source of synchronising signal generated by locating module 1 is 1PPS, as phase frequency detector 201
Reference input, the source of synchronising signal of the 1PPS gives birth in phase frequency detector 201 with the feedback of Direct Digital Synthesizer 205
At goal systems clock signal carry out frequency and phase discrimination processing.Specifically, the signal frequency of goal systems clock signal with it is synchronous
The signal frequency of signal source is identical, specifically, the signal frequency of goal systems clock signal is 1PPS.
Loop filter 202, for being filtered to the departure, departure after being filtered.
Frequency adjusts word processing device 203, is adjusted for generating the first frequency according to departure processing after the filtering
Word.
Internal phaselocked loop 204, the original system clock signal for providing the constant-temperature crystal oscillator 3 become
Frequently, goal systems clock signal is generated, the goal systems clock signal is supplied to the phase frequency detector 201 so that described
Phase frequency detector 201 is based on the goal systems clock signal and carries out frequency and phase discrimination processing to the source of synchronising signal.
More specifically, the mix clock signal of Direct Digital Synthesizer 205 is fed back into feedback divider
207, it is divided from the mix clock signal of Direct Digital Synthesizer 205 by feedback divider and obtains signal frequency and be
The goal systems clock signal of 1PPS, is supplied to phase frequency detector 201.
Direct Digital Synthesizer 205, is used for：According to the default frequency before not receiving the positioning signal
Rate adjusts word and the goal systems clock signal generates mix clock signal；Within there are the period of the positioning signal,
Word is adjusted according to the first frequency and the goal systems clock signal exports the mix clock signal, is believed in the positioning
In number not available period, word is adjusted according to pre- measured frequency and the goal systems clock signal exports the mix clock and believes
Number.
Clock distribution output par, c 206, the mix clock letter for exporting the Direct Digital Synthesizer 205
It number is allocated, obtains the first object clock signal exported outward, and be supplied to the field programmable gate array 4
The second target clock signal.
In specific implementation process, first object clock signal is that frequency is 10M, the frequency of the second target target clock signal
Rate is 1PPS.
Specifically, internal phaselocked loop 204 is specially DPLL (Digital Phase Locked Loop, digital phase-locked loop).
In specific implementation process, due to by the shake of the source of synchronising signal of the 1PPS be reduced to sufficiently low value need by
DPLL loop-lockings are in an extremely low bandwidth, and for the locking demand, the chip interior of digital frequency synthesizer 2 is carried
The attribute list of DPLL constrain the feature of DPLL, when which constrains the primal system of input digital frequency synthesizer 2
The electrical and frequency characteristic of clock signal, bandwidth of phase lock loop, phase margin and phase frequency detector 201 parameters.
And 2 inside of digital frequency synthesizer carries the above-mentioned attribute list of 8 same sizes, and family can be used certainly by the table
The various features of DPLL are defined by ground.In order to enable DPLL loops to be locked in extremely low bandwidth of phase lock loop, based on number frequency
8 attribute lists inside rate synthesizer 2 reduce bandwidth of phase lock loop step by step to change the mode of bandwidth of phase lock loop.Specific method
For：It is the original system clock signal of same reference by the feature constraint of the input signal of 8 attribute lists, and the correlation of DPLL
Its complementary characteristic all same, only change DPLL bandwidth of phase lock loop one, step by step reduce DPLL loop bandwidths.It is filled in synchronised clock
When setting initial start, due to needing to complete the fast Acquisition for DPLL loops and locking, constrained using high bandwidth value
Loop reduces loop bandwidth after DPLL loop stabilities.
The bandwidth of DPLL loops is gradually set to be locked to 0.007Hz always from 0.05Hz by the above method.Wherein, work as locking
When band is wider than 0.01Hz, 10 minutes bandwidth for just switching loop only after locking, but if loop causes to lose because of switching
Lock continues to loop tracks up to being returned to a bandwidth value after ten minutes.When loop is already below 0.001Hz, due at this time
The bandwidth of DPLL loops is very low, if switching bandwidth easily causes the losing lock of DPLL loops too quickly, uses and works as ring
The method that road locking reduces loop bandwidth after twenty minutes, DPLL loops cause losing lock up to being returned to after twenty minutes because of switching
A upper bandwidth value continues to upper bandwidth loop tracks, by being operated above until finally by DPLL loop-lockings in 0.007Hz
In bandwidth.
Bandwidth of phase lock loop switching method is used by above-mentioned, can flexibly and steadily make phase lock loop locks in the band of very little
In width, to the intrinsic shake of the GPS positioning signal of more efficiently reduction 1PPS, net synchronization capability is promoted.
Clock is stably locked in a relatively short period of time under extremely low bandwidth, the output of Synchronization Clock is improved
Clock quality and stability, and improve the flexibility ratio and reliability of synchronised clock.
Specifically, in the presence of the source of synchronising signal, field programmable gate array 4 is based on Kalman filtering algorithm model
The drift behavior of the constant-temperature crystal oscillator 3 is learnt, learning data is obtained；When the source of synchronising signal is lost
Between in section, field programmable gate array 4 carries out drift forecasting according to the learning data to the constant-temperature crystal oscillator 3, obtains
To drift forecasting result；Field programmable gate array 4 is adjusted according to the drift forecasting output control output pre- measured frequency
Word, field programmable gate array 4 adjust Direct Digital Synthesizer 205 described in word drive according to pre- measured frequency, until weight
Newly give the source of synchronising signal for change.
It should be noted that pre- measured frequency adjusts word, first frequency adjusts word, predeterminated frequency adjusts word this three and only uses
In to being which component to provide differentiation name rather than the crossover frequency adjusting word that frequency adjusts word by.
Specifically, it in order to which the frequency drift to constant-temperature crystal oscillator 3 is corrected, in conjunction with aforementioned embodiments, carries
It is based on the corrected embodiment of Kalman filtering algorithm model for a kind of field programmable gate array 4, is described as follows：
Refering to what is shown in Fig. 2, field programmable gate array 4 includes：First low-pass filter 401, the second low-pass filter
402, subtracter 403, third low-pass filter 404, the first sliding average unit 405, the second sliding average unit 406, karr
Graceful time Ageing Model 407, Kalman's temperature drift model 408, filter compensation of delay 409, adder 410.
In the presence of the source of synchronising signal, based on Kalman filtering algorithm model to the constant-temperature crystal oscillator 3
Drift behavior is learnt, and obtains learning data, specially：First low-pass filter 401, in the internal locking phase
After ring 204 is stablized, adjusts in word, filter out from the first frequency that the Direct Digital Synthesizer 205 is read by the second
The frequency of the constant-temperature crystal oscillator 3 at any time with total changing value of temperature change；Second low-pass filter 402 is used
In the first drift value for filtering out the aging at any time of the frequency of the constant-temperature crystal oscillator 3 from total changing value；
The subtracter 403 show that the constant temperature crystal shakes for total changing value to be subtracted first drift value
Swing the second drift value that the frequency of device 3 varies with temperature；The third low-pass filter 404, for second drift value
It is filtered；The first sliding average unit 405 obtains for carrying out sliding average calculating to first drift value
One average rear drift value；The second sliding average unit 406, by being carried out based on sliding average to filtered second drift value
It calculates, obtains the second average rear drift value；Kalman's time Ageing Model 407, for drifting about after being based on described first averagely
Value is trained, and obtains first part's learning data；Kalman's temperature drift model 408, for flat based on described second
Drift value is trained after, obtains second part learning data.
Drift forecasting is carried out to the constant-temperature crystal oscillator 3 according to the learning data, obtains drift forecasting as a result, tool
Body is：When the source of synchronising signal is lost, cut-out reads the first frequency from the Direct Digital Synthesizer 205
Adjust the process of word；The filter compensation of delay 409 is obtained for carrying out compensation of delay to the second part learning data
Learning data after to compensation of delay；The adder 410 is used for learning data after the compensation of delay and the first part
Learning data and the first frequency initially obtained adjust word and are overlapped, and obtain the drift forecasting result.
Temperature sensor 5, for controlling input temp benchmark to Kalman's temperature drift model 408 so that described
Kalman's temperature drift model 408 carries out the training of the described first average rear drift value with the fiducial temperature.
Kalman's time Ageing Model 407, is specifically used for：Using second target clock signal as time reference,
Carry out the training to the described second drift value after average.
The frequency of the goal systems clock signal is specially：1PPS；The frequency of the first object clock signal is specific
For：10M；The frequency of second target clock signal is specially：1PPS；The frequency of the source of synchronising signal is specially：1PPS.
Kalman's time Ageing Model 407 based on the described first drift value after average be trained when it is a length of 2 small
When；Kalman's temperature drift model 408 based on the described second drift value after average be trained when it is 2 hours a length of.
Due to the quality problems of the source of synchronising signal, so the source of synchronising signal that locating module 1 provides can not be used for directly
The synchronous clock source as system is connect, after digital frequency synthesizer 2 completes the above-mentioned source of synchronising signal locking to 1PPS, energy
The jitter amplitude of enough source of synchronising signals for reducing 1PPS well.
Due to, as synchronous clock source, existing by GPS signal, reception positioning signal is unstable to cause GPS signal to be lost
Situation, therefore keep process to pass through Kalman filtering algorithm in the presence of GPS signal the system after positioning signal loss
Model learns local constant-temperature crystal oscillator 3 with the drift behavior of temperature at any time, after being synchronized after GPS signal loss
By learning data of the Kalman filtering algorithm model before to the drift situation of constant-temperature crystal oscillator 3 predicted into
And control the output of Direct Digital Synthesizer 205.Due to constant-temperature crystal oscillator 3 drift behavior there are mainly two types of, one
A is the drift situation that the frequency of constant-temperature crystal oscillator 3 varies with temperature, one be the frequency of constant-temperature crystal oscillator 3 at any time
Between variation aging drift situation.
Wherein, since the drift of frequency at any time is to change slowly, variation with temperature is fast variation.Therefore specific algorithm
Scheme is, after DPLL stablizes in 0.007Hz bandwidth, by the first frequency of Direct Digital Synthesizer 205 adjust word by
What the second read out from digital frequency synthesizer 2, then the first frequency read out adjusting word is sequentially sent to by scene
Programmable gate array 4, by the first low-pass filter 401 of 600uHz in field programmable gate array 4 filter out frequency at any time and
Total changing value of temperature then filters out frequency aging at any time by the second low-pass filter 402 of 20uHz from total changing value
The first drift value, two above-mentioned results are subtracted each other, obtain the second drift value that frequency varies with temperature.By aforesaid operations
The frequency of constant-temperature crystal oscillator 3 is filtered out respectively afterwards at any time with the drift situation of temperature, it is then that frequency is old at any time
The first drift value changed is sent into 100 points of the first sliding average unit 405, for the first drift value to carrying out 100 points of cunning
Dynamic average computation, obtains the first average rear drift value, and the third that the second drift value that frequency varies with temperature enters 600uHz is low
Bandpass filter 404 is filtered second drift value.Filtered second drift value is flat into 100 points of the second sliding
Equal unit 406 carries out filtered second drift value 100 points of sliding average and calculates, and obtains the second average rear drift value.With
This further decreases the variance of Kalman's time Ageing Model 407,408 input jiffer of Kalman's temperature drift model, to
It reduces the duration of module training and study Drift Process and reduces the instability of system.
The first average rear drift value after 100 points of sliding average is calculated passes through using the time as Kalman's time of variable
It is trained in Ageing Model 407, obtains first part's learning data.Wherein, the time is trained on the basis of 1 second.By 100
The second average rear drift value after the sliding average of point calculates passes through using temperature as in Kalman's temperature drift model 408 of variable
It is trained, obtains second part learning data.Wherein, temperature is trained on the basis of 0.1 degree Celsius.When entire Kalman
Between Ageing Model 407 and Kalman's temperature drift model 408 training operation duration be 2 hours.After the completion of training, such as
Fruit positioning signal is lost, then the first frequency of Direct Digital Synthesizer 205 is read in cut-out from digital frequency synthesizer 2
Adjust word.Directly Kalman's time Ageing Model 407, Kalman's temperature drift model 408 are linearly estimated from winding respectively
Meter output, by second part learning data carry out after delay 3600s with first part's learning data and initial first frequency
It adjusts word to be overlapped, the Direct Digital Synthesizer 205 that output directly drives digital frequency synthesizer 2 is exported.
Further, 1PPS signals digital frequency synthesizer 2 generated are as the card in the field programmable gate array 4
The time reference of the time drift of Germania time Ageing Model 407 is completed by the second to the frequency of Direct Digital Synthesizer 205
Rate adjusts the time reference of the reading and write operation and internal system clock timing of word, the operation of the synchronization of data frame.
Using the subsidiary temperature sensor 5 of board, the temperature of current board is read repeatedly and the temperature sensor 5 is done
100 points are averaged, to eliminate temperature sensor 5 reading numerical values shake to 408 accuracy of Kalman's temperature drift model
Influence.Temperature sensor 5 is input to Kalman's temperature drift model 408 with 0.1 degree Celsius for a unit quantity.
In preferred technical solution, if Kalman's time Ageing Model 407, Kalman's temperature drift model 408 exist
When there is the case where positioning signal loss in training process, the direct number that will be recorded in the presence of the source of synchronising signal of 1PPSD
The frequency of word formula frequency synthesizer 205 adjusts 100 sliding averages of word as final holding as a result, until finally again
Give positioning signal for change.
If GPS signal is lost during 100 sliding averages do not fully achieve, then 100 points of slidings are used
The average value finally calculated adjusts the value of word as the frequency of the Direct Digital Synthesizer 205 in holding stage.
Specifically, locating module 1 receives Big Dipper positioning signal, GPS positioning signal from antenna end, and according to preferential
The signal quality of grade and Big Dipper positioning signal and GPS positioning signal selects suitable positioning signal as source of synchronising signal, fixed
The source of synchronising signal 1PPS received is passed to digital frequency synthesizer 2 as input by position module 1, and DPLL is not being received
When the source of synchronising signal of 1PPS, output adjusts word according to predeterminated frequency and is exported, at this point, digital frequency synthesizer 2 is operated in
Free-running operation pattern.When the source of synchronising signal of 1PPS is effective, DPLL is first operated according to maximum DPLL bandwidth 0.05Hz,
When DPLL loop stabilities are lockked after ten minutes, DPLL switches to 0.03Hz bandwidth, same etc. to be locked and stablize 10 minutes and switch
0.02Hz bandwidth, same operation is until 0.01Hz, and according to steady lock, bandwidth drops after twenty minutes after bandwidth is less than 0.01Hz
Low one grade of rule is operated, if above-mentioned DPLL loops switch to a upper bandwidth after switching bandwidth long-time losing lock.Through
Cross after bandwidth is locked in 0.0067Hz by above-mentioned rule, loop settling time after twenty minutes, field programmable gate array 4 start by
The predeterminated frequency that second reads digital frequency synthesizer 2 adjusts word.And the predeterminated frequency is adjusted into word and is sent into field-programmable gate array
It is filtered inside row 4, filters out the variation numerical value with temperature and time respectively.And the two groups of data separated are carried out successively
100 sliding average processing further decrease the mean-square value of the shake of signal.The data that sliding average processing is completed are sent later
Enter in Kalman filter and is trained, training duration 2 hours.After the completion of taming and dociling white silk, if positioning signal is lost, Kalman's temperature
Output with Kalman's time Ageing Model 407 and initial first frequency after the output result delay 3600s of drift model 408
Adjust the pre- measured frequency adjusting word that word is overlapped rear output driving digital frequency synthesizer 2.If lost in the training process
When positioning signal, then use 100 sliding averages there are first frequencies when positioning signal to adjust word as runtime value input
Digital frequency synthesizer 2.
Specifically, digital frequency synthesizer 2 is specially to use AD9548 digital frequency synthesizers.
Specifically, when generating 1PPS signals as the Kalman using the digital frequency synthesizer 2 of model AD9548
Between Ageing Model 407 time drift time reference, complete to adjust the frequency of Direct Digital Synthesizer 205 by the second
The reading and write operation of word.
Collector using subsidiary 5 chip of temperature sensor of board as temperature, reads the temperature of current board repeatedly
And 100 sliding averages are done to the temperature sensor 5, to eliminate temperature sensor 5 reading numerical values shake to Kalman
The influence of 408 accuracy of temperature drift model.Temperature sensor 5 is input to Kalman's temperature with 0.1 degree Celsius for a unit quantity
Spend drift model 408.
If losing 1PPS in Kalman's time Ageing Model 407, the process of the training of Kalman's temperature drift model 408
Source of synchronising signal, by the Direct Digital Synthesizer 205 recorded in the presence of the source of synchronising signal of 1PPS first frequency
Rate adjusts the result that word 100 sliding averages of progress calculate and adjusts word as final pre- measured frequency, keeps the pre- measured frequency
Word is adjusted until finally giving positioning signal for change again.If positioning letter during 100 sliding averages do not fully achieve
Number lose, then use 100 sliding averages latest entry as the holding stage pre- measured frequency adjusting word.
One or more embodiment provided in an embodiment of the present invention, has implemented following technique effect or advantage：
By being provided with field programmable gate array, it is used within the period that the positioning signal is lost, output driving
The pre- measured frequency of Direct Digital Synthesizer DDS adjusts word in digital frequency synthesizer, until give positioning signal for change again,
Digital frequency synthesizer adjusts word before not receiving source of synchronising signal, according to predeterminated frequency and exports first object clock outward
Signal adjusts word according to first frequency and exports first object clock signal outward within the period there are source of synchronising signal, with
And within the source of synchronising signal not available period, word is adjusted according to pre- measured frequency and exports first object clock signal outward.From
And can ensure that within the period that positioning signal is lost, providing pre- measured frequency by field programmable gate array adjusts word, makes
Digital frequency synthesizer is obtained within the period that positioning signal is lost, first can accurately be exported by adjusting word according to pre- measured frequency
Target clock signal, rather than GPS signal then keeps the operating value of last time after losing, therefore improve the standard of synchronised clock
True property.
Further, it due to receiving GPS positioning signal and Big Dipper positioning signal simultaneously, is selected according to signal quality and priority
It is source of synchronising signal to select one, which thereby enhances the stability and reliability of source of synchronising signal, and then improves synchronised clock dress
The reliability set.
Further, pass through the improved Kalman filter correcting algorithm of proposition (Kalman's time Ageing Model+Kalman's temperature
Spend drift model) holding algorithm model as the holding stage, also in Kalman's time Ageing Model, Kalman's temperature drift mould
The input stage of type does 100 sliding averages to reduce the variance of the shake of input signal, to improve Kalman Filtering correction
Stability and veracity, and then improve Synchronization Clock keep the stage accuracy and stability.
Further, by switching the DPLL allocation lists inside integrated digital frequency synthesizer, phase-locked loop is reduced step by step
Width enables internal phaselocked loop to be rapidly locked in extremely low bandwidth in the case of not losing lock, enables a system to rapidly
The intrinsic shake of 1PPS is reduced to very low range, net synchronization capability is improved, so as to avoid the 1PPS of GPS is passed through in the prior art
And stable bandwidth is locked to for OCXO when drift situation of the method at the voltage-controlled end of DAC controls OCXO to correct OCXO
Need the defect taken a long time.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of Synchronization Clock, which is characterized in that including：
Locating module generates synchronizing signal for receiving the positioning signal from positioning service system based on the positioning signal
Source；
Digital frequency synthesizer, for locking the source of synchronising signal；
Constant-temperature crystal oscillator OCXO, for providing original system clock signal to the digital frequency synthesizer；
Field programmable gate array, within the period that the positioning signal is lost, numerical frequency described in output driving to be comprehensive
The pre- measured frequency of Direct Digital Synthesizer DDS adjusts word in clutch, until giving the positioning signal for change again；
Wherein, it before not receiving the source of synchronising signal, is provided to the DDS and the predeterminated frequency of the DDS is driven to adjust
Word, within there are the period of the source of synchronising signal, of DDS described in output driving under the action of the source of synchronising signal
One frequency adjusts word；
The digital frequency synthesizer is additionally operable to before not receiving the source of synchronising signal, according to the predeterminated frequency tune
Section word exports first object clock signal outward, within there are the period of the source of synchronising signal, according to the first frequency
It adjusts word and exports the first object clock signal outward, and within the source of synchronising signal not available period, according to
The pre- measured frequency adjusts word and exports the first object clock signal outward.
2. Synchronization Clock as described in claim 1, which is characterized in that the locating module includes：
The receiver unit of M kind positioning service systems, for receiving the respective positioning letter of the M kinds positioning service system simultaneously
Number, M is the integer more than 1；
Signal behavior unit is used for according to priority selection strategy from the respective positioning signal of M kinds positioning service system
A positioning signal is selected, the source of synchronising signal is determined as.
3. Synchronization Clock as claimed in claim 2, which is characterized in that the receiver list of the M kinds positioning service system
Member includes：GPS signal receiving unit and Big Dipper signal receiving unit；
The GPS signal receiving unit, for receiving GPS positioning signal；
The Big Dipper signal receiving unit, for receiving Big Dipper positioning signal；
The signal behavior unit, for giving tacit consent to using the GPS positioning signal as source of synchronising signal, described in receiving
When GPS positioning signal is unavailable, the Big Dipper positioning signal is switched to as source of synchronising signal, until the GPS positioning signal
Signal quality return back to default value or more, and the signal quality of the GPS positioning signal is received more than the Big Dipper signal
When the peak signal sensitivity of the Big Dipper positioning signal received by unit, then it is described same to switch back into the GPS positioning signal
Signal source is walked, if the GPS positioning signal and the Big Dipper positioning signal are unavailable, enters the holding stage until meeting
Exit the condition in holding stage.
4. Synchronization Clock as claimed in claim 2, which is characterized in that the digital frequency synthesizer further includes：
Phase frequency detector generates the deviation of the source of synchronising signal for carrying out frequency and phase discrimination processing to the source of synchronising signal
Amount；
Loop filter, for being filtered to the departure, departure after being filtered；
Frequency adjusts word processing device, and word is adjusted for generating the first frequency according to departure processing after the filtering；
Internal phaselocked loop, the original system clock signal for providing the OCXO carry out frequency conversion, generate goal systems clock
Signal, the goal systems clock signal are supplied to the phase frequency detector so that the phase frequency detector is based on the target
Clock signal of system carries out frequency and phase discrimination processing to the source of synchronising signal；
The DDS, is used for：Word and the target system are adjusted according to the predeterminated frequency before not receiving the positioning signal
Clock signal of uniting generates mix clock signal；Within there are the period of the positioning signal, adjusted according to the first frequency
Word and the goal systems clock signal export the mix clock signal, within the positioning signal not available period,
Word is adjusted according to pre- measured frequency and the goal systems clock signal exports the mix clock signal；
Clock distribution output par, c, the mix clock signal for exporting the DDS are allocated, and obtain the institute exported outward
First object clock signal is stated, and is supplied to the second target clock signal of the field programmable gate array.
5. Synchronization Clock as claimed in claim 4, which is characterized in that
In the presence of the source of synchronising signal, the field programmable gate array is based on Kalman filtering algorithm model to described
The drift behavior of OCXO is learnt, and learning data is obtained；
Within the period that the source of synchronising signal is lost, the field programmable gate array is according to the learning data to described
OCXO carries out drift forecasting, obtains drift forecasting result；
The field programmable gate array adjusts word according to the drift forecasting output control output pre- measured frequency, according to institute
It states pre- measured frequency and adjusts DDS described in word drive, until giving the source of synchronising signal for change again.
6. Synchronization Clock as claimed in claim 5, which is characterized in that the field programmable gate array includes：First
Low-pass filter, the second low-pass filter, subtracter, third low-pass filter, the first sliding average unit, the second sliding average
Unit, Kalman's time Ageing Model, Kalman's temperature drift model, filter compensation of delay, adder；
In the presence of the source of synchronising signal, based on Kalman filtering algorithm model to the drift behavior of the OCXO
It practises, obtains learning data, specially：
First low-pass filter, is used for：After the internal stabilized, from the DDS by the second read described the
One frequency is adjusted in word, filter out the frequency of the OCXO at any time with total changing value of temperature change；
Second low-pass filter, is used for：Filtered out from total changing value the frequency of the OCXO at any time aging
One drift value；
The subtracter obtains the frequency of the OCXO with temperature for total changing value to be subtracted first drift value
Second drift value of variation；
The third low-pass filter, for being filtered to second drift value；
The first sliding average unit, for carrying out sliding average calculating to first drift value, after obtaining first averagely
Drift value；
The second sliding average unit, for carrying out sliding average calculating to second drift value, after obtaining second averagely
Drift value；
Kalman's time Ageing Model is trained for being based on the described first average rear drift value, obtains first part
Learning data；
Kalman's temperature drift model is trained for being based on the described second average rear drift value, obtains second part
Learning data；
Drift forecasting is carried out to the OCXO according to the learning data, obtains drift forecasting as a result, being specially：
When the source of synchronising signal is lost, cuts off from the DDS and read the process that the first frequency adjusts word；
The filter compensation of delay, for carrying out compensation of delay to the second part learning data, after obtaining compensation of delay
Learning data；
The adder, for by learning data after the compensation of delay and first part's learning data and it is described just
The first frequency that beginning obtains adjusts word and is overlapped, and obtains the drift forecasting result.
7. Synchronization Clock as claimed in claim 6, which is characterized in that the Synchronization Clock further includes：
Temperature sensor, for controlling input temp benchmark to Kalman's temperature drift model so that Kalman's temperature
Degree drift model carries out the training of the described first average rear drift value with the fiducial temperature.
8. Synchronization Clock as claimed in claim 6, which is characterized in that
Kalman's time Ageing Model, is specifically used for：Using second target clock signal as time reference, carry out to institute
State the training of the second average rear drift value.
9. Synchronization Clock as claimed in claim 3, which is characterized in that
The frequency of the goal systems clock signal is specially：1PPS；
The frequency of the first object clock signal is specially：10M；
The frequency of second target clock signal is specially：1PPS；
The frequency of the source of synchronising signal is specially：1PPS.
10. Synchronization Clock as claimed in claim 5, which is characterized in that Kalman's time Ageing Model is based on institute
State first it is average after drift value be trained when it is 2 hours a length of；
Kalman's temperature drift model based on the described second drift value after average be trained when it is 2 hours a length of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810228186.4A CN108521324B (en) | 2018-03-20 | 2018-03-20 | Synchronous clock device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810228186.4A CN108521324B (en) | 2018-03-20 | 2018-03-20 | Synchronous clock device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108521324A true CN108521324A (en) | 2018-09-11 |
| CN108521324B CN108521324B (en) | 2021-07-13 |
Family
ID=63433996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810228186.4A Active CN108521324B (en) | 2018-03-20 | 2018-03-20 | Synchronous clock device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108521324B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110430614A (en) * | 2019-08-06 | 2019-11-08 | 深圳前海中电慧安科技有限公司 | Base station signal synchronous method, device, equipment and storage medium based on GPS signal |
| CN111245593A (en) * | 2020-01-03 | 2020-06-05 | 北京邮电大学 | Time synchronization method and device based on Kalman filtering |
| CN112782725A (en) * | 2020-12-30 | 2021-05-11 | 华清瑞达（天津）科技有限公司 | High-precision GPS synchronization maintaining module |
| CN112821976A (en) * | 2020-12-31 | 2021-05-18 | 锐捷网络股份有限公司 | Method and device for maintaining local clock synchronization |
| CN113078900A (en) * | 2021-03-30 | 2021-07-06 | 中国核动力研究设计院 | System and method for improving clock source performance of DCS (distributed control System) platform of nuclear power plant |
| CN113460124A (en) * | 2020-03-30 | 2021-10-01 | 比亚迪股份有限公司 | Train running time processing method and device, computer equipment and storage medium |
| CN114337655A (en) * | 2020-09-29 | 2022-04-12 | 广州慧睿思通科技股份有限公司 | Time service device circuit |
| CN116318204A (en) * | 2023-03-31 | 2023-06-23 | 北京航天广通科技有限公司 | Signal source combination suitable for high-power radio frequency system |
| CN116700094A (en) * | 2023-06-21 | 2023-09-05 | 哈尔滨博尼智能技术有限公司 | Data driving control system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201008145Y (en) * | 2007-02-16 | 2008-01-16 | 中国科学院武汉物理与数学研究所 | Rubidium atom frequency scale digital phase-locked frequency multiplier |
| CN102436174A (en) * | 2011-10-26 | 2012-05-02 | 东莞市泰斗微电子科技有限公司 | Method and corresponding device for taming crystal oscillation frequency of time-keeping device |
| US20120269205A1 (en) * | 2011-04-19 | 2012-10-25 | Honeywell International, Inc. | Novel low latency and self-adjusting frame synchronization algorithm for data streaming applications |
| CN104765045A (en) * | 2015-04-27 | 2015-07-08 | 成都振芯科技股份有限公司 | Beidou foundation navigation network ground monitoring station pseudolite and control method |
| CN106877963A (en) * | 2016-12-29 | 2017-06-20 | 河北远东通信系统工程有限公司 | A kind of synchronised clock with learning functionality keeps system and method |
| CN106980133A (en) * | 2017-01-18 | 2017-07-25 | 中国南方电网有限责任公司超高压输电公司广州局 | The GPS INS Combinated navigation methods and system for being compensated and being corrected using neural network algorithm |
-
2018
- 2018-03-20 CN CN201810228186.4A patent/CN108521324B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201008145Y (en) * | 2007-02-16 | 2008-01-16 | 中国科学院武汉物理与数学研究所 | Rubidium atom frequency scale digital phase-locked frequency multiplier |
| US20120269205A1 (en) * | 2011-04-19 | 2012-10-25 | Honeywell International, Inc. | Novel low latency and self-adjusting frame synchronization algorithm for data streaming applications |
| CN102436174A (en) * | 2011-10-26 | 2012-05-02 | 东莞市泰斗微电子科技有限公司 | Method and corresponding device for taming crystal oscillation frequency of time-keeping device |
| CN104765045A (en) * | 2015-04-27 | 2015-07-08 | 成都振芯科技股份有限公司 | Beidou foundation navigation network ground monitoring station pseudolite and control method |
| CN106877963A (en) * | 2016-12-29 | 2017-06-20 | 河北远东通信系统工程有限公司 | A kind of synchronised clock with learning functionality keeps system and method |
| CN106980133A (en) * | 2017-01-18 | 2017-07-25 | 中国南方电网有限责任公司超高压输电公司广州局 | The GPS INS Combinated navigation methods and system for being compensated and being corrected using neural network algorithm |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110430614A (en) * | 2019-08-06 | 2019-11-08 | 深圳前海中电慧安科技有限公司 | Base station signal synchronous method, device, equipment and storage medium based on GPS signal |
| CN111245593A (en) * | 2020-01-03 | 2020-06-05 | 北京邮电大学 | Time synchronization method and device based on Kalman filtering |
| CN113460124A (en) * | 2020-03-30 | 2021-10-01 | 比亚迪股份有限公司 | Train running time processing method and device, computer equipment and storage medium |
| CN114337655A (en) * | 2020-09-29 | 2022-04-12 | 广州慧睿思通科技股份有限公司 | Time service device circuit |
| CN112782725A (en) * | 2020-12-30 | 2021-05-11 | 华清瑞达（天津）科技有限公司 | High-precision GPS synchronization maintaining module |
| CN112821976A (en) * | 2020-12-31 | 2021-05-18 | 锐捷网络股份有限公司 | Method and device for maintaining local clock synchronization |
| CN112821976B (en) * | 2020-12-31 | 2023-03-24 | 锐捷网络股份有限公司 | Method and device for maintaining local clock synchronization |
| CN113078900A (en) * | 2021-03-30 | 2021-07-06 | 中国核动力研究设计院 | System and method for improving clock source performance of DCS (distributed control System) platform of nuclear power plant |
| CN113078900B (en) * | 2021-03-30 | 2022-07-15 | 中国核动力研究设计院 | System and method for improving performance of clock source of DCS platform of nuclear power plant |
| CN116318204A (en) * | 2023-03-31 | 2023-06-23 | 北京航天广通科技有限公司 | Signal source combination suitable for high-power radio frequency system |
| CN116700094A (en) * | 2023-06-21 | 2023-09-05 | 哈尔滨博尼智能技术有限公司 | Data driving control system |
| CN116700094B (en) * | 2023-06-21 | 2024-03-01 | 哈尔滨博尼智能技术有限公司 | Data driving control system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108521324B (en) | 2021-07-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108521324A (en) | Synchronous clock device | |
| CA2246146C (en) | Direct digital phase synthesis | |
| CN105960759B (en) | Two phase-locked loop and corresponding method and purposes with frequency stability | |
| US6259328B1 (en) | Method and system for managing reference signals for network clock synchronization | |
| EP0453280B1 (en) | PLL frequency synthesizer | |
| JP2001503940A (en) | Method and apparatus for reducing standby current of communication equipment | |
| CN103004096A (en) | Digital phase-locked loop clock system | |
| TW200522524A (en) | Clock synchroniser | |
| US10763837B2 (en) | Reference oscillator with variable duty cycle, frequency synthesizer and signal receiver with reference oscillator | |
| EP1107457A3 (en) | Method of synchronizing a phase-locked loop, phase-locked loop and semiconductor provided with same | |
| US7148753B1 (en) | Method and apparatus for generating a clock signal in holdover mode | |
| CN107547161B (en) | A kind of clock synchronizing method and device | |
| US11356108B2 (en) | Frequency generator and associated method | |
| TWI462498B (en) | Apparatus for fast phase locked loop (pll) settling for cellular time-division duplexing (tdd) communications systems | |
| CN101399542A (en) | Phase lock loop having temperature drift compensation and method thereof | |
| CN101610123B (en) | Clock unit and realization method thereof | |
| CN106712888A (en) | High-stability time base signal output system | |
| US5936565A (en) | Digitally controlled duty cycle integration | |
| CN104639158B (en) | Synchronous two phase-locked loop adjusting method | |
| CN201270504Y (en) | Frequency synthesizer | |
| CN104467817B (en) | One kind finely tuning algorithm applied to the loop of automatic frequency control system (AFC) | |
| US20110215872A1 (en) | Semiconductor integrated circuit | |
| EP0454955B1 (en) | Sampling clock generating circuit | |
| CN109067395A (en) | A kind of Phase synchronization Low phase noise Phase locking frequency synthesis device | |
| CN204886924U (en) | Frequency synthesizer with initial phase synchronization function |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |