CN108521324A - Synchronous clock device - Google Patents

Abstract

The invention discloses a synchronous clock device, comprising: a positioning module, which receives a positioning signal from a positioning service system, and generates a synchronous signal source based on the positioning signal; a digital frequency synthesizer, which locks the synchronous signal source; a constant temperature crystal oscillator, which provides The digital frequency synthesizer provides the original system clock signal; the field programmable gate array, in the time period when the positioning signal is lost, outputs the predicted frequency adjustment word that drives the DDS in the digital frequency synthesizer until the positioning signal is found again; Before the synchronization signal source, provide the DDS with the preset frequency adjustment word for driving the DDS, and output the first frequency adjustment word for driving the DDS under the action of the synchronization signal source during the time period when the synchronization signal source exists; the digital frequency synthesizer output The word first target clock signal is adjusted according to the frequency. The technical problem of inaccurate clock signal output by the synchronous clock device in the prior art after the GPS module is lost is solved.

Description

A synchronous clock device

technical field

The invention relates to the field of wireless communication, in particular to a synchronous clock device.

Background technique

For a wireless communication system in a TDD (Time-division Duplex, time-division duplex) mode, accurate clock synchronization is crucial to the realization of system functions and the improvement of performance. The synchronization of the system mainly includes the synchronization between the base station and the controller, between the base station and the base station, and between the base station and the terminal. For example: for TD-LTE (Time Division Long Term Evolution, Time Division Long Term Evolution) base stations, all base stations need to meet the time synchronization accuracy of 3us and the frequency accuracy of 0.05ppm.

The current solution for synchronization technology is to receive the 1PPS signal on the satellite through the GPS module, and then pass the 1PPS signal on the satellite and the 1PPS signal generated by the frequency division of the local OCXO (Oven Controlled Crystal Oscillator, Oven Controlled Crystal Oscillator). The digital chip performs digital frequency discrimination and phase discrimination processing inside the digital chip, and performs sliding average processing through the internal accumulator to output according to the internal filtering principle of the phase-locked loop. The voltage control terminal of the local OCXO adjusts the clock frequency of the OCXO. Through the digital phase-locked loop, the 1PPS signal received by GPS is used to correct the deviation of the local OCXO crystal oscillator over time and temperature. When the GPS signal is lost, the last operating value will be maintained. Because the last operating value will be maintained after the GPS signal is lost, the output clock signal will become less and less stable due to the deviation with time and temperature after the positioning signal is lost. precise.

Contents of the invention

The embodiment of the present invention provides a synchronous clock device, which solves the technical problem in the prior art that the synchronous clock device outputs an inaccurate clock signal after the GPS module is lost.

A synchronous clock device provided by an embodiment of the present invention includes:

A positioning module, configured to receive a positioning signal from a positioning service system, and generate a synchronization signal source based on the positioning signal;

a digital frequency synthesizer for locking the synchronization signal source;

Constant temperature crystal oscillator OCXO, for providing the original system clock signal to the digital frequency synthesizer;

The field programmable gate array is used to output the predicted frequency adjustment word for driving the direct digital frequency synthesizer DDS in the digital frequency synthesizer during the time period when the positioning signal is lost, until the positioning signal is found again;

Wherein, before the synchronization signal source is not received, the preset frequency adjustment word for driving the DDS is provided to the DDS, and during the time period when the synchronization signal source exists, under the action of the synchronization signal source Outputting the first frequency adjustment word that drives the DDS;

The digital frequency synthesizer is further configured to output the first target clock signal according to the preset frequency adjustment word before receiving the synchronization signal source, and during the time period when the synchronization signal source exists, Outputting the first target clock signal according to the first frequency adjustment word, and outputting the first target clock signal according to the predicted frequency adjustment word during the time period when the synchronization signal source is unavailable .

Optionally, the positioning module includes:

The receiver unit of M types of positioning service systems is used to simultaneously receive the respective positioning signals of the M types of positioning service systems, and M is an integer greater than 1;

The signal selection unit is configured to select one positioning signal from the respective positioning signals of the M types of positioning service systems according to a priority selection strategy, and determine it as the source of the synchronization signal.

Optionally, the receiver unit of the M positioning service system includes: a GPS signal receiving unit and a Beidou signal receiving unit;

The GPS signal receiving unit is used to receive GPS positioning signals;

The Beidou signal receiving unit is used to receive Beidou positioning signals;

The signal selection unit is configured to use the GPS positioning signal as a synchronization signal source by default, and switch to the Beidou positioning signal as a synchronization signal source when the received GPS positioning signal is unavailable until the GPS positioning signal When the signal quality of the GPS positioning signal returns to above the preset value, and the signal quality of the GPS positioning signal exceeds the maximum signal sensitivity of the Beidou positioning signal received by the Beidou signal receiving unit, then switch back to the GPS positioning signal as the The synchronization signal source, if neither the GPS positioning signal nor the Beidou positioning signal is available, enters the hold phase until the conditions for exiting the hold phase are met.

Optionally, the digital frequency synthesizer also includes:

A frequency and phase detector, configured to perform frequency and phase detection processing on the synchronization signal source to generate an offset of the synchronization signal source;

A loop filter, configured to filter the deviation to obtain a filtered deviation;

A frequency adjustment word processor, configured to process and generate the first frequency adjustment word according to the filtered deviation amount;

The internal phase-locked loop is used to convert the original system clock signal provided by the OCXO to generate a target system clock signal, and the target system clock signal is provided to the frequency detector and phase detector, so that the frequency detector and phase detector performing frequency discrimination and phase discrimination processing on the synchronization signal source based on the target system clock signal;

The DDS is configured to: generate a mixed clock signal according to the preset frequency adjustment word and the target system clock signal before receiving the positioning signal; during the time period when the positioning signal exists, according to the The first frequency adjustment word and the target system clock signal output the mixed clock signal, and output the mixed clock signal according to the predicted frequency adjustment word and the target system clock signal during the time period when the positioning signal is unavailable.

The clock distribution output part is used for distributing the mixed clock signal output by the DDS to obtain the first target clock signal outputted and the second target clock signal provided to the field programmable gate array.

Optionally, when the synchronization signal source exists, the field programmable gate array learns the drift behavior of the OCXO based on a Kalman filter algorithm model to obtain learning data;

During the time period when the synchronization signal source is lost, the field programmable gate array performs drift prediction on the OCXO according to the learning data, and obtains a drift prediction result;

The field programmable gate array controls the output of the predicted frequency adjustment word according to the drift prediction result, and drives the DDS according to the predicted frequency adjustment word until the synchronization signal source is found again.

Optionally, the field programmable gate array includes: a first low-pass filter, a second low-pass filter, a subtractor, a third low-pass filter, a first moving average unit, a second moving average unit, Carl Mann time aging model, Kalman temperature drift model, filter delay compensation, adder;

When the synchronization signal source exists, the drift behavior of the OCXO is learned based on the Kalman filter algorithm model to obtain learning data, specifically:

The first low-pass filter is configured to: filter out the frequency of the OCXO from the first frequency adjustment word read by the DDS second by second after the internal phase-locked loop is stable. The total change value of the temperature change;

The second low-pass filter is configured to: filter out the first drift value of the frequency aging of the OCXO with time from the total change value;

The subtractor is used to subtract the first drift value from the total change value to obtain a second drift value of the frequency of the OCXO as it changes with temperature;

The third low-pass filter is used to filter the second drift value;

The first sliding average unit is configured to perform sliding average calculation on the first drift value to obtain the first averaged drift value;

The second sliding average unit is configured to perform sliding average calculation on the second drift value to obtain a second averaged drift value;

The Kalman time aging model is used for training based on the first average post-drift value to obtain a first part of learning data;

The Kalman temperature drift model is used for training based on the second average post-drift value to obtain a second part of learning data;

Perform drift prediction on the OCXO according to the learning data, and obtain a drift prediction result, specifically:

When the synchronization signal source is lost, cut off the process of reading the first frequency adjustment word from the DDS;

The filter delay compensation is used to perform delay compensation on the second part of learning data to obtain learning data after delay compensation;

The adder is configured to superimpose the delay-compensated learning data with the first part of learning data and the initially obtained first frequency adjustment word to obtain the drift prediction result;

Optionally, the synchronous clock device also includes:

A temperature sensor is used to control the input of a temperature reference to the Kalman temperature drift model, so that the Kalman temperature drift model performs training of the first average post-drift value with the reference temperature.

Optionally, the Kalman time aging model is specifically configured to: use the second target clock signal as a time reference to perform training on the second post-average drift value.

Optionally, the frequency of the target system clock signal is specifically: 1PPS;

The frequency of the first target clock signal is specifically: 10M;

The frequency of the second target clock signal is specifically: 1PPS;

The frequency of the synchronization signal source is specifically: 1PPS.

Optionally, the duration of training the Kalman time aging model based on the first average post-drift value is 2 hours;

The duration of training the Kalman temperature drift model based on the second average post-drift value is 2 hours.

One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

By setting the field programmable gate array, it is used to output and drive the predicted frequency adjustment word of the direct digital frequency synthesizer DDS in the digital frequency synthesizer during the time period when the positioning signal is lost, until the positioning signal is found again, the digital Before the frequency synthesizer receives the synchronization signal source, it outputs the first target clock signal according to the preset frequency adjustment word, and outputs the first target clock signal according to the first frequency adjustment word during the time period when the synchronization signal source exists signal, and output the first target clock signal according to the predicted frequency adjustment word during the time period when the synchronization signal source is unavailable. Therefore, it can be ensured that during the time period when the positioning signal is lost, the predicted frequency adjustment word is given by the field programmable gate array, so that the digital frequency synthesizer can accurately output the first frequency adjustment word according to the predicted frequency adjustment word during the time period when the positioning signal is lost. A target clock signal, rather than the GPS signal being lost, maintains the last operating value, thus improving the accuracy of the synchronized clock.

Further, since the GPS positioning signal and the Beidou positioning signal are received at the same time, one is selected as the synchronization signal source according to the signal quality and priority, thereby improving the stability and reliability of the synchronization signal source, thereby improving the reliability of the synchronization clock device .

Further, the proposed improved Kalman filter correction algorithm (Kalman time aging model + Kalman temperature drift model) is used as the maintenance algorithm model in the maintenance phase, and the input stages of the Kalman time aging model and the Kalman temperature drift model are also averaged. A 100-point moving average is performed to reduce the variance of the jitter of the input signal, thereby improving the accuracy and stability of the Kalman filter correction, thereby improving the accuracy and stability of the synchronous clock device in the hold phase.

Further, by switching the DPLL configuration table inside the integrated digital frequency synthesizer, the bandwidth of the phase-locked loop is reduced step by step, so that the internal phase-locked loop can quickly lock to an extremely low bandwidth without losing lock, so that the system can Quickly reduce the inherent jitter of 1PPS to a very small range, and improve the synchronization performance, thereby avoiding the OCXO's locking to a stable one when correcting the drift of the OCXO through the 1PPS of GPS and the method of controlling the voltage control end of the OCXO by DAC in the prior art Bandwidth takes a long time for the defect.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a synchronous clock device provided by an embodiment of the present invention;

FIG. 2 is a structural block diagram of the field programmable gate array in FIG. 1 .

Detailed ways

The embodiment of the present invention provides a synchronous clock device. In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation manners.

With reference to shown in Fig. 1, the embodiment of the present invention provides a kind of synchronous clock device, comprises: positioning module 1, digital frequency synthesizer 2, constant temperature crystal oscillator 3, FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) 4 , temperature sensor 5.

The positioning module 1 is used to receive a positioning signal from a positioning service system, and generates a synchronization signal source based on the positioning signal; a digital frequency synthesizer 2 is used to lock the synchronization signal source; a constant temperature crystal oscillator 3 is used to provide The digital frequency synthesizer 2 provides the original system clock signal; the field programmable gate array 4 is used to output and drive the DDS (Direct Digital Synthesizer, directly digital frequency synthesizer) 205 predicted frequency adjustment word, until the positioning signal is found again; wherein, before receiving the synchronization signal source, provide the direct digital frequency synthesizer 205 to drive the direct The preset frequency adjustment word of the digital frequency synthesizer 205, within the period of time when the synchronization signal source exists, under the action of the synchronization signal source, the output drives the first frequency adjustment of the direct digital frequency synthesizer 205 word; the digital frequency synthesizer 2 is also used to output the first target clock signal according to the preset frequency adjustment word before receiving the synchronization signal source, and to output the first target clock signal during the time period when the synchronization signal source exists Internally outputting the first target clock signal according to the first frequency adjustment word, and outputting the first target clock signal according to the predicted frequency adjustment word during the time period when the synchronization signal source is unavailable.

Specifically, as shown in FIG. 2 , the positioning module 1 includes: a receiver unit of M types of positioning service systems, for simultaneously receiving respective positioning signals of the M types of positioning service systems, where M is an integer greater than 1; a signal selection unit is used to select a positioning signal from the respective positioning signals of the M types of positioning service systems according to a priority selection strategy, and determine it as the synchronization signal source.

In the specific implementation process, the receiver unit of the M positioning service system includes: a GPS signal receiving unit and a Beidou signal receiving unit; the GPS signal receiving unit is used to receive the Beidou signal receiving unit of the GPS positioning signal. For receiving the Beidou positioning signal; the signal selection unit is used to use the GPS positioning signal as the synchronization signal source by default, and switch to the Beidou positioning signal as the synchronization signal source when the received GPS positioning signal is unavailable, Until the signal quality of the GPS positioning signal returns to above the preset value, and the signal quality of the GPS positioning signal exceeds the maximum signal sensitivity of the Beidou positioning signal received by the Beidou signal receiving unit, then switch back to the The GPS positioning signal is the source of the synchronization signal. If both the GPS positioning signal and the Beidou positioning signal are unavailable, enter the holding phase until the conditions for exiting the holding phase are met.

Specifically, the preset value can be set to -148dBm. It should be noted that the unavailable GPS positioning signal may be: if the signal quality is lower than -148dBm, it is considered that the GPS positioning signal is unavailable. The GPS positioning signal is lost, specifically: the GPS signal receiving unit cannot receive the GPS positioning signal.

Specifically, after entering the maintenance phase, the signal quality of the GPS positioning signal and the Beidou positioning signal are still detected in real time. Within 12 hours of entering the maintenance phase, when the GPS positioning signal or the Beidou positioning signal is collected and available, wait for 10 minutes. minutes, if the signal quality of the collected GPS positioning signal or the signal quality of the Beidou positioning signal continues within 10 minutes and the signal quality rises steadily, then exit the hold phase; if it enters the hold phase for more than 12 hours, once the system receives GPS Positioning signal or Beidou positioning signal, exit the hold phase.

It should be noted that the steady increase in signal quality may refer to: the signal quality of the collected GPS positioning signal does not decrease, or the signal quality of the collected Beidou positioning signal does not decrease.

Through the above process, the positioning module 1 receives the positioning signal from the antenna end, and selects the appropriate positioning signal as input to the digital frequency according to the priority of the GPS positioning signal and the Beidou positioning signal, and the quality of the GPS positioning signal and the Beidou positioning signal. Sync Source for Synthesizer 2.

Further, the synchronization signal source may be specified and selected based on the user's manual operation, and it is not necessary to select according to the priority of the synchronization source.

Continue to refer to shown in Fig. 2, digital frequency synthesizer 2 comprises: frequency discrimination phase detector 201, loop filter 202, frequency adjustment word processor 203, internal phase-locked loop 204, direct digital frequency synthesizer 205, clock distribution output section 206 .

The frequency and phase detector 201 is configured to perform frequency and phase detection processing on the synchronization signal source to generate an offset of the synchronization signal source.

Specifically, the frequency of the synchronization signal source generated by the positioning module 1 is 1PPS. 205 Feedback the generated target system clock signal to perform frequency discrimination and phase discrimination processing. Specifically, the signal frequency of the target system clock signal is the same as the signal frequency of the synchronization signal source, specifically, the signal frequency of the target system clock signal is 1PPS.

The loop filter 202 is configured to perform filtering processing on the deviation to obtain a filtered deviation.

The frequency adjustment word processor 203 is configured to process and generate the first frequency adjustment word according to the filtered deviation amount.

The internal phase-locked loop 204 is used to convert the original system clock signal provided by the constant temperature crystal oscillator 3 to generate a target system clock signal, and the target system clock signal is provided to the frequency and phase detector 201, so that the The frequency and phase detector 201 performs frequency and phase detection processing on the synchronization signal source based on the target system clock signal.

More specifically, the mixed clock signal of the direct digital frequency synthesizer 205 is fed back to the feedback frequency divider 207, and the frequency division obtained by the feedback frequency divider from the mixed clock signal of the direct digital frequency synthesizer 205 is 1PPS The target system clock signal is provided to the frequency and phase detector 201 .

A direct digital frequency synthesizer 205 is configured to: generate a mixed clock signal according to the preset frequency adjustment word and the target system clock signal before the positioning signal is received; during the time period when the positioning signal exists , outputting the mixed clock signal according to the first frequency adjustment word and the target system clock signal, and outputting the mixed clock signal according to the predicted frequency adjustment word and the target system clock signal during the time period when the positioning signal is unavailable Mixed clock signals.

The clock distribution output part 206 is used for distributing the mixed clock signal output by the direct digital frequency synthesizer 205, obtaining the first target clock signal output externally, and providing it to the field programmable gate array 4 The second target clock signal.

In a specific implementation process, the frequency of the first target clock signal is 10M, and the frequency of the second target clock signal is 1PPS.

Specifically, the internal phase-locked loop 204 is specifically a DPLL (Digital Phase Locked Loop, digital phase-locked loop).

In the specific implementation process, because the jitter of the synchronous signal source of this 1PPS is reduced to a sufficiently low value, the DPLL loop needs to be locked in an extremely low bandwidth. For this locking requirement, the internal chip of the digital frequency synthesizer 2 The attribute table of the DPLL is used to constrain the characteristics of the DPLL. The attribute table constrains the electrical and frequency characteristics of the original system clock signal input to the digital frequency synthesizer 2, the bandwidth of the phase-locked loop, the phase margin, and the frequency and phase detector 201 parameters.

The digital frequency synthesizer 2 has 8 above-mentioned attribute tables of the same size, through which the user can freely define the characteristics of the DPLL. In order to enable the DPLL loop to be locked in the extremely low PLL bandwidth, the PLL bandwidth is reduced step by step by changing the PLL bandwidth based on the 8 attribute tables inside the digital frequency synthesizer 2 . The specific method is: constrain the characteristics of the input signals of the 8 attribute tables to the original system clock signal of the same reference, and the remaining characteristics of the DPLL are the same, only change the bandwidth of the phase-locked loop of the DPLL, and reduce it step by step DPLL loop bandwidth. When the synchronous clock device is initially started, due to the need to complete fast acquisition and locking of the DPLL loop, a high bandwidth value is used to constrain the loop, and the loop bandwidth is reduced when the DPLL loop is stable.

The bandwidth of the DPLL loop is gradually locked from 0.05Hz to 0.007Hz through the above method. Among them, when the locked bandwidth is greater than 0.01Hz, the bandwidth of the loop is switched only 10 minutes after locking, but if the loop loses lock due to switching for 10 minutes, it returns to the previous bandwidth value and continues to track the loop. When the loop is lower than 0.001Hz, since the bandwidth of the DPLL loop is already very low at this time, if the bandwidth is switched too quickly, it may easily cause the lock of the DPLL loop, then use the method of reducing the loop bandwidth after the loop is locked for 20 minutes In this method, the DPLL loop loses lock due to switching for up to 20 minutes and then returns to the previous bandwidth value to continue tracking the previous bandwidth loop. Through the above operations, the DPLL loop is finally locked within the 0.007Hz bandwidth.

By using the phase-locked loop bandwidth switching method, the phase-locked loop can be flexibly and stably locked within a small bandwidth, thereby more efficiently reducing the inherent jitter of the 1PPS GPS positioning signal and improving synchronization performance.

The clock is stably locked at an extremely low bandwidth within a short period of time, which improves the quality and stability of the output clock of the synchronous clock device, and improves the flexibility and reliability of the synchronous clock.

Specifically, when the synchronization signal source exists, the field programmable gate array 4 learns the drift behavior of the constant temperature crystal oscillator 3 based on the Kalman filter algorithm model to obtain learning data; when the synchronization signal source is lost During the period of time, the field programmable gate array 4 performs drift prediction on the constant temperature crystal oscillator 3 according to the learning data, and obtains a drift prediction result; the field programmable gate array 4 controls and outputs the predicted frequency according to the drift prediction result The adjustment word, the field programmable gate array 4 drives the direct digital frequency synthesizer 205 according to the predicted frequency adjustment word until the synchronization signal source is found again.

It should be noted that the predicted frequency adjustment word, the first frequency adjustment word, and the preset frequency adjustment word are only used to distinguish which component provides the frequency adjustment word, not for distinguishing the frequency adjustment word.

Specifically, in order to correct the frequency drift of the constant temperature crystal oscillator 3, in combination with the aforementioned embodiments, an implementation mode in which the field programmable gate array 4 is corrected based on the Kalman filter algorithm model is provided, and the specific description is as follows:

With reference to shown in Figure 2, field programmable gate array 4 comprises: the first low-pass filter 401, the second low-pass filter 402, the subtractor 403, the third low-pass filter 404, the first moving average unit 405, the first Two moving average unit 406 , Kalman time aging model 407 , Kalman temperature drift model 408 , filter delay compensation 409 , adder 410 .

When the synchronous signal source exists, the drift behavior of the constant temperature crystal oscillator 3 is learned based on the Kalman filter algorithm model to obtain learning data, specifically: the first low-pass filter 401 is used in the After the internal phase-locked loop 204 is stabilized, from the first frequency adjustment word read by the direct digital frequency synthesizer 205 second by second, the frequency of the constant temperature crystal oscillator 3 changes with time and temperature. total change value; the second low-pass filter 402 is used to filter out the first drift value of the frequency aging of the constant temperature crystal oscillator 3 with time from the total change value;

The subtractor 403 is used to subtract the first drift value from the total change value to obtain a second drift value of the frequency of the constant temperature crystal oscillator 3 as the temperature changes; the third low-pass filter The device 404 is used to filter the second drift value; the first sliding average unit 405 is used to perform sliding average calculation on the first drift value to obtain the first averaged drift value; the second The sliding average unit 406 is used to perform sliding average calculation on the filtered second drift value to obtain the second average post-drift value; the Kalman time aging model 407 is used to train based on the first average post-drift value , to obtain the first part of learning data; the Kalman temperature drift model 408 is used to perform training based on the second average post-drift value to obtain the second part of learning data.

Carry out drift prediction to the constant temperature crystal oscillator 3 according to the learning data, and obtain a drift prediction result, specifically: when the synchronization signal source is lost, cut off reading the first reading from the direct digital frequency synthesizer 205 A frequency adjustment word process; the filter delay compensation 409 is used to perform delay compensation to the second part of the learning data to obtain learning data after delay compensation; the adder 410 is used to add the The delay-compensated learning data is superimposed on the first part of the learning data and the initially obtained first frequency adjustment word to obtain the drift prediction result.

The temperature sensor 5 is used to control the input temperature reference to the Kalman temperature drift model 408, so that the Kalman temperature drift model 408 performs the training of the first average post-drift value with the reference temperature.

The Kalman time aging model 407 is specifically configured to: use the second target clock signal as a time reference to perform training on the second post-average drift value.

The frequency of the target system clock signal is specifically: 1PPS; the frequency of the first target clock signal is specifically: 10M; the frequency of the second target clock signal is specifically: 1PPS; the frequency of the synchronization signal source is specifically: : 1PPS.

The duration of training for the Kalman time aging model 407 based on the first average post-drift value is 2 hours; the duration of training for the Kalman temperature drift model 408 based on the second average post-drift value is 2 hours.

Due to the quality problem of the synchronous signal source, the synchronous signal source provided by the positioning module 1 cannot be directly used as the synchronous clock source of the system. Minimize the jitter amplitude of the 1PPS sync signal source.

Due to relying on the GPS signal as a synchronous clock source, there is a situation where the GPS signal is lost due to the unstable reception of the positioning signal. Therefore, for the system maintenance process after the positioning signal is lost, when the GPS signal exists, the local constant temperature crystal oscillation is performed through the Kalman filter algorithm model. The drift behavior of the constant temperature crystal oscillator 3 is learned with time and temperature. When the GPS signal is lost and synchronized, the Kalman filter algorithm model is used to predict the drift of the constant temperature crystal oscillator 3 according to the previous learning data and then control the direct digital frequency synthesizer 205. output. There are mainly two types of drift behaviors of the constant temperature crystal oscillator 3 , one is the frequency drift of the constant temperature crystal oscillator 3 with temperature, and the other is the aging drift of the constant temperature crystal oscillator 3 with time.

Among them, the drift of frequency with time is a slow change, and the change with temperature is a fast change. Therefore, the specific algorithm scheme is, when the DPLL is stabilized at a bandwidth of 0.007 Hz, the first frequency adjustment word of the direct digital frequency synthesizer 205 is read from the digital frequency synthesizer 2 second by second, and then the read first frequency adjustment word is read out from the digital frequency synthesizer 2 A frequency adjustment word is sent into by field programmable gate array 4 successively, by the first low-pass filter 401 of 600uHz in field programmable gate array 4, filter out the total variation value of frequency with time and temperature, subsequently, by the first low-pass filter 401 of 20uHz The second low-pass filter 402 filters out the first drift value of frequency aging with time from the total change value, subtracts the above two results, and obtains the second drift value of frequency change with temperature. After the above operations, the frequency drift of the constant temperature crystal oscillator 3 with time and temperature has been filtered out, and then the first drift value of the frequency aging with time is sent to the first sliding average unit 405 of 100 points for the first sliding average unit 405. A drift value pair performs 100-point moving average calculation to obtain the first averaged drift value, and the second drift value whose frequency changes with temperature enters the third low-pass filter 404 of 600uHz to filter the second drift value. The filtered second drift value enters the 100-point second moving average unit 406, and a 100-point moving average calculation is performed on the filtered second drift value to obtain a second averaged drift value. In this way, the variance of the input jitter of the Kalman time aging model 407 and the Kalman temperature drift model 408 is further reduced, thereby reducing the duration of the module training and learning drift process and reducing the instability of the system.

The first average post-drift value calculated by the sliding average of 100 points is trained in the Kalman time aging model 407 with time as a variable to obtain the first part of learning data. Among them, the time is based on 1 second for training. The second average post-drift value calculated by the sliding average of 100 points is trained in the Kalman temperature drift model 408 with temperature as a variable to obtain the second part of learning data. Among them, the temperature is trained on the basis of 0.1 degrees Celsius. The running time of the entire training of the Kalman time aging model 407 and the Kalman temperature drift model 408 is 2 hours. After the training is completed, if the positioning signal is lost, then the reading of the first frequency adjustment word of the direct digital frequency synthesizer 205 from the digital frequency synthesizer 2 is cut off. Directly linearly estimate and output the Kalman time aging model 407 and the Kalman temperature drift model 408 respectively from the loopback, delay the second part of the learning data for 3600s and superimpose the first part of the learning data and the initial first frequency adjustment word, and output It directly drives the direct digital frequency synthesizer 205 of the digital frequency synthesizer 2 to output.

Further, the 1PPS signal generated by the digital frequency synthesizer 2 is used as the time reference of the time drift of the Kalman time aging model 407 in the field programmable gate array 4, and the frequency adjustment of the direct digital frequency synthesizer 205 is completed second by second Word read and write operations, and the time base of the internal clock timing of the system, and the synchronous operation of the data frame.

The temperature sensor 5 attached to the board is used to repeatedly read the temperature of the current board and average 100 points of the temperature sensor 5, thereby eliminating the jitter of the reading value of the temperature sensor 5 from affecting the accuracy of the Kalman temperature drift model 408 influences. The temperature sensor 5 is input to the Kalman temperature drift model 408 with a unit of 0.1 degree Celsius.

In the preferred technical solution, if the Kalman time aging model 407 and the Kalman temperature drift model 408 lose positioning signals during the training process, the direct digital frequency synthesizer recorded when the synchronization signal source of 1PPSD exists The 100-point moving average of the frequency adjustment word at 205 is used as the final holding result until the positioning signal is finally found again.

If the GPS signal is lost while the 100-point moving average is not fully realized, the last calculated value of the 100-point moving average is used as the value of the frequency adjustment word of the direct digital frequency synthesizer 205 in the hold phase.

Specifically, the positioning module 1 receives the Beidou positioning signal and the GPS positioning signal from the antenna end, and selects an appropriate positioning signal as a synchronization signal source according to the priority and the signal quality of the Beidou positioning signal and the GPS positioning signal. The received synchronous signal source 1PPS is passed to the digital frequency synthesizer 2 as an input. When the DPLL does not receive the 1PPS synchronous signal source, the output is output according to the preset frequency adjustment word. At this time, the digital frequency synthesizer 2 works in free run mode. When the 1PPS synchronous signal source is valid, the DPLL first operates at the maximum DPLL bandwidth of 0.05Hz. When the DPLL loop is locked stably for 10 minutes, the DPLL switches to the 0.03Hz bandwidth, and waits for the lock and stabilizes for 10 minutes to switch to the 0.02Hz bandwidth. , the same operation up to 0.01Hz, when the bandwidth is less than 0.01Hz, operate according to the rule of reducing the bandwidth by one gear after 20 minutes of stable locking, if the above DPLL loop loses lock for a long time after switching the bandwidth, switch to the previous bandwidth. After the bandwidth is locked at 0.0067 Hz by the above rules, and after 20 minutes of loop stabilization time, the FPGA 4 starts to read the preset frequency adjustment word of the digital frequency synthesizer 2 second by second. And the preset frequency adjustment word is sent to the inside of the field programmable gate array 4 for filtering processing, and the values changing with temperature and time are filtered out respectively. And sequentially perform 100-point moving average processing on the separated two groups of data to further reduce the mean square value of signal jitter. Afterwards, the data processed by the sliding average is sent to the Kalman filter for training, and the training time is 2 hours. After the training is completed, if the positioning signal is lost, the output of the Kalman temperature drift model 408 is delayed for 3600s and then superimposed with the output of the Kalman time aging model 407 and the initial first frequency adjustment word, and then output to drive the digital frequency synthesizer 2 The predicted frequency of the tuning word. If the positioning signal is lost during the training process, the first frequency adjustment word of the 100-point moving average when the positioning signal exists is input to the digital frequency synthesizer 2 as an operating value.

Specifically, the digital frequency synthesizer 2 specifically adopts the AD9548 digital frequency synthesizer.

Specifically, the 1PPS signal generated by the digital frequency synthesizer 2 of the model AD9548 is used as the time reference of the time drift of the Kalman time aging model 407, and the reading of the frequency adjustment word of the direct digital frequency synthesizer 205 is completed second by second with write operations.

The temperature sensor 5 chip attached to the board is used as a temperature collector to repeatedly read the temperature of the current board and perform a 100-point sliding average on the temperature sensor 5, thereby eliminating the jitter of the reading value of the temperature sensor 5 and affecting the Kalman temperature. Impact of Drift Model 408 Accuracy. The temperature sensor 5 is input to the Kalman temperature drift model 408 with a unit of 0.1 degree Celsius.

If the synchronization signal source of 1PPS is lost during the training process of Kalman time aging model 407 and Kalman temperature drift model 408, the first frequency adjustment word in the direct digital frequency synthesizer 205 recorded when the synchronization signal source of 1PPS exists The result of calculating the 100-point moving average is used as the final predicted frequency adjustment word, and the predicted frequency adjustment word is kept until the positioning signal is finally retrieved. If the positioning signal is lost during the incomplete realization of the 100-point moving average, the last calculated value of the 100-point moving average is used as the predicted frequency adjustment word in the hold phase.

One or more embodiments provided by the embodiments of the present invention specifically achieve the following technical effects or advantages:

By setting the field programmable gate array, it is used to output and drive the predicted frequency adjustment word of the direct digital frequency synthesizer DDS in the digital frequency synthesizer during the time period when the positioning signal is lost, until the positioning signal is found again, the digital Before the frequency synthesizer receives the synchronization signal source, it outputs the first target clock signal according to the preset frequency adjustment word, and outputs the first target clock signal according to the first frequency adjustment word during the time period when the synchronization signal source exists signal, and output the first target clock signal according to the predicted frequency adjustment word during the time period when the synchronization signal source is unavailable. Therefore, it can be ensured that during the time period when the positioning signal is lost, the predicted frequency adjustment word is given by the field programmable gate array, so that the digital frequency synthesizer can accurately output the first frequency adjustment word according to the predicted frequency adjustment word during the time period when the positioning signal is lost. A target clock signal, rather than the GPS signal being lost, maintains the last operating value, thus improving the accuracy of the synchronized clock.

Further, since the GPS positioning signal and the Beidou positioning signal are received at the same time, one is selected as the synchronization signal source according to the signal quality and priority, thereby improving the stability and reliability of the synchronization signal source, thereby improving the reliability of the synchronization clock device .

Further, the proposed improved Kalman filter correction algorithm (Kalman time aging model + Kalman temperature drift model) is used as the maintenance algorithm model in the maintenance phase, and the input stages of the Kalman time aging model and the Kalman temperature drift model are also averaged. A 100-point moving average is performed to reduce the variance of the jitter of the input signal, thereby improving the accuracy and stability of the Kalman filter correction, thereby improving the accuracy and stability of the synchronous clock device in the hold phase.

Further, by switching the DPLL configuration table inside the integrated digital frequency synthesizer, the bandwidth of the phase-locked loop is reduced step by step, so that the internal phase-locked loop can quickly lock to an extremely low bandwidth without losing lock, so that the system can Quickly reduce the inherent jitter of 1PPS to a very small range, and improve the synchronization performance, thereby avoiding the OCXO's locking to a stable one when correcting the drift of the OCXO through the 1PPS of GPS and the method of controlling the voltage control end of the OCXO by DAC in the prior art The defect that the bandwidth takes a long time.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. a kind of Synchronization Clock, which is characterized in that including：

Locating module generates synchronizing signal for receiving the positioning signal from positioning service system based on the positioning signal Source；

Digital frequency synthesizer, for locking the source of synchronising signal；

Constant-temperature crystal oscillator OCXO, for providing original system clock signal to the digital frequency synthesizer；

Field programmable gate array, within the period that the positioning signal is lost, numerical frequency described in output driving to be comprehensive The pre- measured frequency of Direct Digital Synthesizer DDS adjusts word in clutch, until giving the positioning signal for change again；

Wherein, it before not receiving the source of synchronising signal, is provided to the DDS and the predeterminated frequency of the DDS is driven to adjust Word, within there are the period of the source of synchronising signal, of DDS described in output driving under the action of the source of synchronising signal One frequency adjusts word；

The digital frequency synthesizer is additionally operable to before not receiving the source of synchronising signal, according to the predeterminated frequency tune Section word exports first object clock signal outward, within there are the period of the source of synchronising signal, according to the first frequency It adjusts word and exports the first object clock signal outward, and within the source of synchronising signal not available period, according to The pre- measured frequency adjusts word and exports the first object clock signal outward.

2. Synchronization Clock as described in claim 1, which is characterized in that the locating module includes：

The receiver unit of M kind positioning service systems, for receiving the respective positioning letter of the M kinds positioning service system simultaneously Number, M is the integer more than 1；

Signal behavior unit is used for according to priority selection strategy from the respective positioning signal of M kinds positioning service system A positioning signal is selected, the source of synchronising signal is determined as.

3. Synchronization Clock as claimed in claim 2, which is characterized in that the receiver list of the M kinds positioning service system Member includes：GPS signal receiving unit and Big Dipper signal receiving unit；

The GPS signal receiving unit, for receiving GPS positioning signal；

The Big Dipper signal receiving unit, for receiving Big Dipper positioning signal；

The signal behavior unit, for giving tacit consent to using the GPS positioning signal as source of synchronising signal, described in receiving When GPS positioning signal is unavailable, the Big Dipper positioning signal is switched to as source of synchronising signal, until the GPS positioning signal Signal quality return back to default value or more, and the signal quality of the GPS positioning signal is received more than the Big Dipper signal When the peak signal sensitivity of the Big Dipper positioning signal received by unit, then it is described same to switch back into the GPS positioning signal Signal source is walked, if the GPS positioning signal and the Big Dipper positioning signal are unavailable, enters the holding stage until meeting Exit the condition in holding stage.

4. Synchronization Clock as claimed in claim 2, which is characterized in that the digital frequency synthesizer further includes：

Phase frequency detector generates the deviation of the source of synchronising signal for carrying out frequency and phase discrimination processing to the source of synchronising signal Amount；

Loop filter, for being filtered to the departure, departure after being filtered；

Frequency adjusts word processing device, and word is adjusted for generating the first frequency according to departure processing after the filtering；

Internal phaselocked loop, the original system clock signal for providing the OCXO carry out frequency conversion, generate goal systems clock Signal, the goal systems clock signal are supplied to the phase frequency detector so that the phase frequency detector is based on the target Clock signal of system carries out frequency and phase discrimination processing to the source of synchronising signal；

The DDS, is used for：Word and the target system are adjusted according to the predeterminated frequency before not receiving the positioning signal Clock signal of uniting generates mix clock signal；Within there are the period of the positioning signal, adjusted according to the first frequency Word and the goal systems clock signal export the mix clock signal, within the positioning signal not available period, Word is adjusted according to pre- measured frequency and the goal systems clock signal exports the mix clock signal；

Clock distribution output par, c, the mix clock signal for exporting the DDS are allocated, and obtain the institute exported outward First object clock signal is stated, and is supplied to the second target clock signal of the field programmable gate array.

5. Synchronization Clock as claimed in claim 4, which is characterized in that

In the presence of the source of synchronising signal, the field programmable gate array is based on Kalman filtering algorithm model to described The drift behavior of OCXO is learnt, and learning data is obtained；

Within the period that the source of synchronising signal is lost, the field programmable gate array is according to the learning data to described OCXO carries out drift forecasting, obtains drift forecasting result；

The field programmable gate array adjusts word according to the drift forecasting output control output pre- measured frequency, according to institute It states pre- measured frequency and adjusts DDS described in word drive, until giving the source of synchronising signal for change again.

6. Synchronization Clock as claimed in claim 5, which is characterized in that the field programmable gate array includes：First Low-pass filter, the second low-pass filter, subtracter, third low-pass filter, the first sliding average unit, the second sliding average Unit, Kalman's time Ageing Model, Kalman's temperature drift model, filter compensation of delay, adder；

In the presence of the source of synchronising signal, based on Kalman filtering algorithm model to the drift behavior of the OCXO It practises, obtains learning data, specially：

First low-pass filter, is used for：After the internal stabilized, from the DDS by the second read described the One frequency is adjusted in word, filter out the frequency of the OCXO at any time with total changing value of temperature change；

Second low-pass filter, is used for：Filtered out from total changing value the frequency of the OCXO at any time aging One drift value；

The subtracter obtains the frequency of the OCXO with temperature for total changing value to be subtracted first drift value Second drift value of variation；

The third low-pass filter, for being filtered to second drift value；

The first sliding average unit, for carrying out sliding average calculating to first drift value, after obtaining first averagely Drift value；

The second sliding average unit, for carrying out sliding average calculating to second drift value, after obtaining second averagely Drift value；

Kalman's time Ageing Model is trained for being based on the described first average rear drift value, obtains first part Learning data；

Kalman's temperature drift model is trained for being based on the described second average rear drift value, obtains second part Learning data；

Drift forecasting is carried out to the OCXO according to the learning data, obtains drift forecasting as a result, being specially：

When the source of synchronising signal is lost, cuts off from the DDS and read the process that the first frequency adjusts word；

The filter compensation of delay, for carrying out compensation of delay to the second part learning data, after obtaining compensation of delay Learning data；

The adder, for by learning data after the compensation of delay and first part's learning data and it is described just The first frequency that beginning obtains adjusts word and is overlapped, and obtains the drift forecasting result.

7. Synchronization Clock as claimed in claim 6, which is characterized in that the Synchronization Clock further includes：

Temperature sensor, for controlling input temp benchmark to Kalman's temperature drift model so that Kalman's temperature Degree drift model carries out the training of the described first average rear drift value with the fiducial temperature.

8. Synchronization Clock as claimed in claim 6, which is characterized in that

Kalman's time Ageing Model, is specifically used for：Using second target clock signal as time reference, carry out to institute State the training of the second average rear drift value.

9. Synchronization Clock as claimed in claim 3, which is characterized in that

The frequency of the goal systems clock signal is specially：1PPS；

The frequency of the first object clock signal is specially：10M；

The frequency of second target clock signal is specially：1PPS；

The frequency of the source of synchronising signal is specially：1PPS.

10. Synchronization Clock as claimed in claim 5, which is characterized in that Kalman's time Ageing Model is based on institute State first it is average after drift value be trained when it is 2 hours a length of；

Kalman's temperature drift model based on the described second drift value after average be trained when it is 2 hours a length of.