CN114337655A - Time service device circuit - Google Patents

Abstract

The application relates to the field of electronic information, in particular to a time service device circuit. The circuit comprises: the device comprises a signal acquisition module, a signal processing module and a signal optimization module; the signal acquisition module is used for acquiring a reference signal, generating a reference pulse signal according to the reference signal and transmitting the reference pulse signal to the signal processing module; the signal processing module is used for acquiring the reference pulse signal, generating an initial clock signal according to the reference pulse signal and transmitting the initial clock signal to the signal optimization module; the signal optimization module is used for acquiring the initial clock signal, and generating a target clock signal after optimizing the initial clock signal. The method and the device are used for solving the problems that the traditional timer algorithm is complex, high in cost and difficult to apply to hardware circuit development.

Description

Time service device circuit

Technical Field

The application relates to the field of electronic information, in particular to a time service device circuit.

Background

The rapid development of modern communication systems, radar systems, synchronization systems and other devices has increasingly high requirements on indexes such as frequency accuracy and frequency stability. The frequency and the time are reciprocal, the time reference is used as the only standard for communication and news release in all countries around the world, and compared with any physical quantity, the requirement on measurement accuracy is higher. Commonly used frequency standards include primary (cesium atomic frequency standard, hydrogen atomic frequency standard) and secondary (highly stable crystal oscillator, rubidium atomic frequency standard), as well as other frequency standards (including other crystal oscillators other than highly stable crystal oscillators). Meanwhile, the method is also an important measurement parameter for indexes such as phase noise, spurious emission, frequency modulation time and the like of the time service device.

The current time service device put forward in the market mostly adopts the mode of combining the intelligent discipline technology and the compensation algorithm, and realizes the high frequency accuracy and the high frequency stability which reach the first-level frequency standard. The main principle is that a closed-loop algorithm of a phase-locked loop is realized by using a processor, a Global Positioning System (GPS for short) or a Beidou navigation System is used as a reference standard, the frequency accuracy of a constant-temperature crystal oscillator is dynamically adjusted, after the phase-locked loop realized by the algorithm is locked, the time and the frequency of the phase-locked loop are synchronous with the GPS or the Beidou System, and the frequency accuracy is correspondingly traced from the GPS or the Beidou System, so that the first-level frequency standard is reached.

However, the traditional time service device uses processors such as Field Programmable Gate Array (FPGA for short) and the like, and the difficulty in developing algorithms such as an accumulator, a multiplier, a digital comparator and the like is high; the high performance of the timer mainly comes from the high performance requirements of the performance of analog devices such as a digital-to-analog converter (DAC) and an Oven Controlled Crystal Oscillator (OCXO), the cost of corresponding products is increased, and the volume of the high performance devices is larger; analog devices such as DAC and OCXO have large consistency difference, and the algorithm needs to be corrected correspondingly, so that additional development difficulty is increased. The algorithm development difficulty is high, the device performance requirement is high, the overall cost of the time service device is further increased, and the time service device is difficult to be applied to hardware circuit development with low cost and simple structure, so that the application range of the time service device is narrowed.

Disclosure of Invention

The application provides a time service device circuit, which is used for solving the problems that the traditional time service device algorithm is complex, the cost is high and the traditional time service device circuit is difficult to be applied to hardware circuit development.

In a first aspect, an embodiment of the present application provides a timer circuit, including: the device comprises a signal acquisition module, a signal processing module and a signal optimization module; the signal acquisition module is used for acquiring a reference signal, generating a reference pulse signal according to the reference signal and transmitting the reference pulse signal to the signal processing module; the signal processing module is used for acquiring the reference pulse signal, generating an initial clock signal according to the reference pulse signal and transmitting the initial clock signal to the signal optimization module; the signal optimization module is used for acquiring the initial clock signal, and generating a target clock signal after optimizing the initial clock signal.

Optionally, the signal processing module includes a frequency synthesis chip and a first oscillator; the first oscillator is used for generating a chip clock signal and transmitting the chip clock signal to the frequency synthesis chip; and the frequency synthesis chip is used for acquiring the chip clock signal and working under the frequency of the chip clock signal.

Optionally, the frequency synthesis chip is configured to acquire and synchronize the reference pulse signal, and multiply the frequency of the reference pulse signal to generate an initial clock signal.

Optionally, the frequency synthesizer chip is a digital frequency synthesizer chip.

Optionally, the first oscillator is an oven-controlled crystal oscillator.

Optionally, the signal optimization module comprises a phase-locked loop and a second oscillator; the phase-locked loop is used for acquiring the initial clock signal, performing first optimization on the initial clock signal to generate an intermediate optimization signal, and transmitting the intermediate optimization signal to the second oscillator; and the second oscillator is used for acquiring the intermediate optimization signal, and generating the target clock signal after the intermediate optimization signal is optimized for the second time.

Optionally, the second oscillator is further configured to return the target clock signal to the phase-locked loop; and the phase-locked loop is used for acquiring the returned target clock signal, correcting the intermediate optimization signal according to the target clock signal and transmitting the intermediate optimization signal to the second oscillator for secondary optimization.

Optionally, the second oscillator is a voltage controlled crystal oscillator.

Optionally, the system further comprises a clock distribution module; the signal optimization module is further configured to transmit the target clock signal to the clock distribution module; the clock distribution module is configured to obtain the target clock signal and generate N frequency-divided clock signals according to the target clock signal, where N is an integer greater than 1.

Optionally, a processor is also included; the processor is used for generating a configuration signal and transmitting the configuration signal to the signal processing module and the signal optimization module; the signal processing module is used for acquiring the configuration signal and completing the configuration of the internal working state according to the configuration signal; and the signal optimization module is used for acquiring the configuration signal and completing the configuration of the internal working state according to the configuration signal.

Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: the circuit provided by the embodiment of the application generates a required target clock signal by building the timer circuit. The circuit does not need a complex program algorithm, can realize a corresponding time service function only by building components, greatly reduces the development difficulty and the overall cost of the time service device, and does not have obvious reduction in performance indexes such as phase noise, spurious and the like after the circuit is successfully built. Meanwhile, the circuit is simple in structure, is very easy to apply to the development of a hardware circuit board, and further improves the application range of the timer.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

FIG. 1 is a schematic diagram of a circuit structure of a time service device according to an embodiment of the present disclosure;

fig. 2 is a first schematic diagram of a circuit structure of a time service device including an internal structure of a signal processing module according to an embodiment of the present disclosure;

FIG. 3 is a second schematic diagram illustrating a connection of a timer circuit including an internal structure of a signal processing module according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a circuit structure of a time service device including an internal structure of a signal optimization module according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a circuit structure of a timer including a feedback loop path according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a circuit structure of a time service device including a clock distribution module according to an embodiment of the present disclosure;

FIG. 7 is a first schematic diagram illustrating a circuit structure of a timer including a processor according to an embodiment of the present disclosure;

FIG. 8 is a second schematic diagram illustrating a circuit structure of a timer including a processor according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram illustrating signal stream transmission in a timer circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a circuit structure of a timer including a specific chip according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application provides a time service ware circuit, and this circuit is built through components and parts and forms, replaces traditional time service ware algorithm to realize the time service function. The circuit is very easy to be applied to the opening of a hardware circuit board, and can also be applied to other scenes needing a time service function. In the embodiment, the time service circuit is applied to a hardware circuit board as an example for description, but the scope of protection of the present application is not limited by the application scenario of the time service circuit.

In one embodiment, as shown in fig. 1, the timer circuit includes a signal obtaining module 101, a signal processing module 102 and a signal optimizing module 103.

The signal acquiring module 101 is configured to acquire a reference signal, generate a reference pulse signal according to the reference signal, and transmit the reference pulse signal to the signal processing module 102.

In this embodiment, the reference signal may be a satellite signal transmitted by a Global Positioning System (GPS) or a beidou navigation System. The originally obtained reference signal has a very low frequency and is not suitable for most applications. The signal acquisition module 101 performs simple processing on the acquired reference signal to obtain a reference pulse signal. The reference Pulse signal may be a 1 Second Pulse (PPS) signal that meets a first-order frequency standard.

It should be noted that the GPS system or the beidou navigation system is only an example of a way to obtain the reference signal, and the source way of the reference signal is not limited in the present application. The 1PPS signal is only one example of the reference pulse signal obtained by the signal acquisition module, and the protection scope of the present application is not limited by the specific form of the reference pulse signal.

In the embodiment, the existing reference signal which is easy to obtain is used for processing, so that the time service process is simpler and easier to realize, other clock generation devices are not needed to obtain clock signals, the realization mode of the time service circuit is further simplified, and the cost of the time service circuit is reduced.

The signal processing module 102 is configured to obtain a reference pulse signal, generate an initial clock signal according to the reference pulse signal, and transmit the initial clock signal to the signal optimization module 103.

In one embodiment, as shown in fig. 2, the signal processing module 102 includes a frequency synthesis chip 1021 and a first oscillator 1022. The first oscillator 1022 is configured to generate a chip clock signal and transmit the chip clock signal to the frequency synthesizing chip 1021. And the frequency synthesis chip 1021 is used for acquiring a chip clock signal and working at the frequency of the chip clock signal.

In this embodiment, as shown in fig. 3, the frequency synthesis chip 1021 is further configured to acquire and synchronize the reference pulse signal, multiply the frequency of the reference pulse signal to generate an initial clock signal, and transmit the initial clock signal to the signal optimization module 103. The chip clock signal generated by the first oscillator 1022 is only the operation clock of the frequency synthesis chip 1021, so that the frequency synthesis chip 1021 operates at the frequency of the chip clock signal, and is not directly linked to the reference pulse signal itself. The acquisition, synchronization and other processing of the reference pulse signal are performed by the frequency synthesis chip 1021.

In this embodiment, the frequency Synthesizer chip 1021 is a Direct Digital Synthesizer (DDS) chip. In the embodiment of the present application, a DDS chip is taken as an example, and other devices capable of implementing corresponding functions may be taken as the frequency synthesis chip 1021 for the frequency synthesis chip 1021, and the protection scope of the present application is not limited by the specific type of the frequency synthesis chip.

In this embodiment, the first Oscillator 1022 is an Oven Controlled Crystal Oscillator (OCXO for short). In a traditional timer, an OCXO is used for generating a clock signal, a signal output by the OCXO is the finally output clock signal, and the accuracy of the output frequency of an oscillator is reduced due to the influence of the ambient temperature, the power supply, the aging rate and the like. In this embodiment, the OCXO is only a working clock of the DDS chip and is used to generate a chip clock signal of the DDS chip, and at the same time, the OCXO is not a final stage of the entire circuit and is not a key point that affects performance, so that a requirement on the OCXO is greatly reduced, cost is further reduced, and interference immunity of the entire circuit is improved.

The signal optimization module 103 is configured to obtain an initial clock signal, perform optimization processing on the initial clock signal, and generate a target clock signal.

In this embodiment, the initial clock signal phase noise and the performance such as spurious output by the DDS chip are very poor, and it is difficult to meet the technical index of the high performance requirement item. Therefore, the added signal optimization module 103 optimizes the initial clock signal.

In one embodiment, as shown in fig. 4, the signal optimization module 103 includes a phase locked loop 1031 and a second oscillator 1032. The phase locked loop 1031 is configured to obtain an initial clock signal, obtain a feedback signal transmitted by the second oscillator 1032, generate an intermediate signal according to the initial clock signal and the feedback signal, and transmit the intermediate signal to the second oscillator 1032. The second oscillator 1032 is configured to obtain the intermediate signal, optimize the intermediate signal, generate an output signal, transmit the output signal to the phase-locked loop 1031 as a feedback signal, and use the output signal with a performance index that tends to be stable as a target clock signal. After the output signal generated by the second oscillator 1032 is the target clock signal with stable performance index, the second oscillator 1032 transmits the target clock signal as a feedback signal to the phase-locked loop 1031, so that the performance index of the target clock signal is kept stable.

In this way, the second oscillator 1032 returns the output signal to the phase-locked loop 1031 as a feedback signal, i.e., a loop-back feedback process is formed. The phase-locked loop 1031 generates an intermediate signal by processing the initial clock signal and the feedback signal, the second oscillator 1032 optimizes the intermediate signal to generate an output signal, and the output signal is used as the feedback signal again to form a cyclic feedback process, so that the finally output target clock signal can well improve the performance index of the target clock signal while the frequency precision of the target clock signal is kept at the initial clock signal, and the target clock signal is closer to the performance index of the second oscillator 1032.

In this embodiment, the second Oscillator 1032 is a Voltage-Controlled crystal Oscillator (VCO for short).

In this embodiment, the phase-locked loop includes a loop filter, and a very narrow-band loop filter is selected to filter out the phase noise at the near end. While the phase noise other than the near-end phase noise is mainly filtered by the phase noise performance of the second oscillator. For example, if the loop filter bandwidth is chosen to be 200Hz, the phase noise at the far end, e.g., 10kHz, is mainly realized by the second oscillator. Because the second oscillator is used for optimizing indexes such as phase noise, stray and the like, the requirement on the frequency standard is correspondingly reduced in the oscillator model selection, and the VCO with the model selection lower than that of the OCXO is only required.

Compared with the traditional time service device, the time service device has the advantages that the signal optimization mode is carried out through a complex algorithm, the target clock signal meeting the frequency accuracy is obtained through the superposition optimization of hardware components twice, and meanwhile, the cost of the time service device circuit is further reduced by selecting simple and cheap components. Meanwhile, the size of the component with lower performance is relatively smaller, and the whole size of the timer circuit is further reduced.

In one embodiment, as shown in fig. 6, the timer circuit further includes a clock distribution module 104. After the signal optimization module 103 transmits the target clock signal to the clock distribution module 104, the clock distribution module 104 generates N frequency-divided clock signals according to the target clock signal, where N is an integer greater than 1. N may be determined according to the requirements of the hardware circuit board, such as the clock level and the number of clock circuits. The clock distribution module 104 may be a clock distribution chip. For example, when multiple sine wave signals are required and the harmonic power is low, the clock distribution module 104 may cascade multiple stages of power dividers, and add a low-pass filter of a corresponding frequency to each clock output.

By dividing the output target clock signal into a plurality of frequency division clock signals, a plurality of requirements can be met simultaneously, unnecessary interference cannot be generated among the plurality of clock signals, and the service efficiency of the time service device circuit is improved.

In this embodiment, the clock distribution module 104 only divides the target clock signal into a plurality of divided clock signals, and the frequency precision and performance index of the target clock signal are not changed after the target clock signal is divided into the divided clock signals. Therefore, when the clock distribution module 104 is included in the timer circuit, the output signal may be returned to the phase-locked loop 1031 as a feedback signal by the second oscillator 1032, or the output signal may be returned to the phase-locked loop 1031 as a feedback signal by the clock distribution module 104, so as to form a loop feedback process, thereby further optimizing the signal.

In one embodiment, as shown in FIG. 7, the timer circuit further comprises a processor 105.

The processor 105 generates configuration signals and transmits the configuration signals to the signal processing module 102 and the signal optimization module 103. After the signal processing module 102 obtains the configuration signal, the configuration of the internal working state is completed according to the configuration signal. After the signal optimization module 103 obtains the configuration signal, the configuration of the internal working state is completed according to the configuration signal. The configuration of the internal working state is completed, including starting or stopping working according to the configuration signal, and changing the internal working state according to the configuration signal.

In this embodiment, as shown in fig. 8, the signal processing module 102 includes a frequency synthesis chip 1021 and a first oscillator 1022, where the frequency synthesis chip 1021 is configured to obtain a configuration signal and complete configuration of an internal working state according to the configuration signal. The signal optimization module 103 includes a phase-locked loop 1031 and a second oscillator 1032, where the phase-locked loop 1031 obtains the configuration signal and completes configuration of the internal operating state according to the configuration signal. When the timer circuit includes the clock distribution module 104, the clock distribution module 104 may also obtain the configuration signal, and complete the configuration of the internal working state according to the configuration signal. Here, the clock distribution module 104 is selected to feed back the output signal as a feedback signal to the phase-locked loop 1031 to form a loop feedback, so as to optimize the target clock signal.

The processor in the traditional time service device needs to complete complex processes such as a clock synchronization algorithm, an oscillator calibration algorithm and the like, and has relatively high requirements on the resource allocation of the processor. The processor in the embodiment only configures the DDS chip, the phase-locked loop, and the second oscillator, no additional algorithm is needed, processor resources are saved, the requirement on processor resource configuration is low, processor equipment with a lower price can be selected, and the cost is further reduced. The volume of the processor with lower performance is smaller, and the whole volume of the timer circuit is further reduced.

In this embodiment, the transmission direction of the signal flow in the timer circuit is as shown in fig. 9. After the signal acquisition module 101 acquires the reference signal, it generates a reference pulse signal and transmits the reference pulse signal to the frequency synthesis chip 1021. The frequency synthesis chip 1021 acquires and synchronizes the reference pulse signal, multiplies the frequency of the reference pulse signal to generate an initial clock signal, and transmits the initial clock signal to the phase-locked loop 1031. The phase-locked loop 1031 acquires the initial clock signal and the feedback signal transmitted by the clock distribution module 104, processes the signals, generates an intermediate signal, and transmits the intermediate signal to the second oscillator 1032. The second oscillator 1032 optimizes the acquired intermediate signal, generates an output signal, and transmits the output signal to the clock distribution module 104.

The clock distribution module 104 transmits the output signal as a feedback signal to the phase-locked loop 1031 to form a loop feedback, so as to continuously and repeatedly optimize the output signal, and when the performance index of the output signal is stable, the output signal can be used as a target clock signal. When the performance index of the output signal is stable, the clock distribution module 104 still returns the target clock signal as a feedback signal to the phase-locked loop 1031, so that the performance index of the target clock signal continues to be stable. Clock distribution module 104 also generates a plurality of divided clock signals for multiple uses based on the target clock signal.

The processor 105 generates configuration signals and transmits the configuration signals to the frequency synthesizing chip 1021, the phase locked loop 1031 and the clock distribution module 104, respectively. The frequency synthesis chip 1021, the phase-locked loop 1031 and the clock distribution module 104 complete the configuration of the internal working state according to the obtained configuration signals, respectively. The first oscillator 1022 generates a chip clock signal and transmits the chip clock signal to the frequency synthesizing chip 1021. The frequency synthesizing chip 1021 acquires a chip clock signal and operates at the chip clock signal frequency.

In this embodiment, as shown in fig. 10, the frequency synthesis chip 1021 is a DDS chip, the first oscillator 1022 is an OCXO, and the second oscillator 1032 is a VCO. The frequency division clock signal output by the time service device circuit and the clock signal output by the traditional time service device of the same type in the industry are respectively tested, and the performance parameters obtained by the test are compared as the following table 1:

TABLE 1 time service circuit and traditional time service performance parameter comparison table

As can be seen from the comparison of the parameters in table 1, the performance of the time service circuit provided in this embodiment in terms of frequency accuracy, output spurs, phase noise, etc. is substantially equal to that of the conventional time service device, especially the noise performance beyond 10 KHz. The time service device circuit meets the precision requirements of electronic products such as communication products and radar products, and has greater advantages in the aspects of cost control, size and the like.

The application provides a time service ware circuit builds whole circuit through hardware components and parts to realize the time service function. The circuit does not need a complex program algorithm, can realize a corresponding time service function only by building components, greatly reduces the development difficulty and the overall cost of the time service device, and does not have obvious reduction in performance indexes such as phase noise, spurious and the like after the circuit is successfully built. Meanwhile, the circuit is simple in structure, is very easy to apply to the development of a hardware circuit board, and further improves the application range of the timer. All components and parts that this time service ware circuit used need not all to operate complicated algorithm, consequently have lower to the performance requirement of components and parts, and low performance components and parts not only low price, and the hardware volume is less relatively moreover, when reduce cost, makes time service ware circuit's whole volume littleer, more does benefit to and is applied to various environment, enlarges time service ware circuit's application range.

Meanwhile, the existing reference signal which is easy to obtain is utilized, so that the time service process is simpler and easier to realize, other clock generating devices are not needed to obtain clock signals, the realization mode of the time service circuit is further simplified, and the cost of the time service circuit is reduced. The output target clock signal is divided into a plurality of frequency division clock signals, so that a plurality of requirements can be met simultaneously, unnecessary interference cannot be generated among the plurality of clock signals, and the service efficiency of the time service device circuit is improved.

Based on the same concept, the embodiment of the present application further provides a clock signal processing method, which is applied to the timer circuit described in the above embodiments, and the method mainly includes:

the signal acquisition module acquires a reference signal, converts the reference signal into a reference pulse signal and transmits the reference pulse signal to the signal processing module;

the signal processing module acquires a reference pulse signal, generates an initial clock signal according to the reference pulse signal and transmits the initial clock signal to the signal optimization module;

the signal optimization module acquires an initial clock signal, and generates a target clock signal after optimizing the initial clock signal.

The generating of the initial clock signal according to the reference pulse signal specifically includes: a frequency synthesizer chip in the signal processing module acquires and synchronizes the reference pulse signal, and the reference pulse signal is multiplied by frequency to generate an initial clock signal.

After the initial clock signal is optimized, a target clock signal is generated, which specifically includes:

a phase-locked loop in the signal optimization module acquires an initial clock signal and outputs an intermediate signal to a second oscillator;

a second oscillator in the signal optimization module acquires the intermediate signal, generates an output signal after optimizing the intermediate signal, and returns the output signal as a feedback signal to be transmitted to the phase-locked loop;

the phase-locked loop acquires a feedback signal, updates the intermediate signal according to the initial clock signal and the feedback signal, and transmits the updated intermediate signal to the second oscillator;

and a feedback loop between the phase-locked loop and the second oscillator continuously repeats the optimization process through the feedback signal, and when the performance index of the output signal tends to be stable, the output signal can be used as a target clock signal.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A time service circuit, comprising: the device comprises a signal acquisition module, a signal processing module and a signal optimization module;

the signal acquisition module is used for acquiring a reference signal, generating a reference pulse signal according to the reference signal and transmitting the reference pulse signal to the signal processing module;

the signal processing module is used for acquiring the reference pulse signal, generating an initial clock signal according to the reference pulse signal and transmitting the initial clock signal to the signal optimization module;

the signal optimization module is used for acquiring the initial clock signal, and generating a target clock signal after optimizing the initial clock signal.

2. The timer circuit of claim 1, wherein the signal processing module comprises a frequency synthesis chip and a first oscillator;

the first oscillator is used for generating a chip clock signal and transmitting the chip clock signal to the frequency synthesis chip;

and the frequency synthesis chip is used for acquiring the chip clock signal and working under the frequency of the chip clock signal.

3. The time service circuit of claim 2, wherein the frequency synthesizer chip is configured to obtain and synchronize the reference pulse signal, and multiply the frequency of the reference pulse signal to generate an initial clock signal.

4. The timer circuit of claim 3, wherein the frequency synthesizer chip is a digital frequency synthesizer chip.

5. The time service circuit of claim 4, wherein the first oscillator is an oven controlled crystal oscillator.

6. The timer circuit according to any one of claims 1 to 5, wherein the signal optimization module comprises a phase-locked loop and a second oscillator;

the phase-locked loop is used for acquiring the initial clock signal, acquiring a feedback signal transmitted by the second oscillator, generating an intermediate signal according to the initial clock signal and the feedback signal, and transmitting the intermediate signal to the second oscillator;

the second oscillator is configured to obtain the intermediate signal, optimize the intermediate signal, generate an output signal, transmit the output signal to the phase-locked loop as the feedback signal, and use the output signal with a performance index that tends to be stable as the target clock signal.

7. The timer circuit of claim 6, wherein the second oscillator is configured to transmit the target clock signal as the feedback signal to the phase locked loop to stabilize the performance level of the target clock signal.

8. The time service circuit of claim 7, wherein the second oscillator is a voltage controlled crystal oscillator.

9. The timer circuit of claim 1, further comprising a clock distribution module;

the signal optimization module is further configured to transmit the target clock signal to the clock distribution module;

the clock distribution module is configured to obtain the target clock signal and generate N frequency-divided clock signals according to the target clock signal, where N is an integer greater than 1.

10. The timer circuit of claim 1, further comprising a processor;

the processor is used for generating a configuration signal and transmitting the configuration signal to the signal processing module and the signal optimization module;

the signal processing module is used for acquiring the configuration signal and completing the configuration of the internal working state according to the configuration signal;

and the signal optimization module is used for acquiring the configuration signal and completing the configuration of the internal working state according to the configuration signal.

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