JP5556412B2 - Timing synchronization apparatus and timing synchronization method - Google Patents

Description

  The present invention relates to an apparatus for generating a system timing synchronized with a reference timing.

In order to match the output timing of radio signals between radio base stations, timing frames are synchronized between the radio base stations. For synchronization of timing frames, for example, a 1 PPS (Pulse Per Second) signal that is acquired from a GPS (Global positioning system) receiver and notifies an interval of 1 second is used. In addition to 1PPS signal from GPS receiver, IEEE
A signal for notifying the 1 second interval of E1588 Precision Time Protocol (PTP) may be used. Hereinafter, signals transmitted from GPS satellites are collectively referred to as GPS signals.

For example, in LTE (Long Term Evolution), there are the following problems when performing radio frame synchronization and radio frequency synchronization between radio base station apparatuses using GPS signals.

  For example, the radio base station apparatus may not be able to capture the GPS signal from the GPS satellite due to the orbit of the GPS satellite, the influence of the weather, or the failure of the GPS antenna. When a GPS signal cannot be captured from a GPS satellite, the wireless base station device performs processing such as outputting a wireless signal using a clock generated using a high-precision oscillator provided in the device. The operation of a radio base station apparatus using a clock generated using a high-accuracy oscillator provided in the own apparatus is hereinafter referred to as “self-running”. An example of the high-precision oscillator is a crystal oscillator.

  When the radio base station device is self-propelled, the accuracy of the clock generated by the radio base station device depends on the accuracy of the high-precision oscillator, so the timing of the generated clock deviates from the timing of the GPS signal as time passes. It will be. Then, the output timing of the radio signal may be shifted between the radio base station devices. Therefore, when the GPS signal from the GPS satellite cannot be captured (GPS satellite uncaptured state) continues for a while and then starts to capture the GPS signal again, the radio base station device shifts with time. It is necessary to correct the timing phase between the GPS signal that has been lost and the generated clock of the device itself. Hereinafter, a state in which the radio base station apparatus cannot capture a GPS signal from a GPS satellite is referred to as a “GPS satellite uncaptured state” or simply a “GPS uncaptured state”. The state in which the radio base station apparatus is capturing a GPS signal from a GPS satellite is referred to as a “GPS satellite capturing state” or simply “GPS capturing state”.

One of the methods for correcting the timing phase is, for example, a method in which the frame position is gradually adjusted by changing the clock frequency of the generated clock of the radio base station apparatus so that the phase matches the GPS signal. In this case, the phase of the GPS signal and the generated clock are compared using DPLL (Digital Phase Locked Loop) or APLL (Analog PLL), and the clock frequency of the generated clock is changed.

JP 2001-52280 A JP 2000-4152 A

However, when DPLL or APLL is used, phase matching is performed by matching the phases closer to each other without determining whether the generated clock is advanced or delayed with respect to the GPS signal. The phase shift increases with the lapse of the time that the GPS satellite unacquired state continues, and if the phase difference is large, the variation of the clock frequency in the PLL also increases, so the clock frequency varies beyond the radio frequency accuracy range. There is a possibility. The radio frequency accuracy is defined as a reference frequency ± 0.05 ppm (Parts Per Million) in, for example, 3GPP (3rd Generation Partnership Project) in which LTE is defined.

  An object of one embodiment of the present invention is to provide a timing synchronization device that accurately synchronizes an internal timing signal of the device itself with a reference timing signal.

One aspect of the present invention is a timing synchronization device. This timing synchronizer
An acquisition unit for acquiring a reference timing signal indicating a predetermined time interval and reference time information indicating a reference time corresponding to the reference timing signal;
A clock generator for generating an internal clock signal having a clock frequency;
A time information generating unit that generates an internal timing signal indicating the predetermined time interval and internal time information indicating a time corresponding to the internal timing signal based on the internal clock signal;
The reference timing signal and the internal timing signal, and the reference time information and the internal time information are compared to detect the advance or delay of the internal timing signal with respect to the reference timing signal, and the reference timing signal Detecting a phase advance amount or delay amount of the internal timing signal with respect to
An adjustment unit that adjusts the clock frequency according to the amount of advance or delay of the phase detected by the detection unit;
Is provided.

  According to the disclosed timing synchronization apparatus, the internal timing signal of the own apparatus can be synchronized with the reference timing signal.

It is a figure which shows the structural example of a radio base station apparatus. It is a figure which shows the structural example of a timing synchronizer. It is a figure which shows the example of the timing synchronizer which operate | moves in a closed loop. It is a figure which shows the example of the timing synchronizer which operate | moves in an open loop. It is a figure which shows the example of a comparison with a 1 second reference | standard counter signal and a PPS signal in case the 1 second reference | standard counter signal is ahead of the PPS signal. It is a figure which shows the example of a comparison with a 1 second reference | standard counter signal and a PPS signal in case the PPS signal is ahead of the 1 second reference | standard counter signal. It is a figure which shows the example of the processing flow of a time phase comparison part. It is an example of the fluctuation | variation of a clock frequency in a phase adjustment process. It is a figure which shows the example of the processing flow of a control value setting part. It is a figure which shows the example of the processing flow of a control value setting part. It is a figure which shows the example of the flow of the DDSTW value average process which a control value setting part performs. It is a figure which shows the example of the flow of the phase change confirmation statistical process which a control value setting part performs. It is a figure which shows the structural example of the timing synchronization apparatus of 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configuration of the following embodiment is an exemplification, and the present invention is not limited to the configuration of the embodiment.

<First Embodiment>
The timing synchronization apparatus is provided in the radio base station apparatus, for example, and synchronizes an internal timing signal generated in the radio base station apparatus with a reference timing signal indicating a predetermined time interval based on a reference clock signal from an external apparatus. Let The reference timing signal is, for example, a 1PPS signal received from a GPS receiver. In addition to signals from GPS satellites, there are also signals used in PTP. In the first embodiment, the timing synchronization device synchronizes the clock signal, time, etc. generated in the own device with the clock signal, time, etc. from the GPS satellite.

<< Device configuration >>
FIG. 1 is a diagram illustrating a configuration example of a radio base station apparatus. The radio base station apparatus 500 includes a radio equipment control station (REC: Radio Equipment Controller) 510 and a radio equipment (RE: Radio Equipment) 520.

The radio equipment control station 510 includes an inter-station transmission path interface unit (HWY: HighWaY) 511, a layer 2 switch unit (L2SW: Layer 2 SWitch) 512, and a baseband unit (BB: Base Band) 513.
, A control unit (CNT: CoNTroller) 514, a GPS receiver 515, and a clock timing unit (CLK Timing: CLocK Timing) 516.

  The inter-station transmission path interface unit 511 is an interface of a wired transmission path that is connected to another radio base station apparatus. The layer 2 switch unit 512 relays data exchange between the inter-station transmission path interface unit 511, the baseband unit 513, and the control unit 514.

  The baseband unit 513 performs error correction encoding, framing, data modulation, and the like of transmission data. The baseband unit 513 performs baseband signal processing such as error correction decoding of received signals and data demultiplexing.

  The control unit 514 transmits and receives control signals to and from other base station devices and higher-level devices, and performs wireless line management, wireless line setting, release, and the like.

  The GPS receiver 515 receives a clock signal and time information transmitted from a GPS satellite. Moreover, based on the clock signal transmitted from the GPS satellite, for example, a 1PPS signal indicating a time interval of 1 second is generated.

  The clock timing unit 516 uses the clock signal, 1PPS signal, time information, and the like received from the GPS receiver 515 to generate clock signal and radio frame transmission / reception timing used in the apparatus.

  The radio 520 includes a transmission / reception unit (TRX: Transmitter and Receiver) 521, a transmission power amplifier unit (T-PA) 522, a transmission / reception switching unit (DUPlexer) 523, and a low noise amplification unit (LNA: Low). Noise Amplifier) 524.

The processing unit included in each of the radio equipment control station 510 and the radio equipment 520 includes, for example, an electronic circuit for realizing each function, a card unit including an integrated circuit for a specific application such as an ASIC (Application Specific Integrated Circuit), etc. It is.

  FIG. 2 is a diagram illustrating a configuration example of the timing synchronization device. The timing synchronization device 1 includes a DPD (Digital Phase Detector) unit 11, a DDS (Direct Digital Synthesis) unit 12, a clock counter unit 13, a time phase comparison unit 14, a control value setting unit 15, and a GPS receiving unit 16. The timing synchronization device 1 corresponds to, for example, the GPS receiver 515 and the clock timing unit 516 in the radio control station 110 in the radio base station device 100.

  The timing synchronization device 1 performs a process for synchronizing a clock signal generated in the own device with a clock signal acquired from a GPS satellite. Furthermore, the timing synchronization device 1 performs processing for synchronizing the time held in the device itself with the time acquired from the GPS satellite.

  The timing synchronization device 1 operates by switching between two modes of a closed loop and an open loop.

  FIG. 3 is a diagram illustrating an example of a timing synchronization device that operates in a closed loop. In the closed loop, the DDS unit 12 accepts only input from the DPD unit 11. Since the clock signal generated from the DDS unit 12 is input to the DPD unit 11, the DPD unit 11 and the DDS unit 12 form a closed loop. In the GPS satellite acquisition state, the timing synchronization device 1 mainly operates in a closed loop.

  FIG. 4 is a diagram illustrating an example of a timing synchronization device that operates in an open loop. In the open loop, the DDS unit 12 disconnects the input from the DPD unit 11 and receives the input from the control value setting unit 15. The timing synchronizer 1 mainly operates in an open loop when performing processing for synchronizing with a GPS satellite unacquired state, a clock signal from a GPS satellite, or a 1PPS signal.

  Details of switching between the open loop and the closed loop of the timing synchronization apparatus 1 will be described later.

(GPS receiver)
The GPS receiver 16 is, for example, the GPS receiver 515 in FIG. 1, and receives a clock signal from a GPS satellite, time information indicating time, and the like. The GPS receiver 16 counts clock signals received from GPS satellites and generates, for example, a PPS signal indicating a time interval of 1 second.

  The clock signal acquired from the GPS satellite is hereinafter referred to as a GPS clock signal or simply a GPS clock. The time information acquired from the GPS satellite is hereinafter referred to as GPS time information. The GPS clock signal is output to the DPD unit 11. The PPS signal and the GPS time information are output to the time phase comparison unit 14.

  When the GPS receiver 16 has not received any clock signal or GPS time information from the GPS satellite for a predetermined time, the GPS receiver 16 determines the GPS uncaptured state and informs the time phase comparator 14 that the GPS is uncaptured. Output.

  The GPS receiving unit 16 corresponds to, for example, an acquiring unit. The PPS signal corresponds to, for example, a reference timing signal. The GPS time information corresponds to, for example, reference time information.

(DPD part)
The DPD unit 11 receives as input a GPS clock signal and a feedback clock signal obtained by feeding back the clock signal generated by the DDS unit 12.

  The DPD unit 11 is a circuit that divides the GPS clock signal and the feedback clock signal into 8 kHz, respectively, and compares the phase of two inputs divided into 8 kHz. The GPS clock signal has a frequency of 10 MHz, for example. Further, the clock signal generated by the DDS unit 12 is assumed to have a frequency in the range of 3.84 MHz to radio frequency accuracy (± 0.05 ppm) in the first embodiment. The DPD unit 11 has a Phase Build Out function, adjusts the output of the frequency division of 8 kHz, and sets the maximum value of the phase difference between the GPS clock signal divided to 8 kHz and the feedback clock signal to the output clock of the DPD unit 11 Is reduced to the range of one cycle.

  The DPD unit 11 outputs the phase difference between the GPS clock signal divided into 8 kHz and the generated clock signal obtained as a result of the phase comparison to the DDS unit 12.

(DDS department)
The DDS unit 12 includes a high-precision oscillator that generates an internal reference clock. Examples of the high-precision oscillator include crystal oscillators such as OCXO (Oven Controlled Xtal Oscillator) and TCXO (Temperature-Compensated crystal Oscillator).

  The DDS unit 12 generates a clock signal used in the apparatus from an internal reference clock using a tuning word (DDSTW) that is a control value. For example, the DDS unit 12 generates a clock signal based on the following expression.

F _out = (F _refclk × DDSTW) / 2 ^ 32 (Formula 1)
F _out : Output frequency (clock frequency)
F _refclk : Internal reference clock frequency DDSTW: Tuning word In the first embodiment, it is assumed that the reference clock frequency is 3.84 MHz. In the first embodiment, it is assumed that the high-accuracy oscillator is OCXO, and the internal reference clock frequency F _refclk is 20 MHz. In Equation 1, 2 to the 32nd power is derived from the fact that the DDS unit 12 includes a 32-bit phase accumulator.

  The DSTTW value for outputting the reference clock frequency (3.84 MHz) is (3.84 MHz × 2 ^ 32) ÷ 20 MHz = 82433720.832 from Equation 1. This DDSTW value is set as a reference DDSTW value.

The internal reference clock frequency F _refclk is created by OCXO and depends on the accuracy of OCXO. For example, when the accuracy of OCXO is ± 100 ppb (Parts Per Billion), the internal reference clock frequency F _refclk has a range of _19.99999999 to 20.000001 MHz.
In the case of F _refclk = 19.999999,
DDSTW = (3.84 × 2 ^ 32) /19.999999=824633762.064
It becomes.
If F _refclk = 20.000001,
DDSTW = (3.84 × 2 ^ 32) /20.000001=824633679.600
It becomes. In this way, the accuracy of the output frequency (clock frequency) is maintained at the reference clock frequency ± 0.05 ppm by changing the DDSTW value according to the change of the internal reference clock frequency.

  When the timing synchronization device 1 is operating in a closed loop, the DDS unit 12 receives the phase difference between the GPS clock signal and the feedback clock signal from the DPD unit 11 as an input. The DDS unit 12 acquires the amount of change in the DDSTW value corresponding to the input phase difference and adds it to the current value of DDSTW. The DDS unit 12 generates a clock signal using the obtained DDSTW value. The DDS unit 12 holds the correspondence between the phase difference between the GPS clock signal and the feedback clock signal and the amount of change in the DDSTW value, for example, as a table or a function in advance.

  When the timing synchronization device 1 is operating in an open loop, the DDS unit 12 receives the DDSTW value from the control value setting unit 15 as an input. The DDS unit 12 generates a clock signal according to Equation 1 using the input DDSTW value.

  When the GPS is not captured, the timing synchronizer 1 does not receive a GPS clock and the timing synchronizer 1 runs on its own. In the case of self-running, the timing synchronization device 1 operates in an open loop, and the DDS unit 12 generates a clock signal according to Equation 1 using a DDSTW value set in advance for use during self-running. The DSTTW value for self-running is hereinafter referred to as a holdover value.

  The DDS unit 12 outputs the generated clock signal to the clock counter unit 13. The DDS unit 12 feeds back the generated clock signal to the DPD unit 11 as a feedback clock signal.

  Hereinafter, the signal generated by the DDS unit 12 is referred to as a generated clock signal or simply a generated clock. The DDS unit 12 corresponds to a clock generation unit. The generated clock signal corresponds to an internal clock signal.

(Clock counter)
The clock counter unit 13 receives the generated clock signal from the DDS unit 12 as an input. The clock counter unit 13 counts the generated clock signal input from the DDS unit 12 and measures, for example, 1 second according to the count number of the generated clock signal. The clock counter unit 13 generates a 1-second reference counter signal indicating a time interval of 1 second. The clock counter unit 13 manages the time used in the apparatus and updates the time by adding 1 second to the current time every time 1 second is measured. The clock counter unit 13 also generates in-device time information including the time at that time together with the 1 second reference counter signal. The clock counter unit 13 outputs the in-device time information to the time phase comparison unit 14 together with the 1 second reference counter signal.

  The clock counter unit 13 corresponds to a time information generation unit. The 1-second reference counter signal corresponds to an internal timing signal. The in-device time information corresponds to the internal time information.

(Time phase comparator)
The time phase comparator 14 receives the PPS signal and GPS time information from the GPS receiver 16 as inputs. Further, the time phase comparison unit 14 receives the 1-second reference counter signal and the in-device time information from the clock counter unit 13 as inputs.

  For example, if the PPS signal and the 1-second reference counter signal are rectangular waves, the time phase comparison unit 14 obtains the phase difference by comparing the rising edges of the PPS signal and the 1-second reference counter signal. At this time, the time phase comparison unit 14 compares the GPS time information with the in-device time information to detect whether the 1-second reference counter signal is advanced or delayed with respect to the PPS signal.

  In addition, the time phase comparison unit 14 includes a detection clock (not shown) for detecting a phase difference, and is detected between the rising edge of the PPS signal and the rising edge of the 1-second reference counter signal. The phase difference value is obtained by measuring the number of clock cycles. That is, the phase difference value is expressed by the number of cycles of the detection clock.

  When the 1-second reference counter signal is ahead of the PPS signal, the time phase comparison unit 14 outputs the obtained phase difference value to the control value setting unit 15 as a negative number.

  When the PPS signal is ahead of the 1-second reference counter signal, the time phase comparison unit 14 outputs the obtained phase difference value to the control value setting unit 15 as a positive number.

  Further, when the GPS receiver 16 notifies the GPS non-capture state, the time phase comparator 14 notifies the control value setting unit 15 of the GPS non-capture state.

  5A and 5B are diagrams for explaining a comparison process between the PPS signal, the GPS time information, the 1-second reference counter signal, and the in-device time information. 5A and 5B, the waveform of the detection clock is shown at the top. The detection clock is a clock for measuring the time difference between the rising timings of the PPS signal and the 1-second reference counter signal. The detection clock is provided in the time phase comparator 14 (not shown). It is assumed that the detection clock has a frequency of 100 MHz in FIGS. 5A and 5B.

  In the second row of FIGS. 5A and 5B, the time included in the GPS time information is displayed. The waveform of the PPS signal is shown in the third row of FIGS. 5A and 5B. Since the time phase comparison unit 14 receives GPS time information including the time stamped at the rising edge of the next PPS signal from the GPS reception unit 16 prior to the PPS signal, the time phase comparison unit 14 Set to PPS signal.

  FIG. 5A is a diagram illustrating an example of comparison between the 1-second reference counter signal and the PPS signal when the 1-second reference counter signal is ahead of the PPS signal.

  In the example shown in FIG. 5A, the time phase comparator 14 detects that the 1-second reference counter signal reaches time n earlier than the PPS signal. That is, the time phase comparison unit 14 detects that the 1-second reference counter signal is advanced with respect to the PPS signal. The time phase comparison unit 14 counts the time from the rise of the 1 second reference counter signal to the rise of the PPS signal, for example, the number of cycles of the detection clock of 100 MHz, and detects that the phase difference is 5 cycles. .

  Therefore, in FIG. 5A, the 1-second reference counter signal is advanced by 5 cycles from the PPS signal, and therefore the time phase comparison unit 14 notifies the control value setting unit 15 of the phase difference value “−5”.

  FIG. 5B is a diagram illustrating an example of comparison between the 1-second reference counter signal and the PPS signal when the PPS signal is ahead of the 1-second reference counter signal.

  In the example shown in FIG. 5B, the time phase comparison unit 14 detects that the PPS signal reaches time n earlier than the 1-second reference counter signal. That is, the time phase comparison unit 14 detects that the 1-second reference counter signal is delayed with respect to the PPS signal. The time phase comparator 14 detects that the time from the rise of the PPS signal to the rise of the 1-second reference counter signal is 6 cycles of the detection clock.

  Therefore, in the example shown in FIG. 5B, the 1-second reference counter signal is delayed by 6 cycles with respect to the PPS signal, so the time phase comparison unit 14 notifies the control value setting unit 15 of the phase difference value “+6”. To do.

  When the phase difference between the PPS signal and the 1-second reference counter signal is less than one cycle of the detection clock, the time phase comparison unit 14 considers that the phases of the PPS signal and the 1-second reference counter signal match. . Hereinafter, a state in which the phase of the PPS signal and the 1-second reference counter signal is considered to be in phase, that is, a state in which the phase difference between the PPS signal and the 1-second reference counter signal is less than one cycle of the detection clock is “ This is referred to as “phase synchronization state”. Further, a state where the phase of the PPS signal and the 1-second reference counter signal is not considered to be in phase, that is, a state where the phase difference between the PPS signal and the 1-second reference counter signal is one cycle or more of the detection clock is Hereinafter, it is referred to as a “phase asynchronous state”.

  Moreover, the time phase comparison part 14 performs the process which determines whether a GPS clock signal and a production | generation clock signal are synchronizing. For example, the time phase comparison unit 14 holds the phase difference value in a memory (not shown), and the phase difference value between the PPS signal and the 1 second reference counter signal is the previous phase difference value (that is, 1 second ago). Whether or not the GPS clock signal and the generated clock signal are synchronized is determined based on whether or not they match.

  The fact that the phase difference value between the PPS signal and the 1-second reference counter signal matches the previous value indicates that the 1-second time interval indicated by the 1-second reference counter signal has not changed, that is, the clock frequency has changed. Indicates not. The fact that the clock frequency has not changed indicates that there is no change in the DDSTW value, that is, the GPS clock signal and the generated clock signal are synchronized. Since the phase difference value is indicated by the number of cycles of the detection clock, it is considered that there is no change in phase difference of less than one cycle. For example, in the example shown in FIGS. 5A and 5B, since one cycle is 10 ns (frequency of the detection clock is 100 MHz), it is considered that there is no change in phase difference of less than ± 10 ns.

  Therefore, the time phase comparator 14 determines that the GPS clock signal and the generated clock signal are synchronized when the phase difference value between the PPS signal and the one-second reference counter signal matches the previous time. . The time phase comparator 14 determines that the GPS clock signal and the generated clock signal are not synchronized when the phase difference value between the PPS signal and the one-second reference counter signal does not match the previous time. .

  Hereinafter, a state in which it is determined that the GPS clock signal and the generated clock signal are synchronized is referred to as a frequency synchronization state. A state where it is determined that the GPS clock signal and the generated clock signal are not synchronized is referred to as a frequency asynchronous state. The time phase comparison unit 14 corresponds to a detection unit.

(Processing flow of time phase comparator)
FIG. 6 is a diagram illustrating an example of a processing flow of the time phase comparison unit 14. The time phase comparator 14 sets the initial value of the frequency synchronization flag to 0 (OP1). The frequency synchronization flag is set to 1 when the frequency synchronization state is set, and is set to 0 when the GPS is not captured.

  The time phase comparator 14 receives the PPS signal from the GPS receiver 16 at a cycle of 1 second. Further, the time phase comparison unit 14 receives GPS time information including the time indicated by the PPS signal prior to the PPS signal. When the GPS receiver 16 cannot receive a signal from a GPS satellite, the time phase comparator 14 receives a notification of the GPS uncaptured state from the GPS receiver 16 (OP2).

  The time phase comparison unit 14 determines whether or not it is in the GPS capturing state (OP3). When the PPS signal and the GPS time information are received from the GPS receiving unit 16, the time phase comparing unit 14 determines that it is in the GPS capturing state. When the notification of the GPS uncaptured state is received from the GPS receiver 16, the time phase comparator 14 determines that the GPS is uncaptured.

  When the GPS is not captured (OP3: No), the time phase comparison unit 14 sets the frequency synchronization flag to 0 (OP4). The time phase comparison unit 14 notifies the control value setting unit 15 of the GPS uncaptured state (OP5). Thereafter, the process returns to OP2.

  In the case of the GPS capture state (OP3: Yes), the time phase comparison unit 14 determines whether or not the frequency synchronization flag is 0 (OP6).

  When the frequency synchronization flag is 0 (OP6: Yes), the time phase comparison unit 14 determines whether or not the frequency synchronization state is set (OP7). The time phase comparison unit 14 compares the PPS signal received from the GPS reception unit 16 with GPS time information, the 1-second reference counter signal received from the time counter unit 13, and the in-device time information. The time phase comparator 14 determines whether or not the GPS clock and the generated clock are synchronized depending on whether or not the obtained phase difference value matches the previous phase difference value, that is, the frequency synchronization state or the frequency asynchronous state. Determine.

In the case of the frequency asynchronous state (OP7: No), the time phase comparison unit 14 notifies the control value setting unit 15 of the GPS capture state and the frequency asynchronous state (OP8). Thereafter, the process returns to OP2.
In the case of the frequency synchronization state (OP7: Yes), the time phase comparison unit 14 sets the frequency synchronization flag to 1 (OP9).

  When the frequency synchronization flag is 1 (OP6: No), or when the frequency synchronization state is determined and the frequency synchronization flag is set to 1 (OP9), the time phase comparison unit 14 determines whether there is a phase difference. Is determined (OP10). When the phase difference value is ± 0, the time phase comparison unit 14 determines that there is no phase difference. When the phase difference value is not ± 0, the time phase comparison unit 14 determines that there is a phase difference.

  When there is no phase difference, that is, when the phase difference value is “± 0” (OP10: Yes), the time phase comparison unit 14 sets the GPS capture state, the frequency synchronization state, and the phase synchronization state to the control value setting unit. 15 (OP11). Thereafter, the process returns to OP2.

  When there is a phase difference (OP10: No), the time phase comparison unit 14 notifies the control value setting unit 15 of the GPS capture state, the frequency synchronization state, the phase asynchronous state, and the phase difference value (OP12). Thereafter, the process returns to OP2.

  When the frequency synchronization flag is 1 in OP6, the process of determining whether there is a phase difference (OP10) moves without determining whether the frequency synchronization state is set (OP7). This means that if the frequency synchronization flag is 1, the time phase comparison unit 14 is in the frequency synchronization state even if it is in the frequency asynchronous state until the GPS unacquired state once the frequency synchronization state is reached. It is shown to be considered.

(Control value setting part)
The control value setting unit 15 determines the switching between the open loop and the closed loop according to the notification content from the time phase comparison unit 14. Details of switching between the open loop and the closed loop will be described later.

  The control value setting unit 15 performs phase adjustment processing for reducing the phase difference between the PPS signal and the 1-second reference counter signal. The phase adjustment process is executed in an open loop. The details of the phase adjustment processing are as follows.

  The control value setting unit 15 sets a DDSTW value such that the phase difference between the PPS signal and the 1-second reference counter signal is reduced according to the phase difference value from the time phase comparison unit 14. In the phase adjustment process, the phase adjustment DDSTW value that is the DDSTW value in the frequency synchronization state immediately before the phase adjustment process is started is used.

  At this time, the control value setting unit 15 changes the DDSTW value stepwise so that the fluctuation range of the clock frequency does not increase.

  In order to suppress the clock frequency within the range of the reference clock frequency ± 0.05 ppm, the maximum value of the fluctuation range from the clock frequency immediately before the phase adjustment processing is set to, for example, ± 20 ppb (= 0.02 ppm) through the phase adjustment processing. Is done.

From Equation 1, when F _refclk = 20 MHz, if DSTTW value increases or decreases by 1, F _out becomes 3
. Increase / decrease by 1.2127ppb with respect to 84MHz. Output frequency F _out is + 20ppb
In order to fluctuate, it is sufficient that the DDSTW value fluctuates by 20 ÷ 1.2127≈ + 16.49. The control value setting unit 15 sets the maximum value of the change amount from the phase adjustment DDSTW value to ± 16 in the phase adjustment process. However, if the DDSTW value changes by ± 16, the fluctuation range of the clock frequency increases, and the range of the radio frequency accuracy may be exceeded. Therefore, the control value setting unit 15 sets the first DSTTW value change amount to ± 8. And When the DDSTW value changes by ± 8, the clock frequency changes by about 10 ppb.

  When the state in which the clock frequency has changed by +1 ppb continues for 1 second, the phase of the 1-second reference counter signal advances by 1 ns. Further, when the state in which the clock frequency is changed by −1 ppb continues for 1 second, the phase of the 1-second reference counter signal is delayed by 1 ns. That is, when the DDSTW value changes by +8, the clock frequency changes to about +10 pbb. When this state continues for 1 second, the phase of the 1-second reference counter signal advances by 10 ns. When the DDSTW value changes by +16, the clock frequency changes by about +20 ppb. If this state continues for 1 second, the phase of the 1-second reference counter signal advances by 20 ns.

  The control value setting unit 15 outputs the DDSTW value obtained according to the phase difference value input from the time phase comparison unit 14 to the DDS unit 12.

  In addition, when the phase of the PPS signal and the one-second reference signal match, that is, when it is considered that the phase difference has disappeared, the control value setting unit 15 returns the DDSTW value to the phase adjustment DDSTW value. However, even when the control value setting unit 15 returns the DDSTW value to the phase adjustment DDSTW value, the control value setting unit 15 returns the DSTTW value stepwise as in the first phase adjustment process. For example, when the phase difference is 2 cycles, that is, 20 ns, the control value setting unit 15 sets the DDSTW value to a value obtained by changing +8 from the phase adjustment DDSTW value, and continues this state for 2 seconds. The DDSTW value is returned to the phase adjustment DDSTW value. By doing so, the DDSTW value is not changed by ± 16 at a time, and the clock frequency is prevented from fluctuating beyond the radio frequency accuracy.

For example, in the case of the example shown in FIG. 5A, the control value setting unit 15 is notified of the phase difference value “−5” from the time phase comparison unit 14. In FIG. 5A, since the frequency of the detection clock is 100 MHz and one cycle is 10 ns, the control value setting unit 15 has a phase difference value of “−5”. Detecting that 50ns is also advanced.

  In the first phase adjustment process, the control value setting unit 15 sets the DDSTW value to a value obtained by changing the phase adjustment DDSTW value by -8 in order to change the clock frequency by about −10 ppb. As a result, the clock frequency fluctuates by about −10 ppb, and after 1 second, the phase of the 1-second reference counter signal is delayed by about 10 ns. Further, the phase difference between the 1-second reference counter signal and the PPS signal is reduced by about 10 ns to 40 ns (phase difference value “−4”).

  In the next phase adjustment process, the phase difference is 40 ns, which is larger than 20 ns. The control value setting unit 15 sets the DDSTW value to a value obtained by changing the phase adjustment DDSTW value by −16. Since the DDSTW value at the previous phase adjustment processing is the phase adjustment DDSTW value −8, the amount of change from the previous DDSTW value is suppressed to −8. By setting the DDSTW value to a value obtained by changing the phase adjustment DDSTW by −16, the clock frequency fluctuates by about −20 ppb, and after 1 second, the phase of the 1-second reference counter signal is delayed by 20 ns. Further, the phase difference between the 1-second reference counter signal and the PPS signal is reduced by about 20 ns to 20 ns (phase difference value “−2”).

  Further, in the next phase adjustment process, since the phase difference is 20 ns, the control value setting unit 15 sets the DDSTW value to a value obtained by changing the phase adjustment DDSTW value by -8. Here, if the DDSTW value is set to a value obtained by changing −16 from the phase adjustment DDSTW value, the phase difference becomes 0 after 1 second, and it is necessary to return the DDSTW value to the phase adjustment DDSTW value. However, when the DDSTW value is changed from the value obtained by changing the phase adjustment DDSTW by -16 to the phase adjustment DDSTW value, the DDSTW value is changed by -16 at a time. Therefore, when the phase difference is 20 ns (the phase difference value is ± 2), the DDSTW value is set to a value obtained by changing the phase adjustment DDSTW value by −8.

  By setting the DDSTW value to a value obtained by changing the phase adjustment DDSTW by −8, the clock frequency further varies by about −10 ppb, and after 1 second, the phase of the 1-second reference counter signal is delayed by 10 ns. Further, the phase difference between the 1-second reference counter signal and the PPS signal is reduced by about 10 ns to about 10 ns (phase difference value “−1”).

  Further, in the next phase adjustment processing, since the phase difference is 10 ns, the control value setting unit 15 sets the DDSTW value to a value obtained by changing the phase adjustment DDSTW value by −8. As a result, the clock frequency further varies by about −10 ppb, and after 1 second, the phase of the 1-second reference counter signal is delayed by 10 ns. Further, the phase difference between the 1-second reference counter signal and the PPS signal is reduced by about 10 ns, and it is considered that there is no phase difference (phase difference value “± 0”).

  Since the phase difference has disappeared, the control value setting unit 15 returns the DDSTW value to the phase adjustment DDSTW value. Since the DDSTW value in the previous phase adjustment process is a value obtained by changing the phase adjustment DDSTW value by −8, the amount of change from the previous DDSTW value is suppressed to +8.

  That is, in the example shown in FIG. 5A, the control value setting unit 15 changes the DDSTW value every other second, the phase adjustment DDSTW value−8 (phase change 10 ns), the phase adjustment DDSTW value−16 (phase change 20 ns), The phase adjustment DDSTW value is changed to -8 (phase change 10 ns), the phase adjustment DDSTW value -8 (phase change 10 ns), and the phase adjustment DDSTW value. As a result, the phase of the 1-second reference counter signal is delayed by 50 ns after 4 seconds, and the phases of the 1-second reference counter signal and the PPS signal match.

  For example, in the case of the example shown in FIG. 5B, the control value setting unit 15 is notified of the phase difference value “+6” from the time phase comparison unit 14. The control value setting unit 15 detects from the phase difference value “+6” that the 1-second reference counter signal is delayed by 60 ns from the PPS signal.

  In the first phase adjustment process, the control value setting unit 15 sets the DDSTW value to a value obtained by changing the DSTTW value by +8 from the phase adjustment DDSTW value in order to advance the phase of the 1-second reference counter signal regardless of the phase difference. To do. As a result, the clock frequency fluctuates by about +10 ppb, and after 1 second, the phase of the 1-second reference counter signal advances by 10 ns. The phase difference between the 1-second reference counter signal and the PPS signal is 50 ns (phase difference value “+5”).

  In the next phase adjustment process, since the phase difference is 50 ns and larger than 20 ns, the control value setting unit 15 sets the DDSTW value to a value obtained by changing +16 from the phase adjustment DDSTW value. As a result, the clock frequency fluctuates by about +20 ppb, and the phase of the 1-second reference counter signal advances by 20 ns after 1 second. The phase difference between the 1-second reference counter signal and the PPS signal is 30 ns (phase difference value “+3”).

  Further, in the next phase adjustment process, the phase difference is 30 ns, which is larger than 20 ns. Therefore, the control value setting unit 15 sets the DDSTW value to a value obtained by changing +16 from the phase adjustment DDSTW value. In this case, the DDSTW value does not change from the previous time. As a result, the clock frequency further varies by about +20 ppb, and the phase of the 1-second reference counter signal advances by 20 ns after 1 second. The phase difference between the 1-second reference counter signal and the PPS signal is about 10 ns (phase difference value “+1”).

  In the next phase adjustment process, since the phase difference is 10 ns, the control value setting unit 15 sets DDSTW to a value obtained by changing +8 from the phase adjustment DDSTW value. As a result, the clock frequency further changes by about +10 ppb, and the phase of the 1-second reference counter signal advances by 10 ns after 1 second. The phase difference between the 1-second reference counter signal and the PPS signal is approximately 0 ns (phase difference value “0”).

  That is, in the case of the example shown in FIG. 5B, the control value setting unit 15 changes DDSTW every other second from the phase adjustment DDSTW value by +8 (advance phase 10 ns), +16 (advance phase 20 ns), +16 (advance phase 20 ns) , +8 (the phase advances by 10 ns). As a result, the phase of the 1-second reference counter signal is advanced by 60 ns, and the phases of the 1-second reference counter signal and the PPS signal are matched.

  FIG. 7 is a diagram illustrating a variation in the clock frequency due to the phase adjustment process when the DDSTW value in the frequency synchronization state immediately before the phase adjustment process is started in FIG. 5B is the reference DDSTW value corresponding to the reference clock frequency. is there. In this case, the phase adjustment DDSTW value becomes the reference DDSTW value. α is 16 and β is 20 ppb. The control value setting unit 15 corresponds to an adjustment unit.

  In addition, the control value setting unit 15 takes statistics on how to decrease the phase difference value, and performs a phase change confirmation statistical process for adjusting the phase adjustment DDSTW value.

  In the example shown in FIGS. 5A and 5B, the phase difference is small, such as −50 ns or +60 ns, and the phase adjustment process only takes about 4 seconds. For example, when 16 bits are used for notification of the phase difference value, it is possible to measure from −32767 to +32767 cycles, and it is possible to detect a phase difference of −327.67 to +327.67 μs. When the maximum fluctuation range of DDSTW is ± 20 ppb, the phase change of the 1-second reference counter signal per second is ± 20 ns. Therefore, when the phase difference is 327.67 μs, it takes 327670 ÷ 20≈16,384 seconds≈4.5 hours.

During the phase adjustment process, an open loop is entered, and the GPS clock input is cut off.
Further, since the clock frequency is changed by the phase adjustment process, the GPS clock is not synchronized. When the phase difference is −327.67 μs, the execution time of the phase adjustment process becomes as long as about 4.5 hours, and the state that is not synchronized with the GPS clock continues during that time. In this case, the frequency of an internal oscillator such as OCXO used by the DDS unit 12 may change due to temperature characteristics and aging. When the frequency of the internal oscillator changes due to temperature characteristics or changes over time, the phase difference between the PPS signal and the 1-second reference counter signal is obtained when the phase adjustment process is executed using a constant value of the phase difference DDSTW. Deviation occurs in the amount of change. The control value setting unit 15 executes a phase change confirmation statistical process in order to correct the shift in the change amount of the phase difference.

  For example, when the DDSTW value is operated with the phase difference DDSTW value ± 20 ppb, the phases of the PPS signal and the 1-second reference counter signal should approach 20 ns per second. That is, the amount of change in the phase difference between the PPS signal every second and the one-second reference counter signal should be 20 ns. However, when the frequency of the internal reference clock fluctuates due to temperature characteristics, aging, etc., the amount of change in the phase difference between the PPS signal per second and the 1-second reference counter signal becomes smaller or larger than 20 ns. It fluctuates.

  Therefore, the control value setting unit 15 obtains an average value of the amount of change in the phase difference value between the PPS signal every second and the 1-second reference counter signal, and adjusts the phase difference adjustment DDSTW value based on the average value. Corrects deviations in the amount of change in value. Details of the phase change confirmation statistical processing will be described later.

  Further, the control value setting unit 15 reads the DDSTW value adjusted in the closed loop, and executes a DDSTW value averaging process for obtaining an average value of DDSTW. The obtained average value of DDSTW is set as a phase adjustment DDSTW value and a holdover DDSTW value. The holdover value is a value of DDSTW used in the case of self-running in an open loop. Details of the DDSTW value averaging process will be described later.

(Processing flow of control value setting unit)
8A and 8B are diagrams illustrating an example of a processing flow of the control value setting unit 15. The control value setting unit 15 first sets the initial value of the variable n to 0 (OP21). The variable 0 is a variable for measuring the number of phase adjustment processes.

  The control value setting unit 15 receives a notification from the time phase comparison unit 14 (OP22). Based on this notification content, the content of the process is determined.

  The control value setting unit 15 determines whether or not it is in a GPS capturing state (OP23). The determination is made based on whether the notification content from the time phase comparison unit 14 includes the notification of the GPS capture state or the notification of the GPS non-capture state.

  When the GPS is not captured (OP23: No), the control value setting unit 15 sets the open loop, and issues an instruction to the DDS unit 12 so as to self-run (OP24). When receiving an instruction for self-running in an open loop, the DDS unit 12 generates a clock using a holdover DDSTW value that is a DSTTW value for self-running. Thereafter, the process returns to OP22.

  When it is in the GPS capturing state (OP23: Yes), the control value setting unit 15 determines whether or not it is in the frequency synchronization state (OP25). The control value setting unit 15 determines whether it is in the frequency synchronization state by including either the frequency synchronization state notification or the frequency asynchronous state notification in the notification content from the time phase comparison unit 14.

When it is in the frequency asynchronous state (OP25: No), that is, when the notification content from the time phase comparison unit 14 includes the notification of the frequency asynchronous state, the control value setting unit 15 sets the closed loop. An instruction is issued to the DDS unit 12 (OP26). Upon receiving the closed loop instruction, the DDS unit 12 starts accepting input from the DPD unit 11 and performs processing for synchronizing the GPS clock and the generated clock.

  The control value setting unit 15 reads the DDSTW value set in the DDS unit 12 and holds it as the phase adjustment DDSTW value (OP27). Thereafter, the process returns to OP22.

  When it is in the frequency synchronization state (OP25: Yes), that is, when the notification content from the time phase comparison unit 14 includes the notification of the frequency synchronization state, the control value setting unit 15 sets the phase synchronization state. Is determined (OP28). The control value setting unit 15 determines whether or not it is in the phase synchronization state by including either the phase synchronization state notification or the phase asynchronous state notification in the notification content from the time phase comparison unit 14.

  When the phase synchronization state is set (OP28: Yes), that is, when the notification content from the time phase comparison unit 14 includes the notification of the phase synchronization state, the DDS unit 12 is set so as to be set to the closed loop. (OP30). The control value setting unit 15 performs a DDSTW value averaging process (OP31), and holds the obtained average value as a phase adjustment DDSTW value (OP32). Thereafter, the process returns to OP22. Details of the DDSTW value averaging process will be described later.

  If the phase is asynchronous (OP28: No), the control value setting unit 15 instructs the DDS unit 12 to set the open loop (OP41). The control value setting unit 15 executes a phase change confirmation statistical process (OP42). Details of the phase change confirmation statistical processing will be described later.

  The control value setting unit 15 determines whether or not the phase difference value included in the notification content from the time phase comparison unit 14 is a positive number (OP43).

  When the phase difference value is a positive number (OP43: Yes), the control value setting unit 15 determines whether the variable n is 0 and whether the phase difference is 2 cycles or less ( OP44). When the variable n is 0, it indicates that it is the first phase adjustment process.

  When the variable n is 0 or the phase difference matches at least one of two cycles or less (OP44: Yes), the control value setting unit 15 sets the DDSTW value to +8 (16 from the phase adjustment DDSTW value) Decimal notation: + 0x8) Set to a changed value (OP45). Since the phase difference value is positive, it indicates that the 1-second reference counter signal is delayed from the PPS signal, and the DSTTW value becomes a value obtained by changing +8 from the phase adjustment DDSTW value. The 1 second reference counter signal can be advanced by about 10 ns. The control value setting unit 15 notifies the DDS unit 12 of the set DDSTW value. Thereafter, the process proceeds to OP50.

  If the variable n is 0 and the phase difference does not match either of two cycles or less (OP44: No), it is not the first phase adjustment processing, and the phase difference may be larger than two cycles. Indicated. The control value setting unit 15 sets the DDSTW value to a value obtained by changing the phase adjustment DDSTW value by +16 (hexadecimal notation: + 0x10) (OP46). Since the phase difference value is positive, it is indicated that the 1-second reference counter signal is delayed from the PPS signal, and the DSTTW value is changed by +16 from the phase adjustment DDSTW value. The 1 second reference counter signal can be advanced by about 20 ns. The control value setting unit 15 notifies the DDS unit 12 of the set DDSTW value. Thereafter, the process proceeds to OP50.

  When the phase difference value is a negative number (OP43: No), the control value setting unit 15 determines whether the variable n is 0 and whether the phase difference is 2 cycles or less ( OP47). When the variable n is 0, it indicates that it is the first phase adjustment process.

  When the variable n is 0 or the phase difference matches at least one of two cycles or less (OP47: Yes), the control value setting unit 15 sets the DDSTW value from the phase adjustment DDSTW value to -8 ( Hexadecimal notation: -0x8) Set to changed value (OP48). Since the phase difference value is negative, it is indicated that the 1-second reference counter signal is ahead of the 1PPS signal, and the DTSTW value becomes a value obtained by changing the phase adjustment DDSTW value by -8. The 1 second reference counter signal can be delayed by about 10 ns. The control value setting unit 15 notifies the DDS unit 12 of the set DDSTW value. Thereafter, the process proceeds to OP50.

  When the variable n is 0 and the phase difference does not match any of two cycles or less (OP47: No), the control value setting unit 15 sets the DDSTW value to -16 (hexadecimal number) from the phase adjustment DDSTW value. Notation: −0 × 10) Set to a changed value (OP49). Since the phase difference value is negative, it is indicated that the 1-second reference counter signal is ahead of the PPS signal, and the DDSTW value is set to a value obtained by changing −16 from the phase adjustment DDSTW value. The 1 second reference counter signal after 2 seconds can be delayed by about 20 ns. The control value setting unit 15 notifies the DDS unit 12 of the set DDSTW value. Thereafter, the process proceeds to OP50.

  When the DDS unit 12 is notified of the phase adjustment DDSTW value, the control value setting unit 15 determines whether or not the predicted value of the phase difference between the PPS signal after one second and the one-second reference counter signal is less than one cycle (OP50). ). For example, when the frequency of the detection clock is 100 MHz and one cycle is 10 ns, and the DDSTW value is set to a value obtained by changing the phase adjustment DDSTW by −8, the control value setting unit 15 sets the phase difference value to − A value changed by 1 is set as a predicted value of the phase difference.

  When the predicted value of the phase difference is less than one cycle (OP50: Yes), the control value setting unit 15 considers that the phase difference disappears after 1 second, and determines the end of the phase adjustment process. The control value setting unit 15 resets the variable n to 0 (OP51). Thereafter, the process returns to OP22.

  When the predicted value of the phase difference is 1 cycle or more (OP50: No), it is indicated that the phase adjustment is required even after 1 second. The control value setting unit 15 updates the variable n by adding 1 (OP52). Thereafter, the process returns to OP22.

  FIG. 9 is a diagram illustrating an example of the flow of the DDSTW value averaging process executed by the control value setting unit 15. The DDSTW value averaging process shown in FIG. 9 is a process executed in OP30 of FIG. 8A.

  The control value setting unit 15 reads the DDSTW value adjusted in the closed loop and accumulates it in a memory (not shown) (OP61).

  The control value setting unit 15 obtains an average value of the accumulated DSDTW values for one hour (OP62). The obtained average value is set to the holdover DDSTW value and is used when the self-running setting is set. Thereafter, the process proceeds to OP31 in FIG. 8A.

  By using the average value of the DDSTW value adjusted in the closed loop as the holdover DDSTW value, it is possible to suppress the influence of the frequency fluctuation of the high-precision oscillator provided in the DDS unit 12, and to obtain a more accurate DDSTW value. Can be used.

  FIG. 10 is a diagram illustrating an example of the flow of the phase change confirmation statistical process executed by the control value setting unit 15. The phase change confirmation statistical process shown in FIG. 10 is a process executed in OP42 of FIG. 8B.

  The control value setting unit 15 accumulates the phase difference used for the n-th phase adjustment process in a memory (not shown) (OP71).

  The control value setting unit 15 obtains an average value for the maximum 50 past changes in the amount of change between the (n−1) th phase difference and the nth phase difference (OP72).

  The control value setting unit 15 determines whether or not the obtained average value is between 1.5 and 2.5 cycles (OP73). In the first embodiment, the maximum fluctuation width of the clock frequency is set to ± 20 ppb, and the maximum fluctuation width of the DDSTW value for changing the clock frequency to the maximum fluctuation width ± 20 ppb is ± 16. Further, the phase change of the 1 second reference counter signal after 1 second after changing the DDSTW value by ± 16 is about ± 20 ns. Since the phase of the 1-second reference counter signal changes by about ± 20 ns in 1 second, the phase difference between the PPS signal and the 1-second reference counter signal also changes by about ± 20 ns in 1 second. 20 ns corresponds to two cycles of a 100 MHz detection clock. The control value setting unit 15 adjusts the frequency variation due to the temperature change and secular change of the high-precision oscillator provided in the DDS unit 12 by moving the average of the change amount of the past phase difference from ± 2 cycles from 2 cycles. Detect.

  When the obtained average value is between 1.5 cycles and 2.5 cycles (OP73: No), the control value setting unit 15 varies the frequency of the high-precision oscillator provided in the DDS unit 12. Consider it not. Thereafter, the process proceeds to OP43.

  When the obtained average value is less than 1.5 cycles or 2.5 cycles or more (OP73: No), the control value setting unit 15 uses the frequency (internal reference) of the high-precision oscillator provided in the DDS unit 12. The clock frequency is considered to have changed. The control value setting unit 15 updates the phase adjustment DDSTW value to a value obtained by changing the phase adjustment DDSTW value by +4 or −4 in order to correct a shift in the amount of change in phase difference due to a change in the internal reference clock frequency (OP74). The reason why the phase adjustment DDSTW value is changed by ± 4 is to change the change amount of the phase difference by about ± 5 ns. Thereafter, the process proceeds to OP43.

<< Effects of First Embodiment >>
8A and 8B, when the GPS is not captured (FIG. 8A, OP23: No), the timing synchronization device 1 is self-running in an open loop setting (FIG. 8A, OP24).

  After the GPS non-capture state continues, when the GPS capture state is entered again (FIG. 8A, OP23: Yes), the timing synchronization device 1 operates in a closed loop setting in order to synchronize the GPS clock signal and the generated clock signal ( FIG. 8A, OP26).

When the frequency synchronization state is reached by operating in the closed loop (FIG. 8A, OP25: Yes), the timing synchronizer 1 sets the open loop in order to match the phase of the PPS signal and the 1 second reference counter signal, Phase adjustment processing is performed (FIG. 8B, OP41-OP52).

  When the phase adjustment process results in the phase synchronization state (FIG. 8A, OP28: Yes), the timing synchronization device 1 sets the closed loop again (FIG. 8A, OP29).

The timing synchronization device 1 compares the GPS time information with the in-device time information during the phase adjustment process, and determines whether the 1-second reference counter signal is advanced or delayed with respect to the PPS signal. . Thereby, the PPS signal and the 1-second reference counter signal can be more accurately synchronized. Since the time phase is also synchronized by the synchronization of the PPS signal and the 1 second reference timing signal, for example, the radio frame phase of LTE and the SFN (System Frame Number) in units of frames can be matched between base stations. .

  In addition, the timing synchronization device 1 sets a DDSTW value such that the fluctuation range of the clock frequency is suppressed to ± 20 ppb. As a result, when the GPS non-capture state continues and the GPS capture state is entered again, it is possible to prevent fluctuations such that the radio frequency accuracy of the clock frequency cannot be maintained. In addition, it is possible to prevent a radio frame phase jump from affecting the radio system to which the timing synchronization device 1 belongs.

<Second Embodiment>
The timing synchronization device of the second embodiment is a duplicate of the timing synchronization device described in the first embodiment. In the second embodiment, descriptions overlapping with those in the first embodiment are omitted.

  In the case of duplication, there are frequency fluctuations in the self-running in the GPS uncaptured state and the processing synchronized with the clock and time from the GPS satellite when returning from the GPS uncaptured state to the GPS captured state. For this reason, the clocks generated by the active system and the standby system are different, and the phases may not match. In addition, the radio frequency accuracy may become out of specification due to the influence of the phase difference and the frequency difference due to switching between the active system and the standby system.

  In the timing synchronization device 1B of the second embodiment, the standby clock is not synchronized with the GPS clock but is synchronized with the generated clock of the active system, thereby suppressing the phase difference between the clocks of the active system and the standby system. be able to.

  FIG. 11 is a diagram illustrating a configuration example of the timing synchronization device of the second embodiment. The timing synchronization device 1B includes an N-system clock unit 10, an E-system clock unit 20, and a GPS receiver unit 16. In the example shown in FIG. 11, the input and output of the N-system clock unit 10 are indicated by solid lines. The input and output of the E-system clock unit 20 are indicated by broken lines.

  N system clock unit 10 and E system clock unit 20 are both DPD units 111, 211, DDS units 112, 212, clock counter units 113, 213, time phase comparison units 114, 214, control value setting units 115, 215, and It includes switching units 117A, 117B, 217A, 217B.

  The switching units 117A, 117B, 217A, and 217B receive the switching instruction between the active system (ACT) and the standby system (STBY) and switch the input. In the example shown in FIG. 11, the processing unit that gives an instruction to switch between the active system and the standby system is not shown. Also, switching between the active system and the standby system is performed, for example, in a predetermined cycle or by detecting the occurrence of a failure in the radio base station apparatus including the timing synchronization apparatus 1B.

  When the switching unit 117A of the N system clock unit 10 operates as an operation system, the switching unit 117A adopts the input of the GPS clock signal and outputs the GPS clock signal to the DPD unit 111. When the switching unit 117A operates as a standby system, the switching unit 117A adopts the input of the generated clock of the E-system clock generation unit 20 and outputs it to the DPD unit 111.

When the switching unit 117B of the N system clock unit 10 operates as an active system, the DDS unit 1
Twelve generated clock signals are input and output to the clock counter unit 113 as a master clock. When the switching unit 117B operates as a standby system, the switching unit 117B adopts the input of the generated clock of the DDS unit 212 of the E system clock unit 20 and outputs it to the clock counter unit 113.

  When operating as an active system, the switching unit 217A of the E system clock unit 20 adopts the input of the GPS clock signal and outputs the GPS clock signal to the DPD unit 211. When the switching unit 217A operates as a standby system, the switching unit 217A adopts the input of the generated clock of the N-system clock generation unit 10 and outputs it to the DPD unit 211.

  When operating as an active system, the switching unit 217B of the E system clock unit 20 adopts the input of the generated clock of the DDS unit 212 and outputs it as a master clock to the clock counter unit 213. When operating as a standby system, the switching unit 217B adopts the input of the generated clock of the DDS unit 112 of the N system clock unit 10 and outputs it to the clock counter unit 213.

  The 1-second reference counter signal and the device time information generated by the clock counter unit 113 are output to the clock counter unit 213 of the E system clock unit 20 in addition to the time phase comparison unit 114. Similarly, the 1-second reference counter signal and the in-device time information generated by the clock counter unit 213 are output to the clock counter unit 113 of the N system clock unit 10 in addition to the time phase comparison unit 214.

  When operating as a standby system, the clock counter units 113 and 213 output the 1-second reference counter signal and the in-device time information input from the operational clock unit to the time phase comparison units 114 and 214. In this case, the time phase comparison units 114 and 214 compare the 1-second reference counter signal of the operating clock unit with the in-device time information, the PPS signal, and the GPS time information to obtain a phase difference value.

  When operating as a standby system, the timing synchronization device 1B ignores the GPS clock and employs the generated clock of the operational clock unit as an input. In addition, when operating as a standby system even during phase adjustment processing, the generated clock of the operating system clock unit is used as an input, and the 1-second reference counter signal input from the operating system clock unit is synchronized with the PPS signal. Thus, it follows the generated clock of the operational system. As a result, the standby system operates in accordance with the active system regardless of the state of the clock section of the active system, and can be switched while minimizing frequency fluctuations whenever it is switched.

1, 1B Timing synchronization device 11, 111, 211 DPD unit 12, 112, 212 DDS unit 13, 113, 213 Clock counter unit 14, 114, 214 Time phase comparison unit 15, 115, 215 Control value setting unit 16 GPS receiving unit 17, 117A, 117B, 217A, 217B Switching unit 10 N system clock unit 20 E system clock unit

Claims (3)

An acquisition unit for acquiring a reference timing signal indicating a predetermined time interval and reference time information indicating a reference time corresponding to the reference timing signal;
A clock generator for generating an internal clock signal having a clock frequency;
A time information generating unit that generates an internal timing signal indicating the predetermined time interval and internal time information indicating an internal time corresponding to the internal timing signal based on the internal clock signal;
The reference timing signal and the internal timing signal, and the reference time information and the internal time information are compared to detect the advance or delay of the internal timing signal with respect to the reference timing signal, and the reference timing signal Detecting a phase advance amount or delay amount of the internal timing signal with respect to
An adjustment unit that adjusts the clock frequency according to the amount of advance or delay of the phase detected by the detection unit ;
The clock generation unit generates an internal clock signal having a clock frequency according to a control value,
The adjusting unit adjusts the clock frequency by adding or subtracting a predetermined value to a reference value of the control value according to the amount of advance or delay of the phase, and further adjusts the phase of the phase detected by the detector. Taking statistics of the amount of change of the advance amount or the delay amount, and correcting the reference value when the statistical value is not included in the predetermined range;
Timing synchronizer. An acquisition unit for acquiring a reference timing signal indicating a predetermined time interval and reference time information indicating a reference time corresponding to the reference timing signal;
A first clock generator for generating a first internal clock signal having a first clock frequency;
A first time information generating unit that generates an internal timing signal indicating the predetermined time interval and an internal time information indicating an internal time corresponding to the internal timing signal based on the first internal clock signal;
The reference timing signal and the internal timing signal, and the reference time information and the internal time information are compared to detect the advance or delay of the internal timing signal with respect to the reference timing signal, and the reference timing signal A first detector for detecting an amount of advance or delay of the phase of the internal timing signal with respect to
A first adjustment unit that adjusts the first clock frequency according to an amount of advance or delay of the phase detected by the first detection unit;
An operational clock including
A second clock generator for generating a second internal clock signal having a second clock frequency;
By comparing the reference timing signal and the internal timing signal, and the reference time information and the internal time information, the advance or delay of the internal timing signal with respect to the reference timing signal is detected, and the reference timing A second detector for detecting an amount of advance or delay of the phase of the internal timing signal with respect to a signal;
The second clock frequency used for generating the second internal clock signal by the second clock generation unit according to the phase advance amount or delay amount detected by the second detection unit. A second adjustment unit to be adjusted;
A standby clock unit including
Bei to give a,
The first clock generation unit generates a first internal clock signal having a first clock frequency according to a control value,
The first adjustment unit adjusts the first clock frequency by adding or subtracting a predetermined value to or from a reference value of the control value according to the amount of advance or delay of the phase, and further, adjusts the first clock frequency. Taking statistics of the amount of change in the phase advance amount or delay amount detected by the detection unit, and correcting the reference value when the statistical value is not included in the predetermined range,
Timing synchronizer. Obtaining a reference timing signal indicating a predetermined time interval and reference time information indicating a reference time corresponding to the reference timing signal;
Generate an internal clock signal at the clock frequency,
Based on the internal clock signal, an internal timing signal indicating the predetermined time interval and internal time information indicating an internal time corresponding to the internal timing signal are generated,
The reference timing signal and the internal timing signal, and the reference time information and the internal time information are compared to detect the advance or delay of the internal timing signal with respect to the reference timing signal, and the reference timing signal Detecting the amount of advance or delay of the phase of the internal timing signal with respect to
Adjust the clock frequency according to the amount of phase advance or delay ,
The process of generating the internal clock signal generates an internal clock signal having a clock frequency according to a control value,
The process of adjusting the clock frequency adjusts the clock frequency by adding or subtracting a predetermined value to the reference value of the control value according to the amount of advance or delay of the phase, and further, adjusts the phase of the internal timing signal. Taking a statistic of the amount of change in the phase advance or lag detected by the process of detecting the amount of advance or lag, and correcting the reference value when the statistic is not included in a predetermined range;
Timing synchronization method.

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