CN106169949B - Baseband signal bit synchronous clock broadband self-adaptive extraction device and method - Google Patents
Baseband signal bit synchronous clock broadband self-adaptive extraction device and method Download PDFInfo
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- CN106169949B CN106169949B CN201610706012.5A CN201610706012A CN106169949B CN 106169949 B CN106169949 B CN 106169949B CN 201610706012 A CN201610706012 A CN 201610706012A CN 106169949 B CN106169949 B CN 106169949B
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- 230000001360 synchronised effect Effects 0.000 title claims abstract description 66
- 238000000605 extraction Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims description 17
- 238000007781 pre-processing Methods 0.000 claims abstract description 19
- 238000001914 filtration Methods 0.000 claims abstract description 13
- 238000007493 shaping process Methods 0.000 claims abstract description 13
- 230000003321 amplification Effects 0.000 claims abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 4
- 238000001514 detection method Methods 0.000 claims description 20
- 230000003044 adaptive effect Effects 0.000 claims description 13
- 238000003708 edge detection Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000000630 rising effect Effects 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention relates to a broadband self-adaptive extraction device of a baseband signal bit synchronous clock, which comprises a signal preprocessing module and a bit synchronous clock extraction module connected with the signal preprocessing module. The invention also relates to a baseband signal bit synchronous clock broadband self-adaptive extraction method, which is used for preprocessing received baseband signals such as amplification, filtering, shaping and the like, and then realizing bit synchronous clock extraction on an FPGA or CPLD hardware platform, and comprises the following steps: and latching the shaped baseband signal, detecting signal edges, detecting minimum pulse width and detecting phase, and finally completing the extraction of the bit synchronous clock by a synchronous pulse forming unit. The invention is easy to realize, can adaptively track the frequency of the baseband signal in a wider frequency dynamic range, can rapidly and accurately extract the bit synchronous clock signal, and has stable generated bit synchronous clock signal and small phase jitter.
Description
Technical Field
The invention relates to the technical field of communication system synchronization, in particular to a baseband signal bit synchronous clock broadband self-adaptive extraction device and method.
Background
Synchronization plays a very important role in a communication system, and the quality of performance directly affects the effectiveness and reliability of the communication system. Wherein bit synchronization, also called symbol synchronization, is a primary condition for achieving correct recovery of symbol information.
In a digital communication system, a phase locking method is generally adopted to extract a bit synchronous clock, and the bit synchronous clock is generally composed of a high-stability quartz crystal oscillator, a frequency divider, a phase comparator, a pulse addition and subtraction controller and the like. This method requires a priori knowledge, i.e. the known symbol rate, from which the division factor of the divider is determined, and it is difficult to achieve the synchronization effect again after the symbol rate is adjusted.
Disclosure of Invention
Aiming at the self-adaptive synchronization problem after the code element rate is adjusted or changed, the invention utilizes the minimum pulse width detection technology to improve the existing phase locking method, and provides a baseband signal bit synchronous clock broadband self-adaptive extraction device based on FPGA/CPLD and a working method thereof.
In order to solve the above technical problems, the present invention provides a baseband signal bit synchronous clock broadband adaptive extraction device, comprising: and the signal preprocessing module is connected with the bit synchronous clock extraction module.
Further, the signal preprocessing module includes: an amplifier module, a filter module, and a pulse shaping module; the signal preprocessing module is suitable for reproducing baseband data signals subjected to channel attenuation, filtering and noise interference; the amplifier module is suitable for amplifying baseband data signals subjected to channel attenuation, filtering and noise interference; the filter module is suitable for filtering out-of-band noise and improving signal quality; the pulse shaping module is suitable for shaping the filter output signal into a high-low level signal, namely a regenerated baseband pulse signal.
Further, the bit synchronous clock extraction module includes: the system clock, the latch unit, the edge detection, the minimum pulse width detection, the phase detection and the synchronous pulse formation; the bit synchronous clock extraction module is suitable for the regenerated baseband data signal bit synchronous clock provided by the broadband self-adaptive extraction signal preprocessing module; the latch unit, the edge detection, the minimum pulse width detection, the phase detection and the synchronous pulse formation are respectively connected with a system clock; the system clock is suitable for the quartz crystal oscillator to generate a high-stability clock signal; the latch unit is suitable for buffering the shaped regenerated baseband signal to synchronize with a system clock; the edge detection is adapted to detect rising and falling edges of the baseband signal; the minimum pulse width detection is suitable for adaptively detecting the minimum pulse width of the baseband signal in a wider frequency band range and is used as a reference basis for adjusting the output frequency parameter of the bit synchronous clock; the phase detection is suitable for calculating the phase difference between the rising edge/falling edge signal of the edge detection and the bit synchronous clock signal generated by the synchronous pulse forming unit, and is used as a reference basis for adjusting the phase parameter output by the bit synchronous clock; the synchronization pulse formation is adapted to generate a bit synchronization clock signal based on the phase difference and the minimum pulse width.
In order to solve the same technical problems, the invention also provides a wideband self-adaptive extraction working method of the baseband signal bit synchronous clock.
The baseband signal bit synchronous clock broadband self-adaptive extraction device comprises: and the signal preprocessing module is connected with the bit synchronous clock extraction module.
Further, the signal preprocessing module is suitable for being realized by hardware, and the bit synchronous clock extraction module is suitable for being realized by adopting a hardware description language based on an FPGA or a CPLD. The working method comprises the following specific steps: (1) receive baseband signal amplification; (2) Selecting a filter according to the frequency range of the baseband signal, and filtering the received baseband signal; (3) shaping the zero crossing comparison into a high-low level pulse signal; (4) And realizing the self-adaptive extraction of the bit synchronous clock on an FPGA or CPLD hardware platform.
Further, implementing bit-synchronized clock adaptive extraction on an FPGA or CPLD hardware platform includes: (1) latching the shaped baseband signal; (2) detecting a signal edge; (3) Detecting the minimum pulse width, and measuring the minimum pulse width by adopting an equal-precision measurement principle when the minimum pulse width is smaller; (4) phase difference detection; (5) The generation of the bit synchronizing clock is accomplished by the synchronizing pulse forming unit based on the minimum pulse width and the phase difference.
The invention has the beneficial effects that:
(1) The bit synchronous clock extraction is realized by adopting FPGA or CPLD hardware, the cost is low, and the method is suitable for small-sized high-speed working clock extraction circuits.
(2) And automatically tracking the minimum pulse width according to the code element rate, adaptively adjusting the frequency division coefficient, and rapidly locking the frequency and the phase of the bit synchronous clock.
(3) When the code element rate is higher, the minimum pulse width is automatically tracked by adopting the principle of equal-precision measurement, and the measurement precision of the minimum pulse width is high.
Drawings
The invention will be further described with reference to the drawings and examples.
FIG. 1 is a schematic block diagram of an embodiment 1 of a baseband signal bit-synchronous clock wideband adaptive extraction apparatus according to the present invention;
fig. 2 is a flowchart of the working method of the wideband adaptive extraction device for baseband signal bit synchronization clock according to the embodiment 2 of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
Example 1
Fig. 1 is a schematic block diagram of a baseband signal bit-synchronous clock broadband adaptive extraction device of the present invention.
As shown in fig. 1, the present invention provides a baseband signal bit synchronous clock broadband adaptive extraction device, which comprises: and the signal preprocessing module is connected with the bit synchronous clock extraction module.
Specifically, the signal preprocessing module includes: an amplifier module, a filter module, and a pulse shaping module; the signal preprocessing module is suitable for reproducing baseband data signals subjected to channel attenuation, filtering and noise interference; the amplifier module is suitable for amplifying baseband data signals subjected to channel attenuation, filtering and noise interference; the filter module is suitable for filtering out-of-band noise and improving signal quality; the pulse shaping module is suitable for shaping the filter output signal into a high-low level signal, namely a regenerated baseband pulse signal.
Further, the bit synchronous clock extraction module includes: the system clock, the latch unit, the edge detection, the minimum pulse width detection, the phase detection and the synchronous pulse formation; the bit synchronous clock extraction module is suitable for the regenerated baseband data signal bit synchronous clock provided by the broadband self-adaptive extraction signal preprocessing module; the latch unit, the edge detection, the minimum pulse width detection, the phase detection and the synchronous pulse formation are respectively connected with a system clock; the system clock is suitable for the quartz crystal oscillator to generate a high-stability clock signal; the latch unit is suitable for buffering the shaped regenerated baseband signal to synchronize with a system clock; the edge detection is adapted to detect rising and falling edges of the baseband signal; the minimum pulse width detection is suitable for adaptively detecting the minimum pulse width of the baseband signal in a wider frequency band range and is used as a reference basis for adjusting the output frequency parameter of the bit synchronous clock; the phase detection is suitable for calculating the phase difference between the rising edge/falling edge signal of the edge detection and the bit synchronous clock signal generated by the synchronous pulse forming unit, and is used as a reference basis for adjusting the phase parameter output by the bit synchronous clock; the synchronization pulse formation is adapted to generate a bit synchronization clock signal based on the phase difference and the minimum pulse width.
Example 2
On the basis of embodiment 1, the invention also provides a wideband adaptive extraction working method of the baseband signal bit synchronous clock, wherein the wideband adaptive extraction device of the baseband signal bit synchronous clock comprises the following steps: and the signal preprocessing module is connected with the bit synchronous clock extraction module.
Further, the implementation process of the wideband adaptive extraction working method of the baseband signal bit synchronous clock is as follows:
fig. 2 shows a flowchart of the working method of the baseband signal bit synchronous clock broadband adaptive extraction device.
(1) Receiving baseband signals for amplification;
(2) Selecting a filter according to the frequency range of the baseband signal, and filtering the received baseband signal;
(3) Zero-crossing comparison shaping is carried out to obtain a high-low level pulse signal;
(4) And realizing the self-adaptive extraction of the bit synchronous clock on an FPGA or CPLD hardware platform.
Further, implementing bit-synchronized clock adaptive extraction on an FPGA or CPLD hardware platform includes:
(1) Latching the shaped baseband signal;
(2) Detecting a signal edge;
(3) Detecting a minimum pulse width;
(4) Detecting a phase difference;
(5) The generation of the bit synchronizing clock is accomplished by the synchronizing pulse forming unit based on the minimum pulse width and the phase difference.
With the above-described preferred embodiments according to the present invention as an illustration, the above-described descriptions can be used by persons skilled in the relevant art to make various changes and modifications without departing from the scope of the technical idea of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.
Claims (4)
1. The utility model provides a baseband signal bit synchronous clock wide band self-adaptation extraction element which characterized in that includes:
the signal preprocessing module is connected with the bit synchronous clock extraction module;
the bit synchronous clock extraction module comprises: the system clock, the latch unit, the edge detection, the minimum pulse width detection, the phase detection and the synchronous pulse formation;
the bit synchronous clock extraction module is suitable for the regenerated baseband data signal bit synchronous clock provided by the broadband self-adaptive extraction signal preprocessing module;
the latch unit, the edge detection, the minimum pulse width detection, the phase detection and the synchronous pulse formation are respectively connected with a system clock;
the system clock is suitable for the quartz crystal oscillator to generate a high-stability clock signal;
the latch unit is suitable for buffering the shaped regenerated baseband signal to synchronize with a system clock;
the edge detection is adapted to detect rising and falling edges of the baseband signal;
the minimum pulse width detection is suitable for adaptively detecting the minimum pulse width of the baseband signal in a wider frequency band range and is used as a reference basis for adjusting the output frequency parameter of the bit synchronous clock;
the phase detection is suitable for calculating the phase difference between the rising edge/falling edge signal of the edge detection and the bit synchronous clock signal generated by the synchronous pulse forming unit, and is used as a reference basis for adjusting the phase parameter output by the bit synchronous clock;
the synchronization pulse formation is adapted to generate a bit synchronization clock signal based on the phase difference and the minimum pulse width.
2. The apparatus of claim 1, wherein,
the signal preprocessing module comprises: an amplifier module, a filter module, and a pulse shaping module;
the signal preprocessing module is suitable for reproducing baseband data signals subjected to channel attenuation, filtering and noise interference;
the amplifier module is suitable for amplifying baseband data signals subjected to channel attenuation, filtering and noise interference;
the filter module is suitable for filtering out-of-band noise and improving signal quality;
the pulse shaping module is suitable for shaping the filter output signal into a high-low level signal, namely a regenerated baseband pulse signal.
3. A broadband self-adaptive extraction method of baseband signal bit synchronous clock is characterized in that,
the implementation of the baseband signal bit-synchronous clock broadband adaptive extraction device according to claim 1 or 2.
4. The baseband signal bit synchronous clock wideband adaptive extraction method of claim 3, comprising:
the signal preprocessing module is suitable for hardware implementation, the bit synchronous clock extraction module is suitable for implementation based on FPGA or CPLD by adopting a hardware description language, and the main working method comprises the following steps: receiving baseband signals for amplification; selecting a filter according to the frequency range of the baseband signal, and filtering the received baseband signal; zero-crossing comparison shaping is carried out to obtain a high-low level pulse signal; then, the bit synchronous clock extraction is realized on the FPGA or CPLD hardware platform, and the method further comprises the following steps: and latching the shaped baseband signal, detecting the signal edge, simultaneously detecting the minimum pulse width and the phase difference, measuring the minimum pulse width by adopting an equal-precision measurement principle when the minimum pulse width is smaller, and finally completing the generation of the bit synchronous clock by a synchronous pulse forming unit according to the minimum pulse width and the phase difference.
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| CN107483170A (en) * | 2017-07-14 | 2017-12-15 | 天津大学 | A kind of binary baseband signal bit synchronization Clock Extraction and digital display method |
| CN111130534B (en) * | 2019-12-20 | 2024-03-01 | 钜泉光电科技(上海)股份有限公司 | Buffer circuit and crystal oscillator circuit |
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| US6272441B1 (en) * | 1998-10-12 | 2001-08-07 | Peter Peyerl | Method for determining the pulse response of a broad band linear system and a measuring circuit for carrying out the method |
| CN102611447A (en) * | 2012-03-26 | 2012-07-25 | 东北大学 | Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array) |
| CN102904849A (en) * | 2011-07-25 | 2013-01-30 | 苏州东奇信息科技有限公司 | Burst communication system utilizing transient peak energy |
| CN104111481A (en) * | 2014-07-30 | 2014-10-22 | 桂林电子科技大学 | Synchronous clock phase difference measuring system and method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6272441B1 (en) * | 1998-10-12 | 2001-08-07 | Peter Peyerl | Method for determining the pulse response of a broad band linear system and a measuring circuit for carrying out the method |
| CN102904849A (en) * | 2011-07-25 | 2013-01-30 | 苏州东奇信息科技有限公司 | Burst communication system utilizing transient peak energy |
| CN102611447A (en) * | 2012-03-26 | 2012-07-25 | 东北大学 | Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array) |
| CN104111481A (en) * | 2014-07-30 | 2014-10-22 | 桂林电子科技大学 | Synchronous clock phase difference measuring system and method |
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Effective date of registration: 20231204 Address after: 213, Block A, Maker Service Center, No. 1, Xihu Road, Wujin National High-tech Industrial Development Zone, Changzhou City, Jiangsu Province, 213000 Patentee after: JIANGSU LAITE BEIDOU INFORMATION TECHNOLOGY CO.,LTD. Address before: 213001, No. 1801, Wu Cheng Road, bell tower, Changzhou, Jiangsu Patentee before: JIANGSU University OF TECHNOLOGY |