CN106169949B - Baseband signal bit synchronous clock broadband self-adaptive extraction device and method - Google Patents

Abstract

The invention relates to a baseband signal bit synchronous clock broadband self-adaptive extraction device, comprising a signal preprocessing module and a bit synchronous clock extraction module connected with the signal preprocessing module. The present invention also relates to a baseband signal bit synchronous clock broadband adaptive extraction method, which preprocesses the received baseband signal by amplifying, filtering, shaping, etc., and then realizes bit synchronous clock extraction on the FPGA or CPLD hardware platform, including: latching The shaped baseband signal, signal edge detection, minimum pulse width detection and phase detection, and finally the synchronization pulse forming unit completes the extraction of the bit synchronization clock. The invention is easy to implement, can adaptively track the baseband signal frequency in a wide frequency dynamic range, can quickly and accurately extract the bit synchronous clock signal, and the generated bit synchronous clock signal is stable and has small phase jitter.

Description

Device and method for broadband adaptive extraction of baseband signal bit synchronous clock

technical field

The invention relates to the technical field of communication system synchronization, in particular to a baseband signal bit synchronization clock broadband adaptive extraction device and method.

Background technique

Synchronization plays a very important role in the communication system, and its performance directly affects the effectiveness and reliability of the communication system. Among them, the bit synchronization is also called the symbol synchronization, which is the first condition to realize the correct recovery of the symbol information.

In digital communication systems, the phase-locking method is usually used to extract bit-synchronous clocks, which are generally composed of high-stable quartz crystal oscillators, frequency dividers, phase comparators, and pulse addition and subtraction controllers. This method requires prior knowledge, that is, the known symbol rate, which determines the frequency division coefficient of the frequency divider. After the symbol rate is adjusted, it is difficult to achieve the synchronization effect again.

Contents of the invention

The purpose of the present invention is to improve the existing phase-locking method by using the minimum pulse width detection technology for the above-mentioned problem of self-adaptive synchronization after symbol rate adjustment or change, and propose a baseband signal bit synchronization clock wide-frequency automatic synchronization based on FPGA/CPLD. Adapt to the extraction device and its working method.

In order to solve the above technical problems, the present invention provides a baseband signal bit synchronous clock broadband adaptive extraction device, including: a signal preprocessing module, and a bit synchronous clock extraction module connected to the signal preprocessing module.

Further, the signal preprocessing module includes: an amplifier module, a filter module, and a pulse shaping module; the signal preprocessing module is suitable for regenerating baseband data signals that have been channel attenuated, filtered, and noise interfered; the amplifier module is suitable for amplifying Baseband data signals through channel attenuation, filtering, and noise interference; the filter module is suitable for filtering out-of-band noise and improving signal quality; the pulse shaping module is suitable for shaping the filter output signal into high and low level signals, namely Regenerate the baseband pulse signal.

Further, the bit synchronous clock extraction module includes: system clock, latch unit, edge detection, minimum pulse width detection, phase detection, synchronous pulse formation; the bit synchronous clock extraction module is suitable for broadband adaptive extraction signal preprocessing module The provided regenerative baseband data signal bit synchronous clock; the latch unit, edge detection, minimum pulse width detection, phase detection, and synchronous pulse formation are respectively connected with the system clock; the system clock is suitable for a quartz crystal oscillator to generate high stability clock signal; the latch unit is suitable for buffering the regenerated baseband signal after shaping, so that it is synchronized with the system clock; the edge detection is suitable for detecting the rising edge and falling edge of the baseband signal; the minimum pulse width detection is suitable for relatively Adaptively detect the minimum pulse width of the baseband signal in a wide frequency band as a reference for adjusting the output frequency parameters of the bit synchronization clock; the phase detection is suitable for calculating the rising edge/falling edge signal of edge detection and the synchronous pulse forming unit. The phase difference of the bit synchronous clock signal is used as a reference basis for adjusting the phase parameters of the bit synchronous clock output; the synchronous pulse formation is suitable for generating the bit synchronous clock signal according to the phase difference and the minimum pulse width.

In another aspect, in order to solve the same technical problem, the present invention also provides a working method for wide-band adaptive extraction of baseband signal bit synchronization clock.

The baseband signal bit synchronous clock broadband adaptive extraction device includes: a signal preprocessing module, and a bit synchronous clock extraction module connected to the signal preprocessing module.

Further, the signal preprocessing module is suitable for hardware implementation, and the bit synchronous clock extraction module is suitable for implementation based on FPGA or CPLD by using hardware description language. The specific steps of the working method include: (1) receiving baseband signal amplification; (2) selecting a filter according to the baseband signal frequency range, and filtering the received baseband signal; (3) zero-crossing comparison shaping into high and low level pulse signals ; (4) realize self-adaptive extraction of bit synchronous clock on FPGA or CPLD hardware platform.

Further, realizing bit synchronous clock self-adaptive extraction on FPGA or CPLD hardware platform includes: (1) baseband signal after latch shaping; (2) detection signal edge; (3) minimum pulse width detection, when the minimum pulse width is smaller , using the same precision measurement principle to measure the minimum pulse width; (4) Phase difference detection; (5) The synchronization pulse forming unit completes the generation of the bit synchronization clock according to the minimum pulse width and phase difference.

The beneficial effects of the present invention are:

(1) FPGA or CPLD hardware is used to realize bit-synchronous clock extraction, which is low in cost and suitable for small-scale high-speed clock extraction circuits.

(2) Automatically track the minimum pulse width according to the symbol rate, adaptively adjust the frequency division coefficient, and quickly lock the frequency and phase of the bit synchronization clock.

(3) When the symbol rate is high, the equal-precision measurement principle is used to automatically track the minimum pulse width, and the measurement accuracy of the minimum pulse width is high.

Description of drawings

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Fig. 1 is the functional block diagram of baseband signal bit synchronous clock broadband adaptive extraction device embodiment 1 of the present invention;

Fig. 2 is a flow chart of the working method of Embodiment 2 of the device for extracting baseband signal bit synchronous clock and broadband adaptively according to the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings. These drawings are all simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, so they only show the configurations related to the present invention.

Example 1

Fig. 1 is a functional block diagram of a baseband signal bit synchronous clock broadband adaptive extraction device of the present invention.

As shown in FIG. 1 , a baseband signal bit synchronous clock broadband adaptive extraction device of the present invention includes: a signal preprocessing module, and a bit synchronous clock extraction module connected to the signal preprocessing module.

Specifically, the signal preprocessing module includes: an amplifier module, a filter module, and a pulse shaping module; the signal preprocessing module is suitable for regenerating a baseband data signal that has been channel attenuated, filtered, and noise interfered; the amplifier module is suitable for Amplifying the baseband data signal through channel attenuation, filtering, and noise interference; the filter module is suitable for filtering out-of-band noise and improving signal quality; the pulse shaping module is suitable for shaping the filter output signal into high and low level signals, That is, the baseband pulse signal is reproduced.

Further, the bit synchronous clock extraction module includes: system clock, latch unit, edge detection, minimum pulse width detection, phase detection, synchronous pulse formation; the bit synchronous clock extraction module is suitable for broadband adaptive extraction signal preprocessing module The provided regenerative baseband data signal bit synchronous clock; the latch unit, edge detection, minimum pulse width detection, phase detection, and synchronous pulse formation are respectively connected with the system clock; the system clock is suitable for a quartz crystal oscillator to generate high stability clock signal; the latch unit is suitable for buffering the regenerated baseband signal after shaping, so that it is synchronized with the system clock; the edge detection is suitable for detecting the rising edge and falling edge of the baseband signal; the minimum pulse width detection is suitable for relatively Adaptively detect the minimum pulse width of the baseband signal in a wide frequency band as a reference for adjusting the output frequency parameters of the bit synchronization clock; the phase detection is suitable for calculating the rising edge/falling edge signal of edge detection and the synchronous pulse forming unit. The phase difference of the bit synchronous clock signal is used as a reference basis for adjusting the phase parameters of the bit synchronous clock output; the synchronous pulse formation is suitable for generating the bit synchronous clock signal according to the phase difference and the minimum pulse width.

Example 2

On the basis of Embodiment 1, the present invention also provides a baseband signal bit-synchronous clock broadband adaptive extraction method, wherein the baseband signal bit-synchronous clock broadband adaptive extraction device includes: a signal preprocessing module, and the signal preprocessing module A bit synchronous clock extraction module connected to the processing module.

Further, the specific implementation process of a baseband signal bit synchronous clock broadband adaptive extraction method is as follows:

Fig. 2 shows a flow chart of the working method of the baseband signal bit synchronous clock broadband adaptive extraction device of the present invention.

(1) Receive baseband signal amplification;

(2) Select a filter according to the frequency range of the baseband signal, and filter the received baseband signal;

(3) The zero-crossing comparison is shaped into a high-low level pulse signal;

(4) Realize self-adaptive extraction of bit synchronous clock on FPGA or CPLD hardware platform.

Further, realizing bit synchronization clock adaptive extraction on the FPGA or CPLD hardware platform includes:

(1) Latch the baseband signal after shaping;

(2) detection signal edge;

(3) Minimum pulse width detection;

(4) Phase difference detection;

(5) The bit synchronous clock is generated by the synchronous pulse forming unit according to the minimum pulse width and phase difference.

Inspired by the above-mentioned ideal embodiment according to the present invention, through the above-mentioned description content, relevant workers can make various changes and modifications within the scope of not departing from the technical idea of the present invention. The technical scope of the present invention is not limited to the content in the specification, but must be determined according to the scope of the claims.

Claims (4)

1. A baseband signal bit synchronous clock broadband adaptive extraction device, is characterized in that, comprises: A signal preprocessing module, a bit synchronous clock extraction module connected to the signal preprocessing module; The bit synchronous clock extraction module includes: system clock, latch unit, edge detection, minimum pulse width detection, phase detection, synchronous pulse formation; The bit synchronous clock extraction module is suitable for the regenerated baseband data signal bit synchronous clock provided by the broadband adaptive extraction signal preprocessing module; The latch unit, edge detection, minimum pulse width detection, phase detection, and synchronous pulse formation are respectively connected to the system clock; The system clock is suitable for a quartz crystal oscillator to generate a high-stability clock signal; The latch unit is suitable for buffering the reshaped baseband signal so as to be synchronized with the system clock; The edge detection is suitable for detecting rising and falling edges of baseband signals; The minimum pulse width detection is suitable for adaptively detecting the minimum pulse width of the baseband signal within a wider frequency band, as a reference basis for adjusting the output frequency parameter of the bit synchronization clock; The phase detection is suitable for calculating the phase difference between the rising edge/falling edge signal of the edge detection and the bit synchronous clock signal generated by the synchronous pulse forming unit, as a reference basis for adjusting the phase parameter of the bit synchronous clock output; The synchronous pulse forming is suitable for generating a bit synchronous clock signal according to the phase difference and the minimum pulse width. 2. baseband signal bit synchronous clock broadband adaptive extraction device according to claim 1, is characterized in that, The signal preprocessing module includes: an amplifier module, a filter module, and a pulse shaping module; The signal preprocessing module is suitable for regenerating the baseband data signal after channel attenuation, filtering and noise interference; The amplifier module is suitable for amplifying the baseband data signal through channel attenuation, filtering and noise interference; The filter module is suitable for filtering out-of-band noise and improving signal quality; The pulse shaping module is suitable for shaping the output signal of the filter into high and low level signals, that is, a regenerated baseband pulse signal. 3. A baseband signal bit synchronous clock broadband adaptive extraction method, is characterized in that, Implementation based on the baseband signal bit synchronous clock broadband adaptive extraction device as claimed in claim 1 or 2. 4. baseband signal bit synchronous clock broadband adaptive extraction method according to claim 3, comprising: The signal preprocessing module is suitable for hardware implementation, and the bit synchronous clock extraction module is suitable for implementing based on FPGA or CPLD using a hardware description language. The main working methods include: receiving baseband signal amplification; selecting a filter according to the baseband signal frequency range, and The received baseband signal is filtered; the zero-crossing comparison is shaped into a high-low level pulse signal; and then the bit-synchronous clock extraction is realized on the FPGA or CPLD hardware platform, which further includes: latching the shaped baseband signal, detecting the signal edge, and at the same time performing minimum For pulse width detection and phase difference detection, when the minimum pulse width is small, the minimum pulse width is measured by the principle of equal precision measurement, and finally the synchronous pulse forming unit completes the generation of the bit synchronization clock according to the minimum pulse width and phase difference.

Images