CN104111481A - Synchronous clock phase difference measuring system and method - Google Patents
Synchronous clock phase difference measuring system and method Download PDFInfo
- Publication number
- CN104111481A CN104111481A CN201410369321.9A CN201410369321A CN104111481A CN 104111481 A CN104111481 A CN 104111481A CN 201410369321 A CN201410369321 A CN 201410369321A CN 104111481 A CN104111481 A CN 104111481A
- Authority
- CN
- China
- Prior art keywords
- phase difference
- signal
- transmitter
- receiver
- count
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Measuring Phase Differences (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The invention discloses a synchronous clock phase difference measuring system and method. A unipolar conversion unit converts the synchronous signals of a transmitter and a receiver from bipolarity to unipolarity; under the control of the same constant-temperature crystal oscillator, the synchronous signals of the transmitter and the receiver are simultaneously sent to a pulse counting unit to perform rough measurement of the phase difference and simultaneously sent to a quantization delay unit to perform fine measurement of the phase difference; the sum of the results obtained from the rough measurement and the fine measurement is the phase difference of the synchronous clock signals. The synchronous clock phase difference measuring system and method can precisely measure the phase difference between the synchronous clock signals of the transmitter and the receiver of a coal mine water detecting radar and has significant effects on correction of the synchronous clock phase difference as well as precision enhancement of subsequent inversion calculation.
Description
Technical field
The present invention relates to visit submarine mine and reach technical field, be specifically related to a kind of synchronous clock phase difference measurements system and method.
Background technology
Transient electromagnetic method measurement mechanism is comprised of emission coefficient and receiving system two parts.In transmitting coil, pass to step current I, transmitter current drops to zero by I suddenly, according to electromagnetic coupling theory, and the magnetic field that in transmitting coil, the unexpected variation of electric current will around change at it, this magnetic field is called Primary field, Primary field is around in communication process, as runs into the geologic body of underground good conduction, and portion excites generation induction current within it, claim again eddy current or secondary current, secondary current temporal evolution, thereby produce again new magnetic field around at it, be called secondary magnetic field.Thermal losses due to the good induced currents of plastid conductively, secondary magnetic field is roughly decayed in time by exponential law, form transient magnetic field, secondary magnetic field is mainly derived from the induction current of good plastid conductively, therefore it is comprising the geological information relevant with geologic body, by receiving coil, secondary magnetic field is observed, and data analysis and processing to observation, the relevant physical parameter of underground geologic bodies is made an explanation.
Because submarine mine Dary transient electromagnetic ratio juris is visited in colliery, at transmitter, turn-off the moment of transmitter current, receiver collection receives the pure secondary field that underground medium produces, and therefore needs must, with the work of homophase frequently, could obtain observation data more accurately between transmitter and receiver.Although it is that complementary co-ordination by GPS and constant-temperature crystal oscillator produces synchronous clock that transmitter and receiver that submarine mine reaches is visited in colliery, but the complicacy of exploration geology and not intellectual, the synchronizing clock signals of Receiver And Transmitter is spatially separated, the clock signal that makes transmitter and receiver is not often Complete Synchronization, can produce inevitable phase differential, and this phase place extent the precision of whole system sampling and the accuracy of follow-up inversion algorithm have been determined.Although the clock signal that observation personnel can observe transmitter and receiver by oscillograph judges that whether clock signal is synchronous, but oscillograph often just obtains the observation data of short-term, and can not store phase data, thereby the conclusion obtaining is inaccurate.Visible, adopt oscillograph to observe the clock signal of transmitter and receiver, for the rectification of subsequent transmission machine and receiver synchronous clock, there is certain limitation.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of synchronous clock phase difference measurements system and method, it can measure the phase differential that synchronizing clock signals between the transmitter and receiver that submarine mine reaches is visited in colliery accurately, and can and play obvious effect to the raising of follow-up Inversion Calculation precision to the poor rectification of synchronous clock phase.
For addressing the above problem, the present invention is achieved by the following technical solutions:
Synchronous clock phase difference measurements method, comprises the steps:
Step 1, is converted to respectively unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals by the bipolarity transmitter synchronizing clock signals collecting and bipolarity receiver synchronizing clock signals;
Step 2, carries out the frequency of constant-temperature crystal oscillator output to generate counting pulse signal after frequency multiplication, and the cycle of this counting pulse signal is T;
Step 3, carries out bigness scale amount to the phase differential of transmitter and receiver;
Step 3.1, in unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals, allow first the rising edge of the clock period signal that arrives as the counting commencing signal of each count cycle, the rising edge of the clock period signal that another clock period signal arrives is as the count end signal of each count cycle;
Step 3.2, calculates the complete pulse number N of each count cycle inside counting pulse signal;
Step 4, carries out accurate measurement amount to the phase differential of transmitter and receiver;
Step 4.1, counting pulse signal to each count cycle quantizes time delay, so that the rising edge of first complete pulse of the counting pulse signal of each count cycle or negative edge align with the rising edge of the clock period signal first arriving, and record each count cycle counting pulse signal the chronotron number n of process
1;
Step 4.2, counting pulse signal to each count cycle quantizes time delay, so that the rising edge of last complete pulse of the counting pulse signal of each count cycle or negative edge align with the rising edge of the clock period signal of rear arrival, and record each count cycle counting pulse signal the chronotron number n of process
2; Step 4.3, the phase difference T of transmitter computes and receiver
i,
When counting pulse signal is low level when counting commencing signal arrives, when count end signal is low level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is low level when counting commencing signal arrives, when count end signal is high level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is high level when counting commencing signal arrives, when count end signal is low level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is high level when counting commencing signal arrives, when count end signal is high level while arriving, the phase difference T of transmitter and receiver
ifor
ΔT
i＝NT+(T-n
1t)-(T-n
2t) (4)
In formula (1)-(4), N is complete count pulse number, and T is the cycle of counting pulse signal, n
1clock period that is and first arrives during signal alignment, counting pulse signal the chronotron number of process, n
2be with the clock period of rear arrival during signal alignment, counting pulse signal the chronotron number of process, t is the delay time of chronotron;
Step 5, by the phase difference T of calculated transmitter and receiver
istore.
Said method, also further comprises the phase difference T to calculated transmitter and receiver
ithe step showing.
Said method, also further comprises the phase difference T to calculated transmitter and receiver
isend into the step that host computer carries out Synchronization Analysis.
The synchronous clock phase difference measurements system designing based on above-mentioned synchronous clock phase difference measurements method, mainly by the first unipolarity converting unit, the second unipolarity converting unit, constant-temperature crystal oscillator, phase-locked loop circuit, count pulse unit, quantification delay unit, totalizer and storer; Wherein transmitter synchronizing clock signals is connected respectively to count pulse unit and quantizes on an input end of delay unit after the first unipolarity converting unit, and receiver synchronizing clock signals is connected respectively to count pulse unit and quantizes on another input end of delay unit after the second unipolarity converting unit; The output terminal of constant-temperature crystal oscillator is connected with the input end of phase-locked loop circuit, and the output terminal of phase-locked loop circuit is connection count pulse unit and the another input end that quantizes delay unit respectively; The output terminal of count pulse unit is connected to an input end of totalizer, and the output terminal that quantizes delay unit is connected to another input end of totalizer, the output terminal connected storage of totalizer.
In said system, described the first unipolarity converting unit and the second unipolarity converting unit be by conducting diode D1, D2, optocoupler Opt1, Opt2, Sheffer stroke gate NAND1, NAND2, XOR gate XOR1, pull-up resistor R2, R3, R5, R6, and filter capacitor C1, C2 form; The positive pole of ambipolar transmitter or receiver synchronizing clock signals is divided into 2 tunnels, and a road connects the input anode of optocoupler Opt1 through conducting diode D1, and another road connects the input cathode of optocoupler Opt2; The negative pole of synchronizing clock signals is divided into 2 tunnels, and a road connects the input anode of optocoupler Opt2 through conducting diode D2, and another road connects the input cathode of optocoupler Opt1; The output head anode of optocoupler Opt1 connects 2 input ends of Sheffer stroke gate NAND1 simultaneously, and the negative pole of output end of optocoupler Opt1 connects ground connection GND; 2 input ends of Sheffer stroke gate NAND1 connect positive source VCC through pull-up resistor R2, and the output terminal of Sheffer stroke gate NAND1 connects positive source VCC through pull-up resistor R3, and the output terminal of Sheffer stroke gate NAND1 is through filter capacitor C1 ground connection GND; The output terminal of Sheffer stroke gate NAND1 connects one end of XOR gate XOR1; The output head anode of optocoupler Opt2 connects 2 input ends of Sheffer stroke gate NAND2 simultaneously, and the negative pole of output end of optocoupler Opt2 connects ground connection GND; 2 input ends of Sheffer stroke gate NAND2 connect positive source VCC through pull-up resistor R5, and the output terminal of Sheffer stroke gate NAND2 connects positive source VCC through pull-up resistor R6, and the output terminal of Sheffer stroke gate NAND2 is through filter capacitor C2 ground connection GND; The output terminal of Sheffer stroke gate NAND2 connects one end of XOR gate XOR2.
In said system, described quantification delay unit is comprised of a plurality of chronotrons.
In said system, on the output terminal of described storer, be also connected to a display.
In said system, the output terminal of described storer is also connected with a host computer.
Principle of the present invention is: unipolarity converting unit is carried out bipolarity to unipolar conversion to the synchronizing signal of transmitter and receiver respectively, above-mentioned two under the control of same constant-temperature crystal oscillator, be sent in step-by-step counting unit simultaneously and both phase differential carried out to bigness scale amount and be sent to simultaneously quantizing, in delay unit, both phase differential are carried out to accurate measurement amount, bigness scale amount and accurate measurement amount sum are the phase differential of synchronizing clock signals.
Compared with prior art, the present invention has following features:
1, high resolving power and high stability, compare with traditional oscillograph, and highest resolution can reach 200ps, and can measure for a long time the phase differential of synchronizing clock signals, and phase data is stored and shown on LCD;
2, convenient, low-power consumption, compares with traditional oscillograph, and this synchronous clock measuring system is more convenient, low-power consumption, only needs some powered battery, and can not have in the wild, in the situation of mains-supplied, can work for a long time;
3, easily realize, cost is low, adopts d type flip flop, chronotron and the count pulse of FPGA inside, bipolarity change-over circuit, Liquid Crystal Module and memory module just can realize.
Accompanying drawing explanation
Fig. 1 is a kind of synchronous clock phase difference measurements system chart.
Fig. 2 is unipolarity converting unit schematic diagram.
Fig. 3 is a kind of synchronous clock phase difference measurements method flow diagram.
Fig. 4 is unipolarity converting unit waveform.
Fig. 5 is pulse counting method schematic diagram.
Fig. 6 is for quantizing time expander method schematic diagram.
Embodiment
A synchronous clock phase difference measurements system, as shown in Figure 1, mainly by the first unipolarity converting unit, the second unipolarity converting unit, constant-temperature crystal oscillator, phase-locked loop circuit, count pulse unit, quantification delay unit, totalizer and storer.Wherein transmitter synchronizing clock signals is connected respectively to count pulse unit and quantizes on an input end of delay unit after the first unipolarity converting unit, and receiver synchronizing clock signals is connected respectively to count pulse unit and quantizes on another input end of delay unit after the second unipolarity converting unit.The output terminal of constant-temperature crystal oscillator is connected with the input end of phase-locked loop circuit, and the output terminal of phase-locked loop circuit is connection count pulse unit and the another input end that quantizes delay unit respectively.The output terminal of count pulse unit is connected to an input end of totalizer, and the output terminal that quantizes delay unit is connected to another input end of totalizer, the output terminal connected storage of totalizer.In addition,, for measurement result intuitively being shown, on the output terminal of described storer, be also connected to a display.And in order can gained measurement result to be further processed and to be analyzed, the output terminal of described storer be also connected with a host computer.
The first unipolarity converting unit is identical with the structure of the second unipolarity converting unit, as shown in Figure 2, and by conducting diode D1, D2, optocoupler Opt1, Opt2, Sheffer stroke gate NAND1, NAND2, XOR gate XOR1, pull-up resistor R2, R3, R5, R6, and filter capacitor C1, C2 form.As shown in Figure 2.The positive pole of ambipolar transmitter or receiver synchronizing clock signals is divided into 2 tunnels, and a road connects the input anode of optocoupler Opt1 through conducting diode D1, and another road connects the input cathode of optocoupler Opt2.The negative pole of synchronizing clock signals is divided into 2 tunnels, and a road connects the input anode of optocoupler Opt2 through conducting diode D2, and another road connects the input cathode of optocoupler Opt1.The output head anode of optocoupler Opt1 connects 2 input ends of Sheffer stroke gate NAND1 simultaneously, and the negative pole of output end of optocoupler Opt1 connects ground connection GND.2 input ends of Sheffer stroke gate NAND1 connect positive source VCC through pull-up resistor R2, and the output terminal of Sheffer stroke gate NAND1 connects positive source VCC through pull-up resistor R3, and the output terminal of Sheffer stroke gate NAND1 is through filter capacitor C1 ground connection GND.The output terminal of Sheffer stroke gate NAND1 connects one end of XOR gate XOR1.The output head anode of optocoupler Opt2 connects 2 input ends of Sheffer stroke gate NAND2 simultaneously, and the negative pole of output end of optocoupler Opt2 connects ground connection GND.2 input ends of Sheffer stroke gate NAND2 connect positive source VCC through pull-up resistor R5, and the output terminal of Sheffer stroke gate NAND2 connects positive source VCC through pull-up resistor R6, and the output terminal of Sheffer stroke gate NAND2 is through filter capacitor C2 ground connection GND.The output terminal of Sheffer stroke gate NAND2 connects one end of XOR gate XOR2.
Quantizing delay unit is comprised of a plurality of chronotrons.In the preferred embodiment of the present invention, select 4 grades of chronotrons as example calculations T1.Counting pulse signal is the signal input as d type flip flop through internal delay time device, and OUTA signal is as the clock input of d type flip flop, and d type flip flop is in the conversion of rising edge clock generation state, and output signal equals input signal.In chronotron chain, the delay time of each chronotron is t=200ps left and right, therefore every through a chronotron, and count pulse can time delay 200ps with respect to OUTA signal.By the coding to d type flip flop, just can know count pulse do not line up part be low level or high level.When count pulse and OUTA signal do not line up part and are low level, before in chronotron chain, n1-1 chronotron is low level, and n1 chronotron is high level, illustrates that count pulse is after n1 chronotron, the negative edge of count pulse aligns with the rising edge of OUTA, time T 1=n1t.When count pulse and OUTA signal do not line up part and are high level, before in chronotron chain, n1-1 chronotron is high level, and n1 chronotron is low level, illustrates that count pulse is after n1 chronotron, the rising edge of count pulse aligns with the rising edge of OUTA, time T 1=n1t.In like manner can be in the hope of T2.
A synchronous clock phase difference measurements method, as shown in Figure 3, comprises the steps:
Step 1, is converted to respectively unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals by the bipolarity transmitter synchronizing clock signals collecting and bipolarity receiver synchronizing clock signals.
Because transmitter synchronizing clock signals A and receiver synchronizing clock signals B are ambipolar, and FPGA cannot process negative level, therefore needs unipolarity converting unit.The waveform of unipolarity converting unit as shown in Figure 4.Take synchronizing clock signals A as example.When INA+ is positive voltage, when INA-is negative voltage, optocoupler Opt1 conducting, optocoupler Opt2 cut-off, Sheffer stroke gate NAND1 exports high level, and Sheffer stroke gate NAND2 output low level is exported high level after XOR gate XOR1.In like manner: when INA+ is negative voltage, when INA-is positive voltage, optocoupler Opt1 cut-off, optocoupler Opt2 conducting, Sheffer stroke gate NAND1 output low level, Sheffer stroke gate NAND2 exports high level, after XOR gate XOR1, exports high level, and oscillogram is as shown in Figure 3.Synchronizing clock signals has the sudden change of making zero for twice within each cycle, and therefore the signal sampling pulse of the transponder pulse of this twice Catastrophe control transmitter and receiver need to measure the phase differential of this twice sudden change.
Step 2, carries out the frequency of constant-temperature crystal oscillator output to generate counting pulse signal after frequency multiplication, and the cycle of this counting pulse signal is T.
The synchronizing frequency of bipolar signal is 6.25Hz, and the frequency that converts unipolar signal to is 12.5Hz.Because unipolarity converting unit is full symmetric, the delay time error therefore synchronizing clock signals being caused is negligible.Constant-temperature crystal oscillator output frequency is stable, and degree of stability is fine in a short time, and is not subject to extraneous thermal effect, for FPGA provides accurate clock.FPGA calls the phaselocked loop (PLL) in IP kernel, and the 10MHz frequency frequency multiplication of constant-temperature crystal oscillator output, to 100MHz, can be reduced to counting error so effectively, and error is 10ns.Phase difference measurement module is carried out phase differential precision measurement to synchronizing clock signals A, B, comprises bigness scale amount and accurate measurement amount, is slightly measured as pulse counting method, and essence is measured as quantification time expander method, and both sums are the phase differential of synchronizing clock signals.
Step 3, carries out bigness scale amount to the phase differential of transmitter and receiver.
Step 3.1, in unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals, the rising edge of the clock period signal first arriving is as the counting commencing signal of each count cycle, and the rising edge of the clock period signal that another clock period signal arrives is as the count end signal of each count cycle.
Step 3.2, calculates the complete pulse number N of each count cycle inside counting pulse signal.
As shown in Figure 5, the rising edge of OUTA is as rolling counters forward commencing signal for pulse counting method, and the rising edge of OUTB is as rolling counters forward end signal, count pulse cycle T=10ns, and count results is bigness scale amount.T1 is the part that count pulse and OUTA do not line up, and T2 is the part that count pulse and OUTB do not line up, and measurement result is accurate measurement amount, and accurate measurement amount is realized by internal hardware chronotron lcell and the D-latch of FPGA, quantizes time expander method as shown in Figure 6.
Step 4, carries out accurate measurement amount to the phase differential of transmitter and receiver.
Step 4.1, counting pulse signal to each count cycle quantizes time delay, so that the rising edge of first complete pulse of the counting pulse signal of each count cycle or negative edge align with the rising edge of the clock period signal first arriving, and record each count cycle counting pulse signal the chronotron number n of process
1.
Step 4.2, counting pulse signal to each count cycle quantizes time delay, so that the rising edge of last complete pulse of the counting pulse signal of each count cycle or negative edge align with the rising edge of the clock period signal of rear arrival, and record each count cycle counting pulse signal the chronotron number n of process
2.
Step 4.3, the phase difference T of transmitter computes and receiver
i,
When counting pulse signal is low level when counting commencing signal arrives, when count end signal is low level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is low level when counting commencing signal arrives, when count end signal is high level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is high level when counting commencing signal arrives, when count end signal is low level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is high level when counting commencing signal arrives, when count end signal is high level while arriving, the phase difference T of transmitter and receiver
ifor
ΔT
i＝NT+(T-n
1t)-(T-n
2t) (4)
In formula (1)-(4), N is complete count pulse number, and T is the cycle of counting pulse signal, n
1clock period that is and first arrives during signal alignment, counting pulse signal the chronotron number of process, n
2be with the clock period of rear arrival during signal alignment, counting pulse signal the chronotron number of process, t is the delay time of chronotron.
In Fig. 6, select 4 grades of chronotrons as example calculations T1.Counting pulse signal is the signal input as d type flip flop through internal delay time device, and OUTA signal is as the clock input of d type flip flop, and d type flip flop is in the conversion of rising edge clock generation state, and output signal equals input signal.In chronotron chain, the delay time of each chronotron is t=200ps left and right, therefore every through a chronotron, and count pulse can time delay 200ps with respect to OUTA signal.By the coding to d type flip flop, just can know count pulse do not line up part be low level or high level.When count pulse and OUTA signal do not line up part and are low level, before in chronotron chain, n1-1 chronotron is low level, and n1 chronotron is high level, illustrates that count pulse is after n1 chronotron, the negative edge of count pulse aligns with the rising edge of OUTA, time T 1=n1t.When count pulse and OUTA signal do not line up part and are high level, before in chronotron chain, n1-1 chronotron is high level, and n1 chronotron is low level, illustrates that count pulse is after n1 chronotron, the rising edge of count pulse aligns with the rising edge of OUTA, time T 1=n1t.In like manner can be in the hope of T2.
Step 5, by the phase difference T of calculated transmitter and receiver
istore and show, simultaneously can also be by the phase difference T of calculated transmitter and receiver
isend into the step that host computer carries out Synchronization Analysis.
Claims (8)
1. synchronous clock phase difference measurements method, is characterized in that comprising the steps:
Step 1, is converted to respectively unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals by the bipolarity transmitter synchronizing clock signals collecting and bipolarity receiver synchronizing clock signals;
Step 2, carries out the frequency of constant-temperature crystal oscillator output to generate counting pulse signal after frequency multiplication, and the cycle of this counting pulse signal is T;
Step 3, carries out bigness scale amount to the phase differential of transmitter and receiver;
Step 3.1, in unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals, allow first the rising edge of the clock period signal that arrives as the counting commencing signal of each count cycle, the rising edge of the clock period signal that another clock period signal arrives is as the count end signal of each count cycle;
Step 3.2, calculates the complete pulse number N of each count cycle inside counting pulse signal;
Step 4, carries out accurate measurement amount to the phase differential of transmitter and receiver;
Step 4.1, counting pulse signal to each count cycle quantizes time delay, so that the rising edge of first complete pulse of the counting pulse signal of each count cycle or negative edge align with the rising edge of the clock period signal first arriving, and record each count cycle counting pulse signal the chronotron number n of process
1;
Step 4.2, counting pulse signal to each count cycle quantizes time delay, so that the rising edge of last complete pulse of the counting pulse signal of each count cycle or negative edge align with the rising edge of the clock period signal of rear arrival, and record each count cycle counting pulse signal the chronotron number n of process
2;
Step 4.3, the phase difference T of transmitter computes and receiver
i,
When counting pulse signal is low level when counting commencing signal arrives, when count end signal is low level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is low level when counting commencing signal arrives, when count end signal is high level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is high level when counting commencing signal arrives, when count end signal is low level while arriving, the phase difference T of transmitter and receiver
ifor
When counting pulse signal is high level when counting commencing signal arrives, when count end signal is high level while arriving, the phase difference T of transmitter and receiver
ifor
ΔT
i＝NT+(T-n
1t)-(T-n
2t) (4)
In formula (1)-(4), N is complete count pulse number, and T is the cycle of counting pulse signal, n
1clock period that is and first arrives during signal alignment, counting pulse signal the chronotron number of process, n
2be with the clock period of rear arrival during signal alignment, counting pulse signal the chronotron number of process, t is the delay time of chronotron;
Step 5, by the phase difference T of calculated transmitter and receiver
istore.
2. synchronous clock phase difference measurements method according to claim 1, is characterized in that: also further comprise the phase difference T to calculated transmitter and receiver
ithe step showing.
3. synchronous clock phase difference measurements method according to claim 1 and 2, is characterized in that: also further comprise the phase difference T to calculated transmitter and receiver
isend into the step that host computer carries out Synchronization Analysis.
4. the synchronous clock phase difference measurements system designing based on synchronous clock phase difference measurements method described in claim 1, is characterized in that: mainly by the first unipolarity converting unit, the second unipolarity converting unit, constant-temperature crystal oscillator, phase-locked loop circuit, count pulse unit, quantification delay unit, totalizer and storer; Wherein transmitter synchronizing clock signals is connected respectively to count pulse unit and quantizes on an input end of delay unit after the first unipolarity converting unit, and receiver synchronizing clock signals is connected respectively to count pulse unit and quantizes on another input end of delay unit after the second unipolarity converting unit; The output terminal of constant-temperature crystal oscillator is connected with the input end of phase-locked loop circuit, and the output terminal of phase-locked loop circuit is connection count pulse unit and the another input end that quantizes delay unit respectively; The output terminal of count pulse unit is connected to an input end of totalizer, and the output terminal that quantizes delay unit is connected to another input end of totalizer, the output terminal connected storage of totalizer.
5. synchronous clock phase difference measurements system according to claim 4, it is characterized in that: described the first unipolarity converting unit and the second unipolarity converting unit are by conducting diode D1, D2, optocoupler Opt1, Opt2, Sheffer stroke gate NAND1, NAND2, XOR gate XOR1, pull-up resistor R2, R3, R5, R6, and filter capacitor C1, C2 form; The positive pole of ambipolar transmitter or receiver synchronizing clock signals is divided into 2 tunnels, and a road connects the input anode of optocoupler Opt1 through conducting diode D1, and another road connects the input cathode of optocoupler Opt2; The negative pole of synchronizing clock signals is divided into 2 tunnels, and a road connects the input anode of optocoupler Opt2 through conducting diode D2, and another road connects the input cathode of optocoupler Opt1; The output head anode of optocoupler Opt1 connects 2 input ends of Sheffer stroke gate NAND1 simultaneously, and the negative pole of output end of optocoupler Opt1 connects ground connection GND; 2 input ends of Sheffer stroke gate NAND1 connect positive source VCC through pull-up resistor R2, and the output terminal of Sheffer stroke gate NAND1 connects positive source VCC through pull-up resistor R3, and the output terminal of Sheffer stroke gate NAND1 is through filter capacitor C1 ground connection GND; The output terminal of Sheffer stroke gate NAND1 connects one end of XOR gate XOR1; The output head anode of optocoupler Opt2 connects 2 input ends of Sheffer stroke gate NAND2 simultaneously, and the negative pole of output end of optocoupler Opt2 connects ground connection GND; 2 input ends of Sheffer stroke gate NAND2 connect positive source VCC through pull-up resistor R5, and the output terminal of Sheffer stroke gate NAND2 connects positive source VCC through pull-up resistor R6, and the output terminal of Sheffer stroke gate NAND2 is through filter capacitor C2 ground connection GND; The output terminal of Sheffer stroke gate NAND2 connects one end of XOR gate XOR2.
6. synchronous clock phase difference measurements system according to claim 4, is characterized in that: described quantification delay unit is comprised of a plurality of chronotrons.
7. synchronous clock phase difference measurements system according to claim 4, is characterized in that: on the output terminal of described storer, be also connected to a display.
8. synchronous clock phase difference measurements system according to claim 4, is characterized in that: the output terminal of described storer is also connected with a host computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410369321.9A CN104111481B (en) | 2014-07-30 | 2014-07-30 | Synchronous clock phase difference measurements system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410369321.9A CN104111481B (en) | 2014-07-30 | 2014-07-30 | Synchronous clock phase difference measurements system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104111481A true CN104111481A (en) | 2014-10-22 |
| CN104111481B CN104111481B (en) | 2016-09-28 |
Family
ID=51708336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410369321.9A Active CN104111481B (en) | 2014-07-30 | 2014-07-30 | Synchronous clock phase difference measurements system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104111481B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106169949A (en) * | 2016-08-22 | 2016-11-30 | 江苏理工学院 | A kind of baseband signal bit synchronization clock wideband extracted in self-adaptive device and method |
| CN106443184A (en) * | 2016-11-23 | 2017-02-22 | 优利德科技(中国)有限公司 | Phase detection device and phase detection method |
| CN108206720A (en) * | 2016-12-16 | 2018-06-26 | 联芯科技有限公司 | The method of adjustment of terminal and its slow clock frequency deviation |
| CN111756357A (en) * | 2020-06-16 | 2020-10-09 | 武汉光迅科技股份有限公司 | Periodic signal parameter determination method and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288541B1 (en) * | 1999-08-23 | 2001-09-11 | General Electric Company | MRI measurement of blood vessel wall compliance |
| CN101672931A (en) * | 2009-09-24 | 2010-03-17 | 重庆大学 | Unipolar trapezoidal pulse current control method and device of inductive load |
| WO2011142289A1 (en) * | 2010-05-10 | 2011-11-17 | 株式会社 日立メディコ | Magnetic resonance imaging device |
-
2014
- 2014-07-30 CN CN201410369321.9A patent/CN104111481B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288541B1 (en) * | 1999-08-23 | 2001-09-11 | General Electric Company | MRI measurement of blood vessel wall compliance |
| CN101672931A (en) * | 2009-09-24 | 2010-03-17 | 重庆大学 | Unipolar trapezoidal pulse current control method and device of inductive load |
| WO2011142289A1 (en) * | 2010-05-10 | 2011-11-17 | 株式会社 日立メディコ | Magnetic resonance imaging device |
Non-Patent Citations (2)
| Title |
|---|
| 张法全 等: "基于FPGA的高精度同步测量系统", 《仪表技术与传感器》 * |
| 邹进波: "基于FPGA的精密时间间隔测量研究与实现", 《中国优秀硕士学位论文全文数据库（信息科技辑）》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106169949A (en) * | 2016-08-22 | 2016-11-30 | 江苏理工学院 | A kind of baseband signal bit synchronization clock wideband extracted in self-adaptive device and method |
| CN106169949B (en) * | 2016-08-22 | 2023-04-25 | 江苏理工学院 | Baseband signal bit synchronous clock broadband self-adaptive extraction device and method |
| CN106443184A (en) * | 2016-11-23 | 2017-02-22 | 优利德科技(中国)有限公司 | Phase detection device and phase detection method |
| CN106443184B (en) * | 2016-11-23 | 2023-07-14 | 优利德科技(中国)股份有限公司 | Phase detection device and phase detection method |
| CN108206720A (en) * | 2016-12-16 | 2018-06-26 | 联芯科技有限公司 | The method of adjustment of terminal and its slow clock frequency deviation |
| CN108206720B (en) * | 2016-12-16 | 2019-07-05 | 辰芯科技有限公司 | The method of adjustment of terminal and its slow clock frequency deviation |
| CN111756357A (en) * | 2020-06-16 | 2020-10-09 | 武汉光迅科技股份有限公司 | Periodic signal parameter determination method and electronic equipment |
| CN111756357B (en) * | 2020-06-16 | 2024-04-02 | 武汉光迅科技股份有限公司 | Parameter determination method of periodic signal and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104111481B (en) | 2016-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102313587B (en) | Distance measuring equipment and calibration steps thereof | |
| CN103197145B (en) | Method and system of ultrahigh resolution phase difference measurement | |
| CN104121956B (en) | Time difference measuring method of time difference type ultrasonic flow meter | |
| CN104111481A (en) | Synchronous clock phase difference measuring system and method | |
| CN102116798A (en) | Power grid frequency measurement method and device | |
| CN102749107A (en) | High-precision time difference type single-pulse ultrasonic flowmeter system and flow measurement method thereof | |
| CN106885998B (en) | Method and circuit for improving frequency measurement precision and speed of cesium optical pump magnetic resonance signals | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN101813725A (en) | Method for measuring phase difference of low-frequency signals | |
| CN202563087U (en) | Laser ranging instrument | |
| CN105182069A (en) | High resolution group quantization phase processing method under pilot frequency architecture | |
| CN103176045A (en) | Method and system for pilot frequency bi-phase coincidence detection based on coincidence pulse counting | |
| CN102155905B (en) | Device and method for nondestructive measurement of anchor rod length | |
| CN101866165B (en) | Echoed flight time measuring method based on field programmable gate array | |
| CN102193029B (en) | Method for measuring short-term frequency stability of unconventional sampling time | |
| CN108061885B (en) | Implementation method of multi-channel laser fuse target feature identification signal processing circuit | |
| CN204028377U (en) | Synchronous clock phase difference measurements system | |
| CN103412474B (en) | Range high-precision expanded circuit when TDC-GP2 based on FPGA surveys | |
| CN102928666B (en) | Digital measurement method for phase difference of alternating current | |
| CN109633243B (en) | Beam signal peak amplitude accurate extraction method based on multiphase sampling | |
| CN201107355Y (en) | Time synchronization error measuring circuit based on CPLD technology | |
| CN203502749U (en) | Pulse time interval measuring device | |
| CN102914699B (en) | Modulation domain measurement system and method thereof | |
| CN103529687B (en) | Pulse interval measuring device | |
| CN201323567Y (en) | High precision GPS clock used in detection station of time difference between thunder and lightening |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200902 Address after: No.16, Luoyuan Road, Liuzhou City, Guangxi Zhuang Autonomous Region Patentee after: LIUZHOU YUANCHUANG EFI TECHNOLOGY Co.,Ltd. Address before: 541004 1 Jinji Road, Guilin, the Guangxi Zhuang Autonomous Region Patentee before: GUILIN University OF ELECTRONIC TECHNOLOGY |
|
| TR01 | Transfer of patent right |