CN104111481B - Synchronous clock phase difference measurements system and method - Google Patents
Synchronous clock phase difference measurements system and method Download PDFInfo
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- CN104111481B CN104111481B CN201410369321.9A CN201410369321A CN104111481B CN 104111481 B CN104111481 B CN 104111481B CN 201410369321 A CN201410369321 A CN 201410369321A CN 104111481 B CN104111481 B CN 104111481B
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Abstract
The open a kind of synchronous clock phase difference measurements system and method for the present invention, its unipolarity converting unit synchronizing signal to transmitter and receiver respectively carries out bipolarity to unipolar conversion, above-mentioned two is under the control of same constant-temperature crystal oscillator, being simultaneously fed in pulse count unit the phase contrast to both to carry out the phase contrast that bigness scale amount and being simultaneously fed into quantifies in delay unit both and carry out accurate measurement amount, both sums are the phase contrast of synchronizing clock signals.The present invention can measure colliery accurately and visit the phase contrast of synchronizing clock signals between the transmitter and receiver that submarine mine reaches, and the raising to the rectification of synchronous clock phase difference with to follow-up Inversion Calculation precision can serve significantly effect.
Description
Technical field
The present invention relates to visit submarine mine and reach technical field, be specifically related to a kind of synchronous clock phase difference measurements system
And method.
Background technology
Transient electromagnetic method measurement apparatus is made up of emission system and reception system two parts.Transmitting coil leads to
With step current I, emission current is dropped to zero by I suddenly, according to electromagnetic coupling theory, transmitting coil
Middle electric current changes suddenly and will be referred to as Primary field, once in the magnetic field producing change about, this magnetic field
In the communication process around of magnetic field, as run into the geologic body of the good conduction in underground, generation will be excited therein
Faradic current, also known as eddy current or secondary current, secondary current changes over, thus is producing the most again
The magnetic field of tissue regeneration promoting, referred to as secondary magnetic field.Due to the thermal losses of the good induced currents of plastid conductively, secondary
Decaying the most in time in magnetic field, forms transient magnetic field, and secondary magnetic field is mainly derived from good leading
The faradic current of electricity geologic body, therefore it comprises the geological information relevant with geologic body, by receiving line
Secondary magnetic field is observed by circle, and the data of observation are analyzed and are processed, to underground geologic bodies
Relevant physical parameter explains.
Owing to the principle of submarine mine Dary transient electromagnetic method is visited in colliery, turn off the wink of emission current at transmitter
Between, receiver collection receive underground medium produce pure secondary field, it is therefore desirable to transmitter and receiver it
Between must with frequency homophase work, could obtain and observe data the most accurately.Reach although submarine mine is visited in colliery
Transmitter and receiver be to produce synchronised clock by the complementary co-ordination of GPS and constant-temperature crystal oscillator
, but the complexity of exploration geology and non-intellectual, the synchronizing clock signals of Receiver And Transmitter is at sky
It is to separate between so that the clock signal of transmitter and receiver is frequently not Complete Synchronization, can produce
Raw inevitable phase contrast, and this phase place extent determine whole system sampling precision and after
The accuracy of continuous inversion algorithm.Although observation personnel can observe transmitter and receiver by oscillograph
Clock signal judge whether clock signal synchronizes, but oscillograph the most simply obtains the observation of short-term
Data, and phase data can not be stored, thus the conclusion obtained is inaccurate.Visible, adopt
The clock signal of transmitter and receiver is observed, when subsequent transmission machine and receiver are synchronized with oscillograph
The rectification of clock has certain limitation.
Summary of the invention
The technical problem to be solved is to provide a kind of synchronous clock phase difference measurements system and side
Method, it can be measured colliery accurately and visit synchronizing clock signals between the transmitter and receiver that submarine mine reaches
Phase contrast, and the rectification of synchronous clock phase difference and the raising to follow-up Inversion Calculation precision can be served
Significantly effect.
For solving the problems referred to above, the present invention is achieved by the following technical solutions:
Synchronous clock phase difference measurements method, comprises the steps:
Step 1, when synchronizing the bipolarity transmitter synchronizing clock signals collected and bipolarity receiver
Clock signal is respectively converted into unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronised clock letter
Number；
Step 2, generates counting pulse signal, this counting after the frequency that constant-temperature crystal oscillator exports carries out frequency multiplication
The cycle of pulse signal is T；
Step 3, carries out bigness scale amount to the phase contrast of transmitter and receiver；I.e.
Step 3.1, at unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals
In, allow the rising edge of the clock cycle signal first arrived as the count start signal in each counting cycle,
The rising edge of the clock cycle signal arrived after then another clock cycle signal is is as each counting cycle
Count end signal；
Step 3.2, calculates complete pulse number N of each counting cycle inside counting pulse signal；
Step 4, carries out accurate measurement amount to the phase contrast of transmitter and receiver；I.e.
Step 4.1, carries out quantifying time delay to the counting pulse signal in each counting cycle, so that each
The rising edge of first complete pulse of the counting pulse signal in counting cycle or trailing edge with first arrive
The rising edge alignment of clock cycle signal, and record each counting cycle counting pulse signal process
Chronotron number n1；
Step 4.2, carries out quantifying time delay to the counting pulse signal in each counting cycle, so that each
The rising edge of last complete pulse of the counting pulse signal in counting cycle or trailing edge and rear arrival
The rising edge alignment of clock cycle signal, and the counting pulse signal recording each counting cycle passed through
Chronotron number n2；Step 4.3, calculates phase difference T of transmitter and receiveri, i.e.
When counting pulse signal is low level when count start signal arrives, when count end signal arrives
During for low level, then phase difference T of transmitter and receiveriFor
When counting pulse signal is low level when count start signal arrives, when count end signal arrives
During for high level, then phase difference T of transmitter and receiveriFor
When counting pulse signal is high level when count start signal arrives, when count end signal arrives
During for low level, then phase difference T of transmitter and receiveriFor
When counting pulse signal is high level when count start signal arrives, when count end signal arrives
During for high level, then phase difference T of transmitter and receiveriFor
ΔTi=NT+ (T-n1t)-(T-n2t) (4)
In formula (1)-(4), N is complete counter pulse number, and T is the cycle of counting pulse signal,
n1During the clock cycle signal alignment being and first arrive, counting pulse signal the chronotron number of process, n2
When being the clock cycle signal alignment with rear arrival, counting pulse signal the chronotron number of process, t is
The delay time of chronotron；
Step 5, phase difference T of transmitter and receiver that will be calculatediStore.
Said method, still further comprises phase difference T to the transmitter and receiver calculatediCarry out
The step of display.
Said method, still further comprises phase difference T to the transmitter and receiver calculatediSend into
Host computer carries out the step of Synchronization Analysis.
The synchronous clock phase difference measurements system designed based on above-mentioned synchronous clock phase difference measurements method,
Mainly by the first unipolarity converting unit, the second unipolarity converting unit, constant-temperature crystal oscillator, phase-locked loop circuit,
Count pulse unit, quantization delay unit, adder and memorizer；Wherein transmitter synchronizing clock signals
After the first unipolarity converting unit, it is connected respectively to count pulse unit and quantifies an input of delay unit
On end, receiver synchronizing clock signals is connected respectively to count pulse list after the second unipolarity converting unit
On another input of unit and quantization delay unit；The outfan of constant-temperature crystal oscillator and the input of phase-locked loop circuit
End is connected, and the outfan of phase-locked loop circuit connection count pulse unit respectively is another with quantization delay unit
Input；The outfan of count pulse unit is connected to an input of adder, quantifies delay unit
Outfan is connected to another input of adder, and the outfan of adder connects memorizer.
In said system, described first unipolarity converting unit and the second unipolarity converting unit are by conducting
Diode D1, D2, optocoupler Opt1, Opt2, NAND gate NAND1, NAND2, XOR gate XOR1, on
Pull-up resistor R2, R3, R5, R6, and filter capacitor C1, C2 composition；Ambipolar transmitter or connect
The positive pole of receipts machine synchronizing clock signals is divided into 2 tunnels, and a road connects optocoupler Opt1's through conducting diode D1
Input anode, another road connects the input cathode of optocoupler Opt2；The negative pole of synchronizing clock signals is divided into
2 tunnels, a road connects the input anode of optocoupler Opt2 through conducting diode D2, and another road connects optocoupler
The input cathode of Opt1；The output head anode of optocoupler Opt1 is simultaneously connected with 2 of NAND gate NAND1
Input, the negative pole of output end of optocoupler Opt1 connects ground connection GND；2 inputs of NAND gate NAND1
Connecting positive source VCC through pull-up resistor R2, the outfan of NAND gate NAND1 is through pull-up resistor R3 even
Meet positive source VCC, the outfan filtered electric capacity C1 ground connection GND of NAND gate NAND1；NAND gate NAND1
Outfan connect XOR gate XOR1 one end；The output head anode of optocoupler Opt2 is simultaneously connected with NAND gate
2 inputs of NAND2, the negative pole of output end of optocoupler Opt2 connects ground connection GND；NAND gate NAND2
2 inputs through pull-up resistor R5 connect positive source VCC, the outfan of NAND gate NAND2 is through upper
Pull-up resistor R6 connects positive source VCC, the outfan filtered electric capacity C2 ground connection GND of NAND gate NAND2；
The outfan of NAND gate NAND2 connects one end of XOR gate XOR2.
In said system, described quantization delay unit is made up of multiple chronotron.
In said system, the outfan of described memorizer is further connected with a display.
In said system, the outfan of described memorizer is also connected with a host computer.
The principle of the present invention is: the synchronizing signal of transmitter and receiver is entered by unipolarity converting unit respectively
Row bipolarity, is simultaneously fed into unipolar conversion, above-mentioned two under the control of same constant-temperature crystal oscillator
In pulse count unit phase contrast to both carry out bigness scale amount and be simultaneously fed in quantization delay unit right
Both phase contrasts carry out accurate measurement amount, bigness scale amount and accurate measurement amount sum and are the phase contrast of synchronizing clock signals.
Compared with prior art, the present invention has a characteristic that
1, high-resolution and high stability, compared with traditional oscillograph, highest resolution can reach
200ps, and the phase contrast of synchronizing clock signals can be measured for a long time, and to phase place difference
According to carrying out storing and showing on LCD；
2, convenient, low-power consumption, compared with traditional oscillograph, this synchronised clock measure system more convenient,
Low-power consumption, if only needing dry cell power supply, and in the case of can there is no mains-supplied in the wild, can
To work for a long time；
3, easy realization, low cost, use d type flip flop, chronotron and the count pulse within FPGA,
Bipolarity change-over circuit, Liquid Crystal Module and memory module just can realize.
Accompanying drawing explanation
Fig. 1 is a kind of synchronous clock phase difference measurements system block diagram.
Fig. 2 is unipolarity converting unit schematic diagram.
Fig. 3 is a kind of synchronous clock phase difference measurements method flow diagram.
Fig. 4 is unipolarity converting unit waveform.
Fig. 5 is pulse counting method schematic diagram.
Fig. 6 is for quantifying time expander method schematic diagram.
Detailed description of the invention
A kind of synchronous clock phase difference measurements system, as it is shown in figure 1, mainly single by the first unipolarity conversion
Unit, the second unipolarity converting unit, constant-temperature crystal oscillator, phase-locked loop circuit, count pulse unit, quantization are prolonged
Shi Danyuan, adder and memorizer.Wherein transmitter synchronizing clock signals is through the first unipolarity converting unit
After be connected respectively to count pulse unit and quantify delay unit an input on, receiver synchronised clock
Signal is connected respectively to count pulse unit after the second unipolarity converting unit and quantifies the another of delay unit
On one input.The outfan of constant-temperature crystal oscillator is connected with the input of phase-locked loop circuit, phase-locked loop circuit
Outfan connection count pulse unit respectively and the another input of quantization delay unit.Count pulse unit
Outfan be connected to an input of adder, the outfan quantifying delay unit is connected to adder
Another input, the outfan of adder connects memorizer.Additionally, in order to measurement result is carried out
Display directly perceived, the outfan of described memorizer is further connected with a display.And in order to gained is measured
Result is further processed and analyzes, and the outfan of described memorizer is also connected with a host computer.
First unipolarity converting unit is identical with the structure of the second unipolarity converting unit, such as Fig. 2 institute
Show, by conducting diode D1, D2, optocoupler Opt1, Opt2, NAND gate NAND1, NAND2, different
Or door XOR1, pull-up resistor R2, R3, R5, R6, and filter capacitor C1, C2 composition.Such as Fig. 2
Shown in.The positive pole of ambipolar transmitter or receiver synchronizing clock signals is divided into 2 tunnels, and a road is through conducting
Diode D1 connects the input anode of optocoupler Opt1, and another road connects the input cathode of optocoupler Opt2.
The negative pole of synchronizing clock signals is divided into 2 tunnels, and a road connects the input of optocoupler Opt2 through conducting diode D2
Rectifying pole, another road connects the input cathode of optocoupler Opt1.The output head anode of optocoupler Opt1 is simultaneously
Connecting 2 inputs of NAND gate NAND1, the negative pole of output end of optocoupler Opt1 connects ground connection GND.With
2 inputs of not gate NAND1 connect positive source VCC through pull-up resistor R2, NAND gate NAND1
Outfan connects positive source VCC, the filtered electric capacity of outfan of NAND gate NAND1 through pull-up resistor R3
C1 ground connection GND.The outfan of NAND gate NAND1 connects one end of XOR gate XOR1.Optocoupler Opt2's
Output head anode is simultaneously connected with 2 inputs of NAND gate NAND2, and the negative pole of output end of optocoupler Opt2 is even
Ground connection GND.2 inputs of NAND gate NAND2 connect positive source VCC through pull-up resistor R5,
The outfan of NAND gate NAND2 connects positive source VCC, NAND gate NAND2 defeated through pull-up resistor R6
Go out to hold filtered electric capacity C2 ground connection GND.The outfan of NAND gate NAND2 connects the one of XOR gate XOR2
End.
Quantify delay unit to be made up of multiple chronotron.In a preferred embodiment of the invention, select 4 grades to prolong
Time device as example calculations T1.Counting pulse signal is defeated as the signal of d type flip flop through internal delay time device
Entering, OUTA signal inputs as the clock of d type flip flop, and d type flip flop turns in rising edge clock generation state
Changing, output signal is equal to input signal.In chronotron chain, the delay time of each chronotron is t=200ps
Left and right, the most often through a chronotron, count pulse can time delay 200ps relative to OUTA signal.Logical
Cross the coding to d type flip flop, just can know that the part that do not lines up of count pulse is low level or high level.
When count pulse and OUTA signal do not line up part be low level time, in chronotron chain before n1-1 chronotron
Being low level, the n-th 1 chronotron are high level, then explanation count pulse is after n1 chronotron,
The trailing edge of count pulse and the rising edge alignment of OUTA, then time T1=n1t.As count pulse and OUTA
Signal does not lines up part when being high level, in chronotron chain before n1-1 chronotron be high level, the n-th 1
Chronotron is low level, then explanation count pulse after n1 chronotron, the rising edge of count pulse and
The rising edge alignment of OUTA, then time T1=n1t.In like manner can be in the hope of T2.
A kind of synchronous clock phase difference measurements method, as it is shown on figure 3, comprise the steps:
Step 1, when synchronizing the bipolarity transmitter synchronizing clock signals collected and bipolarity receiver
Clock signal is respectively converted into unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronised clock letter
Number.
Owing to transmitter synchronizing clock signals A and receiver synchronizing clock signals B is ambipolar, and FPGA
Negative level cannot be processed, it is therefore desirable to unipolarity converting unit.The waveform of unipolarity converting unit such as Fig. 4
Shown in.As a example by synchronizing clock signals A.When INA+ is positive voltage, and INA-is negative voltage, then optocoupler
Opt1 turns on, and optocoupler Opt2 ends, and NAND gate NAND1 output high level, NAND gate NAND2 exports
Low level, exports high level after XOR gate XOR1.In like manner: when INA+ is negative voltage, and INA-is
During positive voltage, optocoupler Opt1 ends, and optocoupler Opt2 turns on, NAND gate NAND1 output low level, with
Not gate NAND2 exports high level, exports high level after XOR gate XOR1, oscillogram such as Fig. 3 institute
Show.Synchronizing clock signals has twice zero sudden change within each cycle, this twice Catastrophe control transmitter
Launch pulse and the signal sampling pulse of receiver, it is therefore desirable to measure the phase contrast of this twice sudden change.
Step 2, generates counting pulse signal, this counting after the frequency that constant-temperature crystal oscillator exports carries out frequency multiplication
The cycle of pulse signal is T.
The synchronizing frequency of bipolar signal is 6.25Hz, and the frequency being converted into unipolar signal is 12.5Hz.
Owing to unipolarity converting unit is full symmetric, the delay time error therefore caused synchronizing clock signals can
To ignore.Constant-temperature crystal oscillator output frequency is stable, and degree of stability is fine in a short time, and not by extraneous temperature
Degree impact, provides accurate clock for FPGA.FPGA calls the phaselocked loop (PLL) in IP kernel, by perseverance
The 10MHz frequency frequency multiplication of temperature crystal oscillator output, to 100MHz, so can be effectively reduced counting error, by mistake
Difference is 10ns.Phase difference measurement module carries out phase contrast accurate measurement to synchronizing clock signals A, B, bag
Including bigness scale amount and accurate measurement amount, be slightly measured as pulse counting method, essence is measured as quantifying time expander method, both sums
It is the phase contrast of synchronizing clock signals.
Step 3, carries out bigness scale amount to the phase contrast of transmitter and receiver.I.e.
Step 3.1, at unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronizing clock signals
In, the rising edge of the clock cycle signal first arrived is as the count start signal in each counting cycle, then
The rising edge of the clock cycle signal that another clock cycle signal arrives after being is as each counting cycle
Count end signal.
Step 3.2, calculates complete pulse number N of each counting cycle inside counting pulse signal.
Pulse counting method is as it is shown in figure 5, the rising edge of OUTA is as rolling counters forward commencing signal, OUTB
Rising edge be bigness scale as rolling counters forward end signal, count pulse cycle T=10ns, count results
Amount.T1 is the part that count pulse does not lines up with OUTA, and T2 is the portion that count pulse does not lines up with OUTB
Point, measurement result is accurate measurement amount, and accurate measurement amount is by the internal hardware chronotron lcell of FPGA and D-latch
Realize, quantify time expander method as shown in Figure 6.
Step 4, carries out accurate measurement amount to the phase contrast of transmitter and receiver.I.e.
Step 4.1, carries out quantifying time delay to the counting pulse signal in each counting cycle, so that each
The rising edge of first complete pulse of the counting pulse signal in counting cycle or trailing edge with first arrive
The rising edge alignment of clock cycle signal, and record each counting cycle counting pulse signal process
Chronotron number n1。
Step 4.2, carries out quantifying time delay to the counting pulse signal in each counting cycle, so that each
The rising edge of last complete pulse of the counting pulse signal in counting cycle or trailing edge and rear arrival
The rising edge alignment of clock cycle signal, and the counting pulse signal recording each counting cycle passed through
Chronotron number n2。
Step 4.3, calculates phase difference T of transmitter and receiveri, i.e.
When counting pulse signal is low level when count start signal arrives, when count end signal arrives
During for low level, then phase difference T of transmitter and receiveriFor
When counting pulse signal is low level when count start signal arrives, when count end signal arrives
During for high level, then phase difference T of transmitter and receiveriFor
When counting pulse signal is high level when count start signal arrives, when count end signal arrives
During for low level, then phase difference T of transmitter and receiveriFor
When counting pulse signal is high level when count start signal arrives, when count end signal arrives
During for high level, then phase difference T of transmitter and receiveriFor
ΔTi=NT+ (T-n1t)-(T-n2t) (4)
In formula (1)-(4), N is complete counter pulse number, and T is the cycle of counting pulse signal,
n1During the clock cycle signal alignment being and first arrive, counting pulse signal the chronotron number of process, n2
When being the clock cycle signal alignment with rear arrival, counting pulse signal the chronotron number of process, t is
The delay time of chronotron.
In Fig. 6, select 4 grades of chronotron as example calculations T1.Counting pulse signal is through internal delay time
Device inputs as the signal of d type flip flop, and OUTA signal inputs as the clock of d type flip flop, d type flip flop
At rising edge clock generation State Transferring, output signal is equal to input signal.In chronotron chain, each
The delay time of chronotron is about t=200ps, and the most often through a chronotron, count pulse is relative
Can time delay 200ps in OUTA signal.By the coding to d type flip flop, just can know that count pulse not
Aligned portions is low level or high level.It is low level when count pulse and OUTA signal do not line up part
Time, in chronotron chain before n1-1 chronotron be low level, the n-th 1 chronotron are high level, then illustrate
Count pulse after n1 chronotron, the trailing edge of count pulse and the rising edge alignment of OUTA, then
Time T1=n1t.When count pulse and OUTA signal do not line up part be high level time, in chronotron chain
Front n1-1 chronotron is high level, and the n-th 1 chronotron are low levels, then explanation count pulse is through n1
After individual chronotron, the rising edge of count pulse and the rising edge alignment of OUTA, then time T1=n1t.With
Reason can be in the hope of T2.
Step 5, phase difference T of transmitter and receiver that will be calculatediStore and show, with
Time it is also possible that phase difference T of the transmitter and receiver calculatediSend into host computer to carry out synchronizing to divide
The step of analysis.
Claims (9)
1. synchronous clock phase difference measurements method, is characterized in that comprising the steps:
Step 1, synchronizes the bipolarity transmitter synchronizing clock signals collected and bipolarity receiver
When clock signal is respectively converted into unipolarity transmitter synchronizing clock signals and the synchronization of unipolarity receiver
Clock signal；
Step 2, generates counting pulse signal, this meter after the frequency that constant-temperature crystal oscillator exports carries out frequency multiplication
The cycle of number pulse signal is T；
Step 3, carries out bigness scale amount to the phase contrast of transmitter and receiver；I.e.
Step 3.1, believes at unipolarity transmitter synchronizing clock signals and unipolarity receiver synchronised clock
In number, the rising edge of the clock cycle signal first arrived is allowed to start letter as the counting in each counting cycle
Number, then the rising edge of the clock cycle signal arrived after another clock cycle signal is is as each meter
The count end signal of one number time；
Step 3.2, calculates complete pulse number N of each counting cycle inside counting pulse signal；
Step 4, carries out accurate measurement amount to the phase contrast of transmitter and receiver；I.e.
Step 4.1, carries out quantifying time delay to the counting pulse signal in each counting cycle, so that often
The rising edge of first complete pulse of the counting pulse signal in individual counting cycle or trailing edge and elder generation
The rising edge alignment of the clock cycle signal arrived, and record the counting pulse signal in each counting cycle
Chronotron number n of process1；
Step 4.2, carries out quantifying time delay to the counting pulse signal in each counting cycle, so that often
The rising edge of last complete pulse of the counting pulse signal in individual counting cycle or trailing edge with
The rising edge alignment of the clock cycle signal of rear arrival, and record the count pulse letter in each counting cycle
Number chronotron number n of process2；
Step 4.3, calculates the phase contrast △ T of transmitter and receiveri, i.e.
When counting pulse signal is low level when count start signal arrives, count end signal arrives
Time when being low level, then the phase contrast △ T of transmitter and receiveriFor
When counting pulse signal is low level when count start signal arrives, count end signal arrives
Time when being high level, then the phase contrast △ T of transmitter and receiveriFor
When counting pulse signal is high level when count start signal arrives, count end signal arrives
Time when being low level, then the phase contrast △ T of transmitter and receiveriFor
When counting pulse signal is high level when count start signal arrives, count end signal arrives
Time when being high level, then the phase contrast △ T of transmitter and receiveriFor
△Ti=NT+ (T-n1t)-(T-n2t) (4)
In formula (1)-(4), N is complete counter pulse number, and T is the week of counting pulse signal
Phase, n1During the clock cycle signal alignment being and first arrive, counting pulse signal the chronotron of process
Number, n2When being the clock cycle signal alignment with rear arrival, counting pulse signal the time delay of process
Device number, t is the delay time of chronotron；
Step 5, the phase contrast △ T of transmitter and receiver that will be calculatediStore.
Synchronous clock phase difference measurements method the most according to claim 1, is characterized in that: also
Farther include the phase contrast △ T to the transmitter and receiver calculatediCarry out the step shown.
Synchronous clock phase difference measurements method the most according to claim 1 and 2, is characterized in that:
Still further comprise the phase contrast △ T to the transmitter and receiver calculatediFeeding host computer is carried out
The step of Synchronization Analysis.
4. the synchronised clock designed based on synchronous clock phase difference measurements method described in claim 1
Phase Difference Measuring System, it is characterised in that: include that the first unipolarity converting unit, the second unipolarity turn
Change unit, constant-temperature crystal oscillator, phase-locked loop circuit, count pulse unit, quantify delay unit, adder
And memorizer；Wherein transmitter synchronizing clock signals is connected respectively to after the first unipolarity converting unit
On one input of count pulse unit and quantization delay unit, receiver synchronizing clock signals is through second
It is connected respectively to count pulse unit after unipolarity converting unit and quantifies another input of delay unit
On end；The outfan of constant-temperature crystal oscillator is connected with the input of phase-locked loop circuit, the output of phase-locked loop circuit
End connection count pulse unit respectively and the another input of quantization delay unit；Count pulse unit
Outfan is connected to an input of adder, and the outfan quantifying delay unit is connected to adder
Another input, the outfan of adder connects memorizer.
Synchronous clock phase difference measurements system the most according to claim 4, it is characterised in that:
Described first unipolarity converting unit is by conducting diode D1, D2, and optocoupler Opt1, Opt2, with non-
Door NAND1, NAND2, XOR gate XOR1, pull-up resistor R2, R3, R5, R6, and filtered electrical
Hold C1, C2 composition；The positive pole of ambipolar transmitter synchronizing clock signals is divided into 2 tunnels, a road warp
Conducting diode D1 connects the input anode of optocoupler Opt1, and another road connects the defeated of optocoupler Opt2
Enter to hold negative pole；The negative pole of synchronizing clock signals is divided into 2 tunnels, and a road connects light through conducting diode D2
The input anode of coupling Opt2, another road connects the input cathode of optocoupler Opt1；Optocoupler Opt1
Output head anode be simultaneously connected with 2 inputs of NAND gate NAND1, the outfan of optocoupler Opt1
Negative pole connects ground connection GND；2 inputs of NAND gate NAND1 are just connecting power supply through pull-up resistor R2
Pole VCC, the outfan of NAND gate NAND1 connects positive source VCC, NAND gate through pull-up resistor R3
The outfan filtered electric capacity C1 ground connection GND of NAND1；The outfan of NAND gate NAND1 connects XOR
One end of door XOR1；The output head anode of optocoupler Opt2 be simultaneously connected with NAND gate NAND2 2 are defeated
Entering end, the negative pole of output end of optocoupler Opt2 connects ground connection GND；2 inputs of NAND gate NAND2
Connecting positive source VCC through pull-up resistor R5, the outfan of NAND gate NAND2 is through pull-up resistor R6
Connect positive source VCC, the outfan filtered electric capacity C2 ground connection GND of NAND gate NAND2；With non-
The outfan of door NAND2 connects one end of XOR gate XOR2.
Synchronous clock phase difference measurements system the most according to claim 4, it is characterised in that:
Described second unipolarity converting unit by conducting diode D1, D2, optocoupler Opt1, Opt2, with
Not gate NAND1, NAND2, XOR gate XOR1, pull-up resistor R2, R3, R5, R6, and filtering
Electric capacity C1, C2 form；The positive pole of ambipolar receiver synchronizing clock signals is divided into 2 tunnels, a road
Connect the input anode of optocoupler Opt1 through conducting diode D1, another road connects optocoupler Opt2's
Input cathode；The negative pole of synchronizing clock signals is divided into 2 tunnels, and a road connects through conducting diode D2
The input anode of optocoupler Opt2, another road connects the input cathode of optocoupler Opt1；Optocoupler Opt1
Output head anode be simultaneously connected with 2 inputs of NAND gate NAND1, the outfan of optocoupler Opt1
Negative pole connects ground connection GND；2 inputs of NAND gate NAND1 are just connecting power supply through pull-up resistor R2
Pole VCC, the outfan of NAND gate NAND1 connects positive source VCC, NAND gate through pull-up resistor R3
The outfan filtered electric capacity C1 ground connection GND of NAND1；The outfan of NAND gate NAND1 connects XOR
One end of door XOR1；The output head anode of optocoupler Opt2 be simultaneously connected with NAND gate NAND2 2 are defeated
Entering end, the negative pole of output end of optocoupler Opt2 connects ground connection GND；2 inputs of NAND gate NAND2
Connecting positive source VCC through pull-up resistor R5, the outfan of NAND gate NAND2 is through pull-up resistor R6
Connect positive source VCC, the outfan filtered electric capacity C2 ground connection GND of NAND gate NAND2；With non-
The outfan of door NAND2 connects one end of XOR gate XOR2.
Synchronous clock phase difference measurements system the most according to claim 4, it is characterised in that:
Described quantization delay unit is made up of multiple chronotron.
Synchronous clock phase difference measurements system the most according to claim 4, it is characterised in that:
A display it is further connected with on the outfan of described memorizer.
Synchronous clock phase difference measurements system the most according to claim 4, it is characterised in that:
The outfan of described memorizer is also connected with a host computer.
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| CN108206720B (en) * | 2016-12-16 | 2019-07-05 | 辰芯科技有限公司 | The method of adjustment of terminal and its slow clock frequency deviation |
| CN111756357B (en) * | 2020-06-16 | 2024-04-02 | 武汉光迅科技股份有限公司 | Parameter determination method of periodic signal and electronic equipment |
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