CN111756357B - Parameter determination method of periodic signal and electronic equipment - Google Patents
Parameter determination method of periodic signal and electronic equipment Download PDFInfo
- Publication number
- CN111756357B CN111756357B CN202010550254.6A CN202010550254A CN111756357B CN 111756357 B CN111756357 B CN 111756357B CN 202010550254 A CN202010550254 A CN 202010550254A CN 111756357 B CN111756357 B CN 111756357B
- Authority
- CN
- China
- Prior art keywords
- clock signal
- signal
- module
- delay
- external periodic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000737 periodic effect Effects 0.000 title claims abstract description 176
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000005259 measurement Methods 0.000 claims abstract description 36
- 238000006243 chemical reaction Methods 0.000 claims description 25
- 230000001934 delay Effects 0.000 claims description 14
- 238000005070 sampling Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 13
- 230000002093 peripheral effect Effects 0.000 description 9
- 230000003111 delayed effect Effects 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
Abstract
The embodiment of the invention is suitable for the technical field of signal measurement, and provides a parameter determining method of a periodic signal and electronic equipment, wherein the parameter determining method of the periodic signal comprises the following steps: receiving an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the setting precision; under the condition that the setting precision is in a first setting range, respectively inputting an external periodic signal into a delay module and the trigger to obtain an output signal of the trigger; each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to an external periodic signal or a delay signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delay device and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the setting accuracy and the reference clock signal provided by the clock module.
Description
Technical Field
The invention belongs to the field of signal measurement, and particularly relates to a parameter determination method of a periodic signal and electronic equipment.
Background
In the working process of the electronic equipment, the parameter of the periodic signal needs to be measured, and the measurement accuracy of the parameter of the periodic signal can influence the output result of the electronic equipment. For example, in the optical power output control of a pulse laser, the measurement accuracy of the pulse width and pulse period of a pulse signal directly affects the calculation of peak power and average power. At present, related technology needs to increase the measurement accuracy of parameters of periodic signals by adding a peripheral circuit, and the peripheral circuit has complex design and high cost.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method for determining parameters of a periodic signal and an electronic device, so as to at least solve the problem of high cost caused by the fact that the related art increases the peripheral circuit to improve the measurement accuracy of the parameters of the periodic signal.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a method for determining parameters of a periodic signal, where the method is applied to an electronic device, where the electronic device includes a field programmable gate array FPGA module and a clock module, and the FPGA module includes a phase-locked loop, a delay module, and a trigger; the delay module consists of at least two delays which are cascaded in sequence, and is characterized in that the parameter determining method comprises the following steps:
Receiving an external periodic signal;
determining configuration parameters of the phase-locked loop corresponding to the setting precision; the set precision characterizes the measurement precision of the parameters of the external periodic signal;
under the condition that the setting precision is in a first setting range, inputting the external periodic signal into the delay module and the trigger respectively to obtain an output signal of the trigger; each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal characterizes the level state of the external periodic signal;
determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delay device and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module.
In the above scheme, the FPGA module further includes a first serial-parallel conversion interface, and the parameter determining method further includes:
Controlling the phase-locked loop to generate the first clock signal and the second clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the frequencies of the first clock signal and the second clock signal are different;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel interface and the first clock signal;
parameters of the external periodic signal are determined based on the first parallel data and the second clock signal.
In the above scheme, the FPGA module further includes a second serial-parallel conversion interface, and the parameter determining method further includes:
controlling the phase-locked loop to generate the first clock signal and the third clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the frequencies of the first clock signal and the third clock signal are different;
Sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel interface and the first clock signal;
a parameter of the external periodic signal is determined based on the second parallel data and the third clock signal.
In the above solution, the parameters of the external periodic signal at least include any one of the following:
the period of the external periodic signal;
the pulse width of the external periodic signal.
In the above solution, when determining the configuration parameters of the phase-locked loop based on the setting accuracy, the parameter determining method further includes:
controlling the phase-locked loop to generate the first clock signal based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module;
the number of delays in the delay module is determined based on the frequency of the first clock signal.
In the above scheme, the parameter determining method further includes:
determining the current temperature of the FPGA module;
and determining the delay time corresponding to the delay module based on the current temperature.
In a second aspect, an embodiment of the present invention provides an electronic device, including:
A clock module for providing a reference clock signal;
the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module consists of at least two delays which are cascaded front and back; the FPGA module is used for: acquiring an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the setting precision; the set precision characterizes the measurement precision of the parameters of the external periodic signal; under the condition that the setting precision is in a first setting range, inputting the external periodic signal into the delay module and the trigger respectively to obtain an output signal of the trigger; each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal characterizes the level state of the external periodic signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delay device and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module.
In the above scheme, the FPGA module further includes a first serial-parallel conversion interface, and when the setting precision is located in the second setting range, the FPGA module is further configured to:
controlling the phase-locked loop to generate the first clock signal and the second clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal are different in frequency;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel interface and the first clock signal;
parameters of the external periodic signal are determined based on the first parallel data and the second clock signal.
In the above scheme, the FPGA module further includes a second serial-parallel conversion interface, and when the setting precision is in a third setting range, the FPGA module is further configured to:
controlling the phase-locked loop to generate the first clock signal and the third clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal are different in frequency;
Sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel interface and the first clock signal;
a parameter of the external periodic signal is determined based on the second parallel data and the third clock signal.
In the embodiment of the invention, the electronic equipment receives the external periodic signal and determines the configuration parameters of the phase-locked loop corresponding to the setting precision. The electronic equipment comprises a clock module and an FPGA module, wherein a phase-locked loop in the FPGA module generates a first clock signal based on configuration parameters corresponding to setting precision and a reference clock signal provided by the clock module. Under the condition that the setting precision is in a first setting range, respectively inputting external periodic signals into a delay module and a trigger in the FPGA module to obtain output signals of the trigger; each stage of delayer in the delay module respectively sends delay signals to the next stage of delayer and the trigger; the flip-flop generates an output signal according to an external periodic signal or a delayed signal. Finally, the electronic device determines a parameter of the external periodic signal based on the output signal, the corresponding delay time of the delay device, and the first clock signal. According to the embodiment of the invention, on the premise of not increasing a peripheral circuit, the internal resource of the FPGA module is directly utilized to improve the measurement accuracy of the parameters of the external periodic signal.
Drawings
Fig. 1 is a schematic structural diagram of a pulse laser according to an embodiment of the present invention;
fig. 2 is a schematic implementation flow chart of a method for determining parameters of a periodic signal according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart of another method for determining parameters of periodic signals according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another electronic device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram showing the relationship among an external periodic signal, a first clock signal and a delayed signal according to an embodiment of the present invention;
FIG. 7 is a schematic flow chart of another method for determining parameters of a periodic signal according to an embodiment of the present invention;
FIG. 8 is a schematic flow chart of another method for determining parameters of a periodic signal according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of converting serial signals into parallel signals according to an embodiment of the present invention;
FIG. 10 is a schematic flow chart of another method for determining parameters of a periodic signal according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
Fig. 12 is a schematic structural diagram of another electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision.
In addition, in the embodiments of the present invention, "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pulse laser according to an embodiment of the present invention, where the pulse laser includes: the device comprises a parameter measuring device, a feedback control device, a photoelectric conversion device, a driving circuit, a coupler and a laser.
As shown in fig. 1, the optical pulse signal output by the laser is divided into two paths by the coupler, one path of optical pulse signal is used as pure output, and the other path of optical pulse signal is input into the photoelectric conversion device. The photoelectric conversion device performs photoelectric conversion on the optical pulse signal to obtain an electric pulse signal, the photoelectric conversion device inputs the electric pulse signal into the parameter measurement device, and the parameter measurement device performs parameter measurement on the electric pulse signal to obtain parameters such as a period and a pulse width of the electric pulse signal. The parameter measuring device inputs the measured parameters into the feedback control device, the feedback control device calculates peak power and average power in real time according to the pulse capacity of the electric pulse signal measured by the photoelectric conversion device and the parameters of the electric pulse signal, and the output current of the driving circuit is adjusted in real time according to the peak power and the average power, so that the waveform and the size of the optical pulse output by the laser are controlled. Where peak power = pulse energy/pulse width, average power = pulse energy/pulse period. It can be seen that the measurement accuracy of the pulse width and the pulse period of the pulse signal directly affects the calculation of the peak power and the average power, and the higher the measurement accuracy of the pulse width and the pulse period of the pulse signal is, the more accurate the calculation of the peak power and the average power is, and the more accurate the output control of the optical pulse is.
At present, the related art improves the measurement accuracy of the parameter of the periodic signal by adding a peripheral circuit, and the peripheral circuit has complex design and higher cost. In some electronic devices, parameters of multiple periodic signals need to be measured simultaneously, and different requirements on measurement accuracy of different periodic signals are met, and peripheral circuits can only provide one measurement accuracy, and the measurement accuracy cannot be changed.
In view of the technical defects in the related art, the embodiment of the invention provides a method for determining parameters of a periodic signal, which can improve the measurement accuracy of the parameters of the periodic signal on the premise of not increasing a peripheral circuit. In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Fig. 2 is a schematic implementation flow chart of a method for determining parameters of a periodic signal according to an embodiment of the present invention, where an execution body of the method is an electronic device, and the electronic device may be, for example, a pulse laser in fig. 1. The electronic equipment comprises a field programmable gate array (FPGA, field Programmable Gate Array) module and a clock module, wherein the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module is composed of at least two delays cascaded in sequence, and referring to fig. 2, the parameter determining method of the periodic signal comprises the following steps:
S201, receiving an external periodic signal.
In practical application, the electronic device may receive the external periodic signal through the buffer, and the FPGA module reads the external periodic signal from the buffer.
Here, if the electronic device is a pulse laser, the external periodic signal may be a pulse signal input to the pulse laser.
S202, determining configuration parameters of the phase-locked loop corresponding to the setting precision; the set accuracy characterizes the measurement accuracy of the parameters of the external periodic signal.
The setting accuracy represents the measurement accuracy of the parameter of the external periodic signal, and the setting accuracy may be selected by manually operating the electronic device by a user, or the electronic device determines the setting accuracy according to its own hardware, for example, assuming that the electronic device has 3 input interfaces of the external periodic signal, each input interface corresponds to one setting accuracy, and which input interface receives the external periodic signal, the setting accuracy is determined to be the setting accuracy corresponding to the input interface.
In practical applications, the setting accuracy is expressed in time, for example, the setting accuracy is 100 picoseconds, or the setting accuracy is 1 nanosecond, or the like.
In practical application, the corresponding relation between the setting precision and the configuration parameters can be written into a data table in advance, and after the setting precision is obtained, the data table is queried to obtain the configuration parameters corresponding to the setting precision. The configuration parameters of the phase-locked loop comprise frequency multiplication, frequency division coefficient and the like of the phase-locked loop, the phase-locked loop is connected with the clock module, and the phase-locked loop can carry out frequency division or frequency multiplication on the reference clock signal provided by the clock module based on the configuration parameters so as to obtain clock signals with different frequencies.
Referring to fig. 3, in an embodiment, when the configuration parameters of the phase-locked loop are determined based on the setting accuracy, the parameter determining method further includes:
s301, the phase-locked loop is controlled to generate the first clock signal based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module.
In an embodiment of the present invention, the first clock signal may be a clock signal having a frequency of several hundred MHz.
S302, determining the number of delayers in the delay module based on the frequency of the first clock signal.
The number of the time delays is determined by the frequency of the first clock signal, the period of the first clock signal is the inverse of the frequency of the first clock signal, and the sum of the delay times of all the time delays in the time delay module is required to be larger than the clock period of the first clock signal. For example, if the delay time of the delay device is 1ms and the period of the first clock signal is 10ms, the number of delay devices needs to be greater than 10. For example, the number of delays may be 12.
S203, when the setting precision is in a first setting range, respectively inputting the external periodic signals into the delay module and the trigger to obtain output signals of the trigger; each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal characterizes a level state of the external periodic signal.
And under the condition that the setting precision is in a first setting range, inputting external periodic signals into the delay module and the trigger respectively. Referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. The electronic equipment comprises a clock module and an FPGA module, wherein the FPGA module comprises a phase-locked loop, a delay module and a trigger, and the delay module consists of at least two delays which are cascaded front and back. The external periodic signals are firstly respectively input into a delayer 1 and a trigger in the delay module, and the trigger obtains output signals based on the external periodic signals. Each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger. Wherein the delay device 1 generates a delay signal based on an external periodic signal and transmits the delay signal to the trigger and the delay device 2, respectively, and the trigger obtains an output signal based on the delay signal. The delay 2 sends delay signals to the delay 3 and the flip-flop, respectively, based on the delay signals, and so on, until the last stage of the delay N. Finally, the trigger obtains n+1 output signals, wherein N corresponds to the output signals corresponding to the N delays, and 1 corresponds to the output signal corresponding to the external periodic signal.
The above embodiment has only one flip-flop, and all output signals are output by one flip-flop. Referring to fig. 5, fig. 5 is a schematic structural diagram of another electronic device according to an embodiment of the present invention. The application embodiment of the invention comprises n+1 triggers, wherein an external periodic signal is input into a trigger 0, a delay signal output by a delay device 1 is input into the trigger 1, and the like, and a delay signal of a delay device N is input into the trigger N. In the embodiment of the invention, only one output signal corresponding to one delayer is obtained by one trigger, so that the load of a single trigger can be reduced, the output signal corresponding to each delayer is clear at a glance, and the output signals corresponding to other delayers are not confused.
The delay signals are basically external periodic signals, and the delay signals output by each delayer are identical, but the output time is different, and the time interval of the delay signals output by two adjacent delayers is the corresponding delay time of the delayers. In practical applications, the delay device may be a Look-Up Table (LUT), which is essentially a random access memory (RAM, random Access Memory), and the delay device requires a delay time to output a delayed signal because the signal needs to go through a logic circuit in the RAM. The delay time of each of the delays is the same as long as the external environment is not changed.
In practical application, the flip-flop may be a D flip-flop, which has two stable states, namely "0" and "1", and outputs "1" when the external periodic signal is in a high level state; when the external periodic signal is in a low level state, the D flip-flop outputs "0". Therefore, the level state of the external periodic signal can be judged from the output signal of the flip-flop.
S204, determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module.
The parameters of the external periodic signal at least comprise any one of the following:
the period of the external periodic signal;
the pulse width of the external periodic signal.
Here, since the first clock signal is generated by the phase locked loop based on the configuration parameters and the reference clock signal, the period and pulse width of the first clock signal are known. The first clock signal can be used as a reference signal, the output signals of the triggers are read when the first clock signal is in an integer multiple period, and the level state of the external periodic signal can be accurately known between the two triggers according to the output signals of the triggers, so that the advance time of the rising edge of the external periodic signal relative to the rising edge of the first clock signal is deduced. According to the principle, when the level state of the external periodic signal is changed again according to the output signal of the trigger, the advance time of the falling edge of the external periodic signal relative to the rising edge of the first clock signal is deduced, and finally the pulse width of the external periodic signal is obtained based on the period of the first clock signal and the twice deduced advance time. The same can be said to obtain the low level time width of the external periodic signal, thereby obtaining the period of the external periodic signal.
For example, referring to fig. 6, fig. 6 is a schematic diagram showing a relationship among an external periodic signal, a first clock signal and a delayed signal provided by an application embodiment of the present invention, the embodiment of the present invention is implemented by the electronic device in fig. 5, and the delayed signal 1, the delayed signal 2 and the delayed signal 3 in fig. 6 are output by the delayer 1, the delayer 2 and the delayer 3 in fig. 5, respectively.
As shown in fig. 6, at time T0, since all signals are at low level, the outputs of all flip-flops are "0". At time T1, the flip-flop 0 output is 1, the flip-flop 1 output is 1, the flip-flop 2 output is 1, and the flip-flop 3 output is 0. From the output of the flip-flop, it can be known that the level state of the external periodic signal changes between the flip-flop 2 and the flip-flop 3, and it is inferred that the advance time of the rising edge of the external periodic signal with respect to the rising edge of the first clock signal is the sum of the delay times corresponding to the delay 1 and the delay 2, defined as R1 (lut1+lut2), lut1 is the delay time corresponding to the delay 1, and Lut2 is the delay time corresponding to the delay 2. At time T2, all flip-flop outputs are 1. At time T3, the flip-flop 0 output is 0, the flip-flop 1 output is 0, the flip-flop 2 output is 1, and the flip-flop 3 output is 0. From the output of the flip-flop, it can be known that the level state of the external periodic signal is changed between the flip-flop 1 and the flip-flop 2, and it is inferred that the advance time of the rising edge of the external periodic signal with respect to the falling edge of the first clock signal is the delay time corresponding to the delayer 1, which is defined as R2 (Lut 1). As can be seen from the figure, the high level time of the external periodic signal lasts for approximately 5 periods of the first clock signal, so the pulse width of the external periodic signal is 5clk+r1 (lut1+lut2) -R2 (Lut 1) =5clk+lut2, wherein clk is the period of the first clock signal. Similarly, the low level time of the external periodic signal, the pulse width of the external periodic signal+the low level time of the external periodic signal=the period of the external periodic signal can be calculated.
According to the method, the parameters of the external periodic signals can be obtained through calculation, according to a calculation formula, the measurement accuracy of the parameters of the external periodic signals can be known to depend on the delay time of the delayer, and the delayer is an RAM (random access memory) in nature, so that the signal transmission speed in the RAM is high, the delay time is very short, the measurement accuracy of the parameters of the external periodic signals is high, and the measurement accuracy can reach tens of picoseconds.
Referring to fig. 7, in an embodiment, the parameter determining method further includes:
s701, determining the current temperature of the FPGA module.
The electronic device may include a temperature detector, and the current temperature of the FPGA module is measured by the temperature detector, and in practical application, the current temperature may be a chip surface temperature of the FPGA module.
S702, determining delay time corresponding to the delayer based on the current temperature.
Since the delay device is essentially a RAM, the temperature affects the stability of the RAM, and thus the delay time corresponding to the delay device varies under different ambient temperatures. Therefore, the embodiment of the invention can write the delay time corresponding to the delayers at different temperatures into the data table in advance, and after determining the current temperature of the FPGA module, the data table is queried according to the current temperature to obtain the delay time corresponding to the current temperature.
According to the embodiment of the invention, the delay time corresponding to the delay device is determined based on the current temperature of the FPGA module, so that the measurement error of the parameter of the external periodic signal can be reduced, and the accuracy of the parameter measurement result is improved.
In the embodiment of the invention, the electronic equipment receives the external periodic signal and determines the configuration parameters of the phase-locked loop corresponding to the setting precision. The electronic equipment comprises a clock module and an FPGA module, wherein a phase-locked loop in the FPGA module generates a first clock signal based on configuration parameters corresponding to setting precision and a reference clock signal provided by the clock module. Under the condition that the setting precision is in a first setting range, respectively inputting external periodic signals into a delay module and a trigger in the FPGA module to obtain output signals of the trigger; each stage of delayer in the delay module respectively sends delay signals to the next stage of delayer and the trigger; the flip-flop generates an output signal according to an external periodic signal or a delayed signal. Finally, the electronic device determines a parameter of the external periodic signal based on the output signal, the corresponding delay time of the delay device, and the first clock signal. According to the embodiment of the invention, on the premise of not increasing a peripheral circuit, the internal resource of the FPGA module is directly utilized to improve the measurement accuracy of the parameters of the external periodic signal.
Referring to fig. 8, in an embodiment, the FPGA module further includes a first serial-parallel conversion interface, and the parameter determining method further includes, in a case where the setting accuracy is within a second setting range:
s801, the phase-locked loop is controlled to respectively generate the first clock signal and the second clock signal based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the frequencies of the first clock signal and the second clock signal are different.
And when the setting precision is in the second setting range, the phase-locked loop respectively generates a first clock signal and a second clock signal based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module. Here, the first clock signal and the second clock signal are clock signals having different frequencies, for example, the first clock signal may be a clock signal having a frequency of hundreds MHz, and the second clock signal may be a clock signal having a frequency of 1 GHz. In the embodiment of the invention, the first clock signal is used as a reference clock signal, the second clock signal is used as an interface clock signal of the first serial-parallel conversion interface, and the first clock signal and the second clock signal need to be in phase alignment. In practical applications, the first serial-parallel interface is a SELECT IO interface.
S802, sampling the external periodic signal based on the second clock signal to obtain first serial data.
In the embodiment of the invention, the received external periodic signal is high-speed serial data, and the first serial-parallel conversion interface receives the external periodic signal based on the second clock signal and samples the external periodic signal to obtain the first serial data.
S803 converts the first serial data into first parallel data based on the first serial-parallel interface and the first clock signal.
In most data communication systems, most of the communication data is serial data, while most processors require that the data be stored and processed in a parallel manner, so serial data needs to be converted into parallel data. And the FPGA module cannot process signals with higher frequency, and can only process the signals after being converted into parallel data with lower frequency.
For example, the first clock signal may be a clock signal having a frequency of hundreds of MHz, and the second clock signal may be a clock signal having a frequency of 1GHz, and since the first clock signal has a frequency lower than that of the second clock signal and the first clock signal and the second clock signal are phase-aligned, the first serial data may be converted into first parallel data corresponding to the first clock signal. In the embodiment of the invention, the first serial-parallel conversion interface has a serial-parallel conversion function, and can convert the first serial data into the first parallel data based on the first clock signal.
S804, determining parameters of the external periodic signal based on the first parallel data and the second clock signal.
The first parallel data is a digital signal consisting of 0 and 1. In the first parallel signal, 1 represents that the external periodic signal is in a high level state, 0 represents that the external periodic signal is in a low level state, and the number of 1 represents the pulse width of the external periodic signal. Thus, the parameters of the external periodic signal may be determined from the first parallel data and the second clock signal.
Referring to fig. 9, fig. 9 is a schematic diagram of converting a serial signal into a parallel signal according to an embodiment of the present invention. In fig. 9, the first clock signal and the second clock signal are phase aligned, and the period of the second clock signal is 7 times the period of the first clock signal. First, an external periodic signal is sampled based on a second clock signal to obtain first serial data. The first serial data is then converted into first parallel data based on the first clock signal. In fig. 9, a numeral 1 indicates that the external period signal is in a high level state, a numeral 0 indicates that the external period signal is in a low level state, and a duration of a numeral 1 indicates a pulse width of the external period signal, and 6 1 s are shown in fig. 9, so that the pulse width of the external period signal=6×the period of the second clock signal. Similarly, the duration of the number 0 indicates the low-level time width of the external periodic signal, and the period of the external periodic signal=the pulse width of the external periodic signal+the low-level time width of the external periodic signal.
In an embodiment of the invention, the maximum measurement accuracy of the parameter of the external periodic signal depends on the period width of the interface clock signal of the first serial-parallel conversion interface, i.e. the period width of the second clock signal. For example, if the frequency of the second clock signal is 1GHz, the maximum measurement accuracy of the parameter of the external periodic signal is 1ns. Therefore, the embodiment of the invention can be used for measuring the periodic signal with the period of 1ns-1ms, and has high measurement accuracy.
Referring to fig. 10, in an embodiment, the FPGA module further includes a second serial-parallel conversion interface, and in a case where the setting accuracy is within a third setting range, the parameter determining method further includes:
s1001, controlling the phase-locked loop to respectively generate the first clock signal and the third clock signal based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the frequencies of the first clock signal and the third clock signal are different.
The frequencies of the first clock signal and the third clock signal are different, for example, the first clock signal may be a clock signal with a frequency of hundreds of MHz, and the third clock signal may be a clock signal with a frequency of tens of GHz.
In practical application, the second serial-parallel conversion interface is a TRANSCEIVER interface.
S1002, sampling the external periodic signal based on the third clock signal to obtain second serial data.
And S1003, converting the second serial data into second parallel data based on the second serial-parallel conversion interface and the first clock signal.
In the embodiment of the invention, the second serial-parallel conversion interface has a serial-parallel conversion function, and can convert the second serial data into the second parallel data based on the first clock signal.
S1004 determining a parameter of the external periodic signal based on the second parallel data and the third clock signal.
The second parallel data is a digital signal, wherein 1 in the second parallel data represents that the external periodic signal is in a high level state, 0 represents that the external periodic signal is in a low level state, and the number of 1 represents the pulse width of the external periodic signal. Thus, the parameters of the external periodic signal may be determined from the second parallel data and the second clock signal. Reference is made in particular to the embodiment shown in fig. 9 described above.
In the embodiment of the invention, the maximum measurement accuracy of the parameter of the external periodic signal depends on the period width of the interface clock signal of the second serial-parallel conversion interface, i.e. the period width of the third clock signal. For example, if the third clock signal has a frequency of 10GHz, the maximum measurement accuracy of the parameter of the external periodic signal is 100ps. Therefore, the embodiment of the invention can be used for measuring the periodic signal with the period of 100ps-1us, and has high measurement accuracy.
If the electronic device has both the second serial-to-parallel interface and the first serial-to-parallel interface, the frequencies of the first clock signal, the second clock signal, and the third clock signal are different. The parameters of the periodic signal can be measured according to the actual precision requirement, and if the set precision is in the first set range, the external periodic signal is respectively input into the delay module and the trigger. If the setting accuracy is within the second setting range, an external periodic signal is input to the first serial-parallel interface. If the setting accuracy is within the third setting range, an external periodic signal is input to the second serial-parallel interface.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.
Referring to fig. 11, fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. The electronic device includes:
a clock module for providing a reference clock signal;
the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module consists of at least two delays which are cascaded front and back; the FPGA module is used for: acquiring an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the setting precision; the set precision characterizes the measurement precision of the parameters of the external periodic signal; under the condition that the setting precision is in a first setting range, inputting the external periodic signal into the delay module and the trigger respectively to obtain an output signal of the trigger; each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal characterizes the level state of the external periodic signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delay device and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module.
In practical application, the electronic device may receive the external periodic signal through the buffer, and the FPGA module obtains the external periodic signal from the buffer.
Here, if the electronic device is a pulse laser, the external periodic signal may be a pulse signal input to the pulse laser.
The embodiment of the present invention corresponds to the above embodiment of the method, so the electronic device in fig. 11 is the electronic device in fig. 4.
Referring to fig. 12, in an embodiment, the FPGA module further includes a first serial-parallel conversion interface, and in a case where the setting accuracy is within the second setting range, the FPGA module is further configured to:
controlling the phase-locked loop to generate the first clock signal and the second clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal are different in frequency;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel interface and the first clock signal;
Parameters of the external periodic signal are determined based on the first parallel data and the second clock signal.
Referring to fig. 12, in an embodiment, the FPGA module further includes a second serial-parallel interface, and in a case where the setting accuracy is within a third setting range, the FPGA module is further configured to:
controlling the phase-locked loop to generate the first clock signal and the third clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal are different in frequency;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel interface and the first clock signal;
a parameter of the external periodic signal is determined based on the second parallel data and the third clock signal.
The electronic device provided in the above embodiment and the method embodiment for determining the parameter of the external periodic signal belong to the same concept, and the specific implementation process of the method embodiment is detailed in the method embodiment, which is not repeated herein.
The electronic device further comprises a memory, which may be an internal storage unit of the electronic device, such as a hard disk or a memory of the electronic device. The memory may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the electronic device. Further, the memory may also include both an internal storage unit and an external storage device of the electronic device. The memory is used for storing other programs and data required by the electronic device. The memory may also be used to temporarily store data that has been output or is to be output.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (9)
1. The parameter determining method of the periodic signal is applied to electronic equipment, wherein the electronic equipment comprises a Field Programmable Gate Array (FPGA) module and a clock module, and the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module consists of at least two delays which are cascaded in sequence, and is characterized in that the parameter determining method comprises the following steps:
receiving an external periodic signal;
determining configuration parameters of the phase-locked loop corresponding to the setting precision; the set precision characterizes the measurement precision of the parameters of the external periodic signal;
under the condition that the setting precision is in a first setting range, inputting the external periodic signal into the delay module and the trigger respectively to obtain an output signal of the trigger; each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal characterizes the level state of the external periodic signal;
Determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delay device and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module.
2. The parameter determination method according to claim 1, wherein the FPGA module further includes a first serial-parallel conversion interface, and wherein the parameter determination method further includes, in a case where the setting accuracy is within a second setting range:
controlling the phase-locked loop to generate the first clock signal and the second clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the frequencies of the first clock signal and the second clock signal are different;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel interface and the first clock signal;
parameters of the external periodic signal are determined based on the first parallel data and the second clock signal.
3. The parameter determination method according to claim 1, wherein the FPGA module further includes a second serial-parallel conversion interface, and wherein in a case where the setting accuracy is within a third setting range, the parameter determination method further includes:
controlling the phase-locked loop to generate the first clock signal and the third clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the frequencies of the first clock signal and the third clock signal are different;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel interface and the first clock signal;
a parameter of the external periodic signal is determined based on the second parallel data and the third clock signal.
4. A parameter determining method according to any one of claims 1 to 3, wherein the parameter of the external periodic signal comprises at least any one of:
the period of the external periodic signal;
The pulse width of the external periodic signal.
5. The parameter determination method according to claim 1, wherein when determining the configuration parameter of the phase-locked loop based on the setting accuracy, the parameter determination method further comprises:
controlling the phase-locked loop to generate the first clock signal based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module;
the number of delays in the delay module is determined based on the frequency of the first clock signal.
6. The parameter determination method according to claim 1, characterized in that the parameter determination method further comprises:
determining the current temperature of the FPGA module;
and determining the delay time corresponding to the delay module based on the current temperature.
7. An electronic device, comprising:
a clock module for providing a reference clock signal;
the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module consists of at least two delays which are cascaded front and back; the FPGA module is used for: acquiring an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the setting precision; the set precision characterizes the measurement precision of the parameters of the external periodic signal; under the condition that the setting precision is in a first setting range, inputting the external periodic signal into the delay module and the trigger respectively to obtain an output signal of the trigger; each stage of delayer in the delay module respectively transmits delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal characterizes the level state of the external periodic signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delay device and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module.
8. The electronic device of claim 7, wherein the FPGA module further comprises a first serial-to-parallel interface, the FPGA module further configured to, if the setting accuracy is within a second setting range:
controlling the phase-locked loop to generate the first clock signal and the second clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal are different in frequency;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel interface and the first clock signal;
parameters of the external periodic signal are determined based on the first parallel data and the second clock signal.
9. The electronic device of claim 7, wherein the FPGA module further comprises a second serial-to-parallel interface, the FPGA module further configured to, if the setting accuracy is within a third setting range:
Controlling the phase-locked loop to generate the first clock signal and the third clock signal respectively based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal are different in frequency;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel interface and the first clock signal;
a parameter of the external periodic signal is determined based on the second parallel data and the third clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010550254.6A CN111756357B (en) | 2020-06-16 | 2020-06-16 | Parameter determination method of periodic signal and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010550254.6A CN111756357B (en) | 2020-06-16 | 2020-06-16 | Parameter determination method of periodic signal and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111756357A CN111756357A (en) | 2020-10-09 |
| CN111756357B true CN111756357B (en) | 2024-04-02 |
Family
ID=72675380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010550254.6A Active CN111756357B (en) | 2020-06-16 | 2020-06-16 | Parameter determination method of periodic signal and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111756357B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104111481A (en) * | 2014-07-30 | 2014-10-22 | 桂林电子科技大学 | Synchronous clock phase difference measuring system and method |
| CN110514404A (en) * | 2019-08-23 | 2019-11-29 | 武汉光迅科技股份有限公司 | A kind of pulse signal generation device, method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8683254B2 (en) * | 2011-01-07 | 2014-03-25 | Anue Systems, Inc. | Systems and methods for precise event timing measurements |
-
2020
- 2020-06-16 CN CN202010550254.6A patent/CN111756357B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104111481A (en) * | 2014-07-30 | 2014-10-22 | 桂林电子科技大学 | Synchronous clock phase difference measuring system and method |
| CN110514404A (en) * | 2019-08-23 | 2019-11-29 | 武汉光迅科技股份有限公司 | A kind of pulse signal generation device, method |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA同步时钟测量系统的研究及实现;陈巍;王国富;张法全;叶金才;;电子技术应用(第12期);86-88,91页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111756357A (en) | 2020-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100866601B1 (en) | Apparatus and Method for controlling on-die terminator in semiconductor device | |
| CN105718404B (en) | A kind of square-wave generator and method based on FPGA | |
| US9344066B2 (en) | Digital open loop duty cycle correction circuit | |
| US6463006B2 (en) | Semiconductor integrated circuit | |
| US11381231B2 (en) | Digital measurement circuit and memory system using the same | |
| CN101645301B (en) | Temperature self-adaptive adjustment method for read data sampling and device thereof | |
| CN111161766B (en) | DDR SDRAM physical layer interface circuit and DDR SDRAM control device | |
| CN102967819B (en) | High speed test circuit and method | |
| CN111756357B (en) | Parameter determination method of periodic signal and electronic equipment | |
| US20150113236A1 (en) | Memory controller | |
| US5668982A (en) | System and method for using a half-clock module to implement computer timing control circuitry | |
| CN113504513B (en) | Time domain nonlinear frequency modulation signal generation method | |
| CN116155243A (en) | Ultra-narrow pulse stretching circuit, method and electronic equipment | |
| US10156603B1 (en) | Apparatus for adding jitters to the edges of a pulse sequence | |
| CN114791556A (en) | On-chip clock network delay test method and test circuit | |
| CN115705876A (en) | Delay calibration circuit, memory and clock signal calibration method | |
| CN112290934B (en) | Controllable jitter clock generating device based on Bias-Tee signal synthesis | |
| US11227642B2 (en) | Memory controller, method for read control of memory, and associated storage system | |
| CN111641490B (en) | High-precision phase calibration and time reference determination method for sampling clock | |
| KR20150014611A (en) | Data output circuit | |
| CN111371453A (en) | Signal period measuring circuit and method | |
| Zhaolin et al. | High resolution programmable digital delay generator design and realization | |
| CN109155798B (en) | Asynchronous FIFO circuit and time delay determination method | |
| Nieminen et al. | A 5.8-Gbps low-noise scalable low-voltage signaling serial link transmitter for MIPI M-PHY in 40-nm CMOS | |
| CN220188975U (en) | Data transmission system and chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |