CN111756357A - Periodic signal parameter determination method and electronic equipment - Google Patents
Periodic signal parameter determination method and electronic equipment Download PDFInfo
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Abstract
The embodiment of the invention is suitable for the technical field of signal measurement and provides a parameter determination method of a periodic signal and electronic equipment, wherein the parameter determination method of the periodic signal comprises the following steps: receiving an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the set precision; respectively inputting external periodic signals into a delay module and the trigger to obtain output signals of the trigger under the condition that the set precision is within a first set range; each stage of delayer in the delay module respectively sends delay signals to the next stage of delayer and the trigger; the trigger generates an output signal according to an external periodic signal or a delay signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and a first clock signal; the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
Description
Technical Field
The invention belongs to the field of signal measurement, and particularly relates to a parameter determination method of a periodic signal and electronic equipment.
Background
In the working process of the electronic equipment, the parameters of the periodic signals need to be measured, and the measurement precision of the parameters of the periodic signals can influence the output result of the electronic equipment. For example, in the optical power output control of a pulse laser, the measurement accuracy of the pulse width and the pulse period of a pulse signal directly affects the calculation of the peak power and the average power. At present, in the related art, the measurement accuracy of the parameter of the periodic signal needs to be improved by adding a peripheral circuit, and the peripheral circuit is complex in design and high in cost.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for determining parameters of a periodic signal and an electronic device, so as to at least solve the problem that the measurement accuracy of the parameters of the periodic signal is improved by adding a peripheral circuit in the related art, which results in high cost.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a method for determining a parameter of a periodic signal, which is applied to an electronic device, where the electronic device includes a field programmable gate array FPGA module and a clock module, and the FPGA module includes a phase-locked loop, a delay module, and a trigger; the delay module is composed of at least two cascaded delays, and is characterized in that the parameter determination method comprises the following steps:
receiving an external periodic signal;
determining configuration parameters of the phase-locked loop corresponding to the set precision; the set precision represents the measurement precision of the parameter of the external periodic signal;
under the condition that the setting precision is in a first setting range, respectively inputting the external periodic signal into the delay module and the trigger to obtain an output signal of the trigger; each stage of delayer in the delay module sends a delay signal to a next stage of delayer and the trigger respectively; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal is used for representing the level state of the external periodic signal;
determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and a first clock signal; and the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
In the foregoing solution, the FPGA module further includes a first serial-to-parallel conversion interface, and when the setting precision is in a second setting range, the parameter determining method further includes:
controlling the phase-locked loop to respectively generate the first clock signal and the second clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal have different frequencies;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the first parallel data and the second clock signal.
In the foregoing solution, the FPGA module further includes a second serial-to-parallel conversion interface, and when the setting precision is within a third setting range, the parameter determining method further includes:
controlling the phase-locked loop to respectively generate the first clock signal and the third clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal have different frequencies;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the second parallel data and the third clock signal.
In the above scheme, the parameter of the external periodic signal at least includes any one of:
a period of the external periodic signal;
pulse width of the external periodic signal.
In the foregoing solution, when determining the configuration parameter of the phase-locked loop based on the setting accuracy, the parameter determining method further includes:
controlling the phase-locked loop to generate the first clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module;
determining a number of delays in the delay module based on the frequency of the first clock signal.
In the foregoing solution, the parameter determining method further includes:
determining a current temperature of the FPGA module;
and determining the corresponding delay time of the delay module based on the current temperature.
In a second aspect, an embodiment of the present invention provides an electronic device, where the electronic device includes:
a clock module for providing a reference clock signal;
the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module consists of at least two delayers which are cascaded in front and back; the FPGA module is used for: acquiring an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the set precision; the set precision represents the measurement precision of the parameter of the external periodic signal; under the condition that the setting precision is in a first setting range, respectively inputting the external periodic signal into the delay module and the trigger to obtain an output signal of the trigger; each stage of delayer in the delay module sends a delay signal to a next stage of delayer and the trigger respectively; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal is used for representing the level state of the external periodic signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and a first clock signal; and the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
In the foregoing solution, the FPGA module further includes a first serial-to-parallel conversion interface, and when the setting precision is within a second setting range, the FPGA module is further configured to:
controlling the phase-locked loop to respectively generate the first clock signal and the second clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal have different frequencies;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the first parallel data and the second clock signal.
In the foregoing solution, the FPGA module further includes a second serial-to-parallel conversion interface, and when the setting precision is within a third setting range, the FPGA module is further configured to:
controlling the phase-locked loop to respectively generate the first clock signal and the third clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal are different in frequency;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the second parallel data and the third clock signal.
In the embodiment of the invention, the electronic equipment receives the external periodic signal and determines the configuration parameters of the phase-locked loop corresponding to the set precision. The electronic equipment comprises a clock module and an FPGA module, wherein a phase-locked loop in the FPGA module generates a first clock signal based on configuration parameters corresponding to set precision and a reference clock signal provided by the clock module. Respectively inputting external periodic signals into a delay module and a trigger in an FPGA module under the condition that the set precision is in a first set range to obtain output signals of the trigger; each stage of delayer in the delay module respectively sends delay signals to the next stage of delayer and the trigger; the flip-flop generates an output signal according to an external periodic signal or a delay signal. Finally, the electronic device determines a parameter of the external periodic signal based on the output signal, a delay time corresponding to the delay timer, and the first clock signal. According to the embodiment of the invention, the measurement precision of the parameter of the external periodic signal can be improved by directly utilizing the internal resource of the FPGA module on the premise of not increasing the peripheral circuit.
Drawings
Fig. 1 is a schematic structural diagram of a pulse laser according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating an implementation of a method for determining parameters of a periodic signal according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating an implementation of another method for determining parameters of a periodic signal according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another electronic device provided in an embodiment of the invention;
FIG. 6 is a diagram illustrating the relationship between an external periodic signal, a first clock signal and a delay signal according to an embodiment of the present invention;
fig. 7 is a schematic flow chart illustrating an implementation of another method for determining parameters of a periodic signal according to an embodiment of the present invention;
fig. 8 is a schematic flow chart illustrating an implementation of another method for determining parameters of a periodic signal according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of converting serial signals into parallel signals according to an embodiment of the present invention;
fig. 10 is a schematic flow chart illustrating an implementation of another method for determining parameters of a periodic signal according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of another electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The technical means described in the embodiments of the present invention may be arbitrarily combined without conflict.
In addition, in the embodiments of the present invention, "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a specific order or a sequential order.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pulse laser according to an embodiment of the present invention, where the pulse laser includes: the device comprises a parameter measuring device, a feedback control device, a photoelectric conversion device, a driving circuit, a coupler and a laser.
As shown in fig. 1, the optical pulse signal output by the laser is divided into two paths by the coupler, one path of the optical pulse signal is used as a pure output, and the other path of the optical pulse signal is input to the photoelectric conversion device. The photoelectric conversion device carries out photoelectric conversion on the optical pulse signal to obtain an electric pulse signal, the photoelectric conversion device inputs the electric pulse signal into the parameter measuring device, and the parameter measuring device carries out parameter measurement on the electric pulse signal to obtain parameters such as the period and the pulse width of the electric pulse signal. The parameter measuring device inputs the measured parameters into the feedback control device, the feedback control device calculates the peak power and the average power in real time according to the pulse capacity of the electric pulse signal measured by the photoelectric conversion device and the parameters of the electric pulse signal, and adjusts the output current of the driving circuit in real time according to the peak power and the average power so as to control the waveform and the size of the optical pulse output by the laser. The peak power is pulse energy/pulse width, and the average power is pulse energy/pulse period. Therefore, the measurement accuracy of the pulse width and the pulse period of the pulse signal can directly influence the calculation of the peak power and the average power, the higher the measurement accuracy of the pulse width and the pulse period of the pulse signal is, the more accurate the calculation of the peak power and the average power is, and the more accurate the output control of the optical pulse is.
At present, in the related art, the measurement accuracy of the parameter of the periodic signal is improved by adding a peripheral circuit, and the peripheral circuit is complex in design and high in cost. In some electronic devices, parameters of multiple periodic signals need to be measured simultaneously, and measurement accuracy of different periodic signals also has different requirements, while peripheral circuits generally only can provide one measurement accuracy, and the measurement accuracy cannot be changed.
In view of the technical defects in the related art, embodiments of the present invention provide a method for determining parameters of a periodic signal, which can improve the measurement accuracy of the parameters of the periodic signal without adding a peripheral circuit. In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 2 is a schematic flow chart of an implementation of a method for determining parameters of a periodic signal according to an embodiment of the present invention, where an implementation subject of the method is an electronic device, for example, the electronic device may be the pulsed laser in fig. 1. The electronic equipment comprises a Field Programmable Gate Array (FPGA) module and a clock module, wherein the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module is composed of at least two delay units cascaded in tandem, and referring to fig. 2, the parameter determination method of the periodic signal includes:
s201, receiving an external periodic signal.
In practical applications, the electronic device may receive the external periodic signal through a buffer, and the FPGA module reads the external periodic signal from the buffer.
Here, if the electronic device is a pulse laser, the external periodic signal may be a pulse signal input to the pulse laser.
S202, determining configuration parameters of the phase-locked loop corresponding to the set precision; the set accuracy characterizes a measurement accuracy of a parameter of the external periodic signal.
The setting accuracy represents the measurement accuracy of the parameter of the external periodic signal, and the setting accuracy can be selected by the user through manual operation of the electronic device, or the electronic device determines the setting accuracy according to hardware of the electronic device, for example, assuming that the electronic device has 3 input interfaces of the external periodic signal, each input interface corresponds to one setting accuracy, and which input interface receives the external periodic signal determines the setting accuracy as the setting accuracy corresponding to the input interface.
In practical applications, the setting accuracy is expressed in terms of time, and for example, the setting accuracy is 100 picoseconds, or the setting accuracy is 1 nanosecond, or the like.
The configuration parameters of the phase-locked loop corresponding to the set precision are determined, in practical application, the corresponding relation between the set precision and the configuration parameters can be written into a data table in advance, and after the set precision is obtained, the data table is inquired to obtain the configuration parameters corresponding to the set precision. The configuration parameters of the phase-locked loop comprise frequency multiplication, frequency division coefficients and the like of the phase-locked loop, the phase-locked loop is connected with the clock module, and the phase-locked loop can perform frequency division or frequency multiplication processing on a reference clock signal provided by the clock module based on the configuration parameters so as to obtain clock signals with different frequencies.
Referring to fig. 3, in an embodiment, when determining the configuration parameters of the phase-locked loop based on the setting accuracy, the parameter determining method further includes:
and S301, controlling the phase-locked loop to generate the first clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
In the embodiment of the present invention, the first clock signal may be a clock signal having a frequency of several hundred MHz.
S302, determining the number of the delayers in the delay module based on the frequency of the first clock signal.
The number of the delayers is determined by the frequency of the first clock signal, the period of the first clock signal is the reciprocal of the frequency of the first clock signal, and the sum of the delay time of all the delayers in the delay module needs to be larger than the clock period of the first clock signal. For example, if the delay time of the delayer is 1ms and the period of the first clock signal is 10ms, the number of the delayers needs to be more than 10. For example, the number of the delay devices may be 12.
S203, respectively inputting the external periodic signal into the delay module and the trigger to obtain an output signal of the trigger under the condition that the setting precision is in a first setting range; each stage of delayer in the delay module sends a delay signal to a next stage of delayer and the trigger respectively; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal is indicative of a level state of the external periodic signal.
And under the condition that the setting precision is in a first setting range, respectively inputting the external periodic signal into the delay module and the trigger. Referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. The electronic equipment comprises a clock module and an FPGA module, wherein the FPGA module comprises a phase-locked loop, a delay module and a trigger, and the delay module is composed of at least two delayers which are cascaded in front and back. The external periodic signal is firstly respectively input into a delayer 1 and a trigger in the delay module, and the trigger obtains an output signal based on the external periodic signal. Each stage of delay unit in the delay module sends delay signals to the next stage of delay unit and the trigger. The delayer 1 generates a delay signal based on an external periodic signal, and sends the delay signal to the trigger and the delayer 2 respectively, and the trigger obtains an output signal based on the delay signal. And the delayer 2 respectively sends delay signals to the delayer 3 and the trigger based on the delay signals, and so on until the delayer N at the last stage. Finally, the trigger obtains N +1 output signals, wherein N corresponds to the output signals corresponding to the N delayers, and 1 corresponds to the output signal corresponding to the external periodic signal.
The above embodiment has only one flip-flop, and all output signals are output by one flip-flop. Referring to fig. 5, fig. 5 is a schematic structural diagram of another electronic device according to an embodiment of the present invention. The application embodiment of the invention comprises N +1 triggers, wherein an external periodic signal is input into the trigger 0, a delay signal output by the delayer 1 is input into the trigger 1, and the like, and a delay signal of the delayer N is input into the trigger N. In the embodiment of the invention, one trigger only obtains the output signal corresponding to one delayer, so that the load of a single trigger can be reduced, and the output signal corresponding to each delayer is clear at a glance and cannot be confused with the output signals corresponding to other delayers.
The delay signal is essentially an external periodic signal, the delay signals output by each delayer are the same, only the output time is different, and the time interval of the delay signals output by two adjacent delayers is the delay time corresponding to the delayer. In practical applications, the delay device may be a Look-Up Table (LUT), which is essentially a Random Access Memory (RAM), and since the signal needs to go through a logic circuit in the RAM, the delay device needs to output the delayed signal after a delay time. The delay time of each delay is the same as long as the external environment does not change.
In practical application, the flip-flop may be a D flip-flop, and the D flip-flop has two stable states, i.e., "0" and "1", and outputs "1" when the external periodic signal is in a high level state; when the external periodic signal is in a low state, the D flip-flop outputs "0". Therefore, the level state of the external periodic signal can be judged according to the output signal of the trigger.
S204, determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and the first clock signal; and the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
The parameter of the external periodic signal at least comprises any one of the following items:
a period of the external periodic signal;
pulse width of the external periodic signal.
Here, since the first clock signal is generated by the phase locked loop based on the configuration parameters and the reference clock signal, the period and pulse width of the first clock signal are known. The first clock signal can be used as a reference signal, the output signals of the flip-flops are read at integral multiple periods of the first clock signal, and the fact between the two flip-flops that the level state of the external periodic signal changes can be accurately known according to the output signals of the flip-flops, so that the advance time of the rising edge of the external periodic signal relative to the rising edge of the first clock signal can be deduced. According to the principle, when the level state of the external periodic signal is known to change again according to the output signal of the trigger, the advance time of the falling edge of the external periodic signal relative to the rising edge of the first clock signal is deduced, and finally the pulse width of the external periodic signal is obtained based on the period of the first clock signal and the advance time deduced twice. Similarly, the low level time width of the external periodic signal can be obtained, so that the period of the external periodic signal can be obtained.
For example, referring to fig. 6, fig. 6 is a schematic diagram illustrating a relationship between an external periodic signal, a first clock signal and a delay signal according to an embodiment of the present invention, where the embodiment of the present invention is implemented by the electronic device in fig. 5, and a delay signal 1, a delay signal 2 and a delay signal 3 in fig. 6 are respectively output by a delay unit 1, a delay unit 2 and a delay unit 3 in fig. 5.
As shown in fig. 6, at time T0, the outputs of all flip-flops are "0" since all signals are at low level. At time T1, the output of flip-flop 0 is 1, the output of flip-flop 1 is 1, the output of flip-flop 2 is 1, and the output of flip-flop 3 is 0. According to the output of the flip-flop, it can be known that the level state of the external periodic signal changes between the flip-flop 2 and the flip-flop 3, and it is inferred that the advance time of the rising edge of the external periodic signal relative to the rising edge of the first clock signal is the sum of the delay times corresponding to the delayers 1 and 2, and is defined as R1(Lut1+ Lut2), Lut1 is the delay time corresponding to the delayer 1, and Lut2 is the delay time corresponding to the delayer 2. At time T2, all flip-flop outputs are 1. At time T3, the output of flip-flop 0 is 0, the output of flip-flop 1 is 0, the output of flip-flop 2 is 1, and the output of flip-flop 3 is 0. According to the output of the flip-flop, it can be known that the level state of the external periodic signal changes between the flip-flop 1 and the flip-flop 2, and the delay time corresponding to the delay unit 1 is the advance time of the rising edge of the external periodic signal relative to the falling edge of the first clock signal, which is defined as R2(Lut 1). As can be seen from the figure, the high level time of the external periodic signal lasts for about 5 cycles of the first clock signal, so the pulse width of the external periodic signal is 5clk + R1(Lut1+ Lut2) -R2(Lut1) ═ 5clk + Lut2, where clk is the cycle of the first clock signal. Similarly, the low level time of the external periodic signal can be calculated, and the pulse width of the external periodic signal + the low level time of the external periodic signal is equal to the period of the external periodic signal.
The method can calculate the parameters of the external periodic signals, and can know that the measurement accuracy of the parameters of the external periodic signals depends on the delay time of the delayer according to a calculation formula.
Referring to fig. 7, in an embodiment, the parameter determining method further includes:
s701, determining the current temperature of the FPGA module.
The electronic device may include a temperature detector, and the current temperature of the FPGA module is measured by the temperature detector, and in practical application, the current temperature may be a chip surface temperature of the FPGA module.
S702, determining the delay time corresponding to the delayer based on the current temperature.
Since the delayer is essentially a RAM, the temperature affects the stability of the RAM, and therefore, the delay time corresponding to the delayer varies under different environmental temperatures. Therefore, the embodiment of the invention can write the delay time corresponding to the delayers at different temperatures into the data table in advance, and after the current temperature of the FPGA module is determined, the data table is inquired according to the current temperature to obtain the delay time corresponding to the current temperature.
According to the embodiment of the invention, the delay time corresponding to the delayer is determined and determined based on the current temperature of the FPGA module, so that the measurement error of the parameter of the external periodic signal can be reduced, and the accuracy of the parameter measurement result is improved.
In the embodiment of the invention, the electronic equipment receives the external periodic signal and determines the configuration parameters of the phase-locked loop corresponding to the set precision. The electronic equipment comprises a clock module and an FPGA module, wherein a phase-locked loop in the FPGA module generates a first clock signal based on configuration parameters corresponding to set precision and a reference clock signal provided by the clock module. Respectively inputting external periodic signals into a delay module and a trigger in an FPGA module under the condition that the set precision is in a first set range to obtain output signals of the trigger; each stage of delayer in the delay module respectively sends delay signals to the next stage of delayer and the trigger; the flip-flop generates an output signal according to an external periodic signal or a delay signal. Finally, the electronic device determines a parameter of the external periodic signal based on the output signal, a delay time corresponding to the delay timer, and the first clock signal. According to the embodiment of the invention, the measurement precision of the parameter of the external periodic signal can be improved by directly utilizing the internal resource of the FPGA module on the premise of not increasing the peripheral circuit.
Referring to fig. 8, in an embodiment, the FPGA module further includes a first serial-to-parallel conversion interface, and in a case that the setting precision is within a second setting range, the parameter determining method further includes:
s801, controlling the phase-locked loop to respectively generate the first clock signal and the second clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal have different frequencies.
And under the condition that the setting precision is in a second setting range, the phase-locked loop respectively generates a first clock signal and a second clock signal based on the configuration parameters corresponding to the setting precision and the reference clock signal provided by the clock module. Here, the first clock signal and the second clock signal are clock signals having different frequencies, and for example, the first clock signal may be a clock signal having a frequency of several hundreds MHz, and the second clock signal may be a clock signal having a frequency of 1 GHz. In the embodiment of the present invention, the first clock signal is used as a reference clock signal, the second clock signal is used as an interface clock signal of the first serial-to-parallel conversion interface, and the first clock signal and the second clock signal need to be phase-aligned. In practical application, the first serial-to-parallel conversion interface is a SELECT IO interface.
S802, sampling the external periodic signal based on the second clock signal to obtain first serial data.
In the embodiment of the invention, the received external periodic signal is high-speed serial data, the first serial-to-parallel conversion interface receives the external periodic signal based on the second clock signal, and samples the external periodic signal to obtain the first serial data.
S803, converting the first serial data into first parallel data based on the first serial-to-parallel conversion interface and the first clock signal.
In most data communication systems, most of the communication data is serial data, and most processors require the data to be stored and processed in parallel, so that the serial data needs to be converted into parallel data. And the FPGA module can not process signals with higher frequency, and can process the signals only by converting the signals into parallel data with lower frequency.
For example, the first clock signal may be a clock signal having a frequency of several hundreds MHz, the second clock signal may be a clock signal having a frequency of 1GHz, and the first serial data may be converted into the first parallel data corresponding to the first clock signal since the frequency of the first clock signal is lower than that of the second clock signal and the first clock signal and the second clock signal are phase-aligned. In the embodiment of the present invention, the first serial-to-parallel conversion interface has a serial-to-parallel conversion function, and the first serial-to-parallel conversion interface may convert the first serial data into the first parallel data based on the first clock signal.
S804, determining the parameter of the external periodic signal based on the first parallel data and the second clock signal.
The first parallel data is a digital signal composed of 0 and 1. In the first parallel signal, 1 represents that the external periodic signal is in a high level state, 0 represents that the external periodic signal is in a low level state, and the number of 1 represents the pulse width of the external periodic signal. Accordingly, the parameter of the external periodic signal can be determined according to the first parallel data and the second clock signal.
Referring to fig. 9, fig. 9 is a schematic diagram of converting serial signals into parallel signals according to an embodiment of the present invention. In fig. 9, the first clock signal and the second clock signal are phase-aligned, and the period of the second clock signal is 7 times the period of the first clock signal. First, an external periodic signal is sampled based on a second clock signal to obtain first serial data. The first serial data is then converted into first parallel data based on a first clock signal. In fig. 9, a number 1 indicates that the external periodic signal is in a high state, a number 0 indicates that the external periodic signal is in a low state, a duration of the number 1 indicates a pulse width of the external periodic signal, and 6 pulses 1 exist in fig. 9, so that the pulse width of the external periodic signal is equal to 6 × a period of the second clock signal. Similarly, the duration of the digital 0 indicates the low level time width of the external periodic signal, and the period of the external periodic signal is equal to the pulse width of the external periodic signal + the low level time width of the external periodic signal.
In an embodiment of the present invention, the maximum measurement accuracy of the parameter of the external periodic signal depends on the period width of the interface clock signal of the first serial-to-parallel conversion interface, i.e. the period width of the second clock signal. For example, if the frequency of the second clock signal is 1GHz, the maximum measurement accuracy of the parameter of the external periodic signal is 1 ns. Therefore, the embodiment of the invention can be used for measuring the periodic signals with the period of 1ns-1ms, and the measurement precision is high.
Referring to fig. 10, in an embodiment, the FPGA module further includes a second serial-parallel conversion interface, and in a case that the setting precision is within a third setting range, the parameter determining method further includes:
s1001, controlling the phase-locked loop to respectively generate the first clock signal and the third clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal have different frequencies.
The first clock signal and the third clock signal have different frequencies, for example, the first clock signal may be a clock signal having a frequency of several hundreds MHz, and the third clock signal may be a clock signal having a frequency of several tens GHz.
In practical applications, the second serial-to-parallel conversion interface is an TRANSCEIVER interface.
S1002, sampling the external periodic signal based on the third clock signal to obtain second serial data.
S1003, converting the second serial data into second parallel data based on the second serial-to-parallel conversion interface and the first clock signal.
In an embodiment of the present invention, the second serial-to-parallel conversion interface has a serial-to-parallel conversion function, and the second serial-to-parallel conversion interface may convert the second serial data into the second parallel data based on the first clock signal.
S1004, determining a parameter of the external periodic signal based on the second parallel data and the third clock signal.
The second parallel data is a digital signal, wherein 1 in the second parallel data represents that the external periodic signal is in a high level state, 0 represents that the external periodic signal is in a low level state, and the number of 1 represents the pulse width of the external periodic signal. Accordingly, the parameter of the external periodic signal may be determined according to the second parallel data and the second clock signal. Reference may be made in particular to the embodiment shown in fig. 9 described above.
In the embodiment of the present invention, the maximum measurement accuracy of the parameter of the external periodic signal depends on the period width of the interface clock signal of the second serial-to-parallel conversion interface, that is, the period width of the third clock signal. For example, the third clock signal frequency is 10GHz, and the maximum measurement accuracy of the parameter of the external periodic signal is 100 ps. Therefore, the embodiment of the invention can be used for measuring the periodic signal with the period of 100ps-1us, and the measurement precision is high.
If the electronic device has both the second serial-to-parallel conversion interface and the first serial-to-parallel conversion interface, the frequencies of the first clock signal, the second clock signal and the third clock signal are different from each other. The parameters of the periodic signal can be measured according to actual precision requirements, and if the set precision is in a first set range, the external periodic signal is respectively input into the delay module and the trigger. And if the setting precision is in a second setting range, inputting an external periodic signal into the first serial-parallel conversion interface. And if the setting precision is in a third setting range, inputting an external periodic signal into the second serial-parallel conversion interface.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Referring to fig. 11, fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. The electronic device includes:
a clock module for providing a reference clock signal;
the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module consists of at least two delayers which are cascaded in front and back; the FPGA module is used for: acquiring an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the set precision; the set precision represents the measurement precision of the parameter of the external periodic signal; under the condition that the setting precision is in a first setting range, respectively inputting the external periodic signal into the delay module and the trigger to obtain an output signal of the trigger; each stage of delayer in the delay module sends a delay signal to a next stage of delayer and the trigger respectively; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal is used for representing the level state of the external periodic signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and a first clock signal; and the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
In practical applications, the electronic device may receive the external periodic signal through the buffer, and the FPGA module obtains the external periodic signal from the buffer.
Here, if the electronic device is a pulse laser, the external periodic signal may be a pulse signal input to the pulse laser.
The embodiment of the present invention corresponds to the above method embodiment, so the electronic device in fig. 11 is the electronic device in fig. 4.
Referring to fig. 12, in an embodiment, the FPGA module further includes a first serial-to-parallel conversion interface, and in a case that the setting precision is within a second setting range, the FPGA module is further configured to:
controlling the phase-locked loop to respectively generate the first clock signal and the second clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal have different frequencies;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the first parallel data and the second clock signal.
Referring to fig. 12, in an embodiment, the FPGA module further includes a second serial-to-parallel conversion interface, and in a case that the setting precision is within a third setting range, the FPGA module is further configured to:
controlling the phase-locked loop to respectively generate the first clock signal and the third clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal are different in frequency;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the second parallel data and the third clock signal.
The electronic device and the embodiment of the method for determining the parameter of the external periodic signal provided by the above embodiment belong to the same concept, and specific implementation processes thereof are detailed in the embodiment of the method and are not described herein again.
The electronic device further comprises a storage, which may be an internal storage unit of the electronic device, such as a hard disk or a memory of the electronic device. The memory may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Memory Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the electronic device. Further, the memory may also include both an internal storage unit and an external storage device of the electronic device. The memory is used for storing other programs and data required by the electronic equipment. The memory may also be used to temporarily store data that has been output or is to be output.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (9)
1. A parameter determination method of periodic signals is applied to electronic equipment, wherein the electronic equipment comprises a Field Programmable Gate Array (FPGA) module and a clock module, and the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module is composed of at least two cascaded delays, and is characterized in that the parameter determination method comprises the following steps:
receiving an external periodic signal;
determining configuration parameters of the phase-locked loop corresponding to the set precision; the set precision represents the measurement precision of the parameter of the external periodic signal;
under the condition that the setting precision is in a first setting range, respectively inputting the external periodic signal into the delay module and the trigger to obtain an output signal of the trigger; each stage of delayer in the delay module sends a delay signal to a next stage of delayer and the trigger respectively; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal is used for representing the level state of the external periodic signal;
determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and a first clock signal; and the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
2. The parameter determination method according to claim 1, wherein the FPGA module further includes a first serial-to-parallel conversion interface, and in a case where the setting accuracy is within a second setting range, the parameter determination method further includes:
controlling the phase-locked loop to respectively generate the first clock signal and the second clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal have different frequencies;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the first parallel data and the second clock signal.
3. The parameter determination method according to claim 1, wherein the FPGA module further includes a second serial-to-parallel conversion interface, and in a case where the setting accuracy is within a third setting range, the parameter determination method further includes:
controlling the phase-locked loop to respectively generate the first clock signal and the third clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal have different frequencies;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the second parallel data and the third clock signal.
4. The parameter determination method according to any one of claims 1 to 3, wherein the parameter of the external periodic signal includes at least any one of:
a period of the external periodic signal;
pulse width of the external periodic signal.
5. The method according to claim 1, wherein when determining the configuration parameters of the phase-locked loop based on the setting accuracy, the method further comprises:
controlling the phase-locked loop to generate the first clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module;
determining a number of delays in the delay module based on the frequency of the first clock signal.
6. The parameter determination method of claim 1, further comprising:
determining a current temperature of the FPGA module;
and determining the corresponding delay time of the delay module based on the current temperature.
7. An electronic device, comprising:
a clock module for providing a reference clock signal;
the FPGA module comprises a phase-locked loop, a delay module and a trigger; the delay module consists of at least two delayers which are cascaded in front and back; the FPGA module is used for: acquiring an external periodic signal; determining configuration parameters of the phase-locked loop corresponding to the set precision; the set precision represents the measurement precision of the parameter of the external periodic signal; under the condition that the setting precision is in a first setting range, respectively inputting the external periodic signal into the delay module and the trigger to obtain an output signal of the trigger; each stage of delayer in the delay module sends a delay signal to a next stage of delayer and the trigger respectively; the trigger generates an output signal according to the external periodic signal or the delay signal; the output signal is used for representing the level state of the external periodic signal; determining parameters of the external periodic signal based on the output signal, the delay time corresponding to the delayer and a first clock signal; and the first clock signal is generated by the phase-locked loop based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module.
8. The electronic device of claim 7, wherein the FPGA module further comprises a first serial-to-parallel conversion interface, and if the setting accuracy is within a second setting range, the FPGA module is further configured to:
controlling the phase-locked loop to respectively generate the first clock signal and the second clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the second clock signal; the first clock signal and the second clock signal have different frequencies;
sampling the external periodic signal based on the second clock signal to obtain first serial data;
converting the first serial data into first parallel data based on the first serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the first parallel data and the second clock signal.
9. The electronic device of claim 7, wherein the FPGA module further comprises a second serial-to-parallel conversion interface, and if the setting precision is within a third setting range, the FPGA module is further configured to:
controlling the phase-locked loop to respectively generate the first clock signal and the third clock signal based on the configuration parameters corresponding to the set precision and the reference clock signal provided by the clock module; the first clock signal is phase aligned with the third clock signal; the first clock signal and the third clock signal are different in frequency;
sampling the external periodic signal based on the third clock signal to obtain second serial data;
converting the second serial data into second parallel data based on the second serial-to-parallel conversion interface and the first clock signal;
determining a parameter of the external periodic signal based on the second parallel data and the third clock signal.
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