JP2000035463A - Jitter measuring device and integrated circuit incorporating the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a jitter measuring device capable of measuring the amount of jitter according to necessary measurement accuracy, without needing to measure the period of pulse signals and without limiting the number of pulses, and an integrated circuit incorporating the device. SOLUTION: A pulse signal 1, of which the amount of jitter is to be measured, is frequency-divided by an m-dividing circuit 13, then turned into an n-bit delay pulse by a pulse delay circuit 14, and given to an n-bit flip-flop 16 as a clock input. An output of the n-bit flip-flop 16 is stored in a first jitter- data latch circuit 17, and at the next time, new data are stored in the first jitter-data latch circuit 17 while data at the last time are shifted to a second jitter-data latch circuit 18. Data in the first and second jitter-data latch circuits 17, 18 are compared with each other by a jitter comparison circuit 19 and outputted via a parallel/serial conversion circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a jitter measuring apparatus for measuring a jitter amount of a pulse signal output from a PLL (phase control loop) circuit or the like.

[0002]

2. Description of the Related Art Such a jitter amount of a pulse signal is obtained, for example, by measuring the length (period) from the rising or falling edge of the pulse signal to the next corresponding edge over a plurality of periods. . The difference between the obtained minimum value and the maximum value of the period corresponds to the amount of jitter (see Japanese Patent Application Laid-Open No. 55-110454).

FIG. 7 shows a configuration of a conventional jitter amount measurement. Jitter amount measurement pulse signal 1 output from LSI (integrated circuit) semiconductor chip 30 including PLL circuit 11
The jitter is measured by the jitter measuring device 12, and the jitter measurement result 7 is output via the LSI tester 31.

FIG. 8 shows a concept of a conventional jitter amount measurement. The jitter amount measurement pulse signal 1 output from the PLL circuit 11 is a rectangular wave pulse as shown in the figure. The time (period) from the rise of this pulse signal to the next rise is measured by the pulse width measuring device 8 over a plurality of periods (for example, five periods 2 to 6 in FIG. 8). After the measurement data is once stored in the measurement data storage 9, the difference between the minimum value and the maximum value, that is, the jitter 7 is calculated by the calculator 10. Thus, the jitter measuring device 12 is configured by the pulse width measuring device 8, the measurement data storage 9, and the computing device 10.

[0005]

In the conventional jitter measuring apparatus as described above, the number of times (number of periods) for measuring the time from the rising of the pulse signal to the next rising.
Is actually measured over a larger number of cycles (hours) to increase the accuracy of the determination, rather than a small number such as 5 cycles.

However, as the number of times of measurement (the number of periods) increases, the storage capacity of the measurement data storage 9 (memory) for storing the measured periods becomes larger. Conversely, when the memory capacity of the measurement data storage 9 is limited, for example, when a jitter measuring device is built in an integrated circuit, the number of times of measurement (the number of periods) is limited. Difficult to raise.

Therefore, the present invention incorporates a jitter measuring apparatus capable of measuring the amount of jitter without the need to measure the period of the pulse signal and without limiting the number of pulses according to the required measurement accuracy, and a built-in jitter measuring apparatus. It is an object to provide an integrated circuit.

[0008]

SUMMARY OF THE INVENTION A jitter measuring apparatus according to the present invention includes a pulse delay circuit constituted by a buffer and a jitter comparison circuit. After a pulse signal whose jitter is to be measured is passed through the pulse delay circuit, the jitter is measured. The circuit compares the pulses before and after. This makes it possible to measure the amount of jitter without limitation on the number of pulses. In other words, it is not necessary to measure the pulse period, and the number of measurement pulses can be increased or decreased according to the required measurement accuracy. Further, by configuring the pulse delay circuit with a resistance element, the measurement resolution can be increased as compared with the case where the pulse delay circuit is configured with a buffer.

Further, the integrated circuit according to the present invention is characterized in that a circuit such as a PLL for outputting a pulse signal for which the amount of jitter needs to be measured and a jitter measuring apparatus having the above configuration are formed on the same semiconductor chip. Features. This provides an integrated circuit incorporating the jitter measuring device. as a result,
Jitter measurement can be performed without providing a jitter measuring device outside the integrated circuit.

Further, it is preferable that a process variation measuring circuit for measuring the variation of the diffusion process parameters of the semiconductor chip is also incorporated in the integrated circuit. According to this configuration, it is possible to adjust the jitter measurement accuracy in accordance with the variation in the diffusion process parameters of the semiconductor chip.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a block diagram of a jitter measuring apparatus according to a first embodiment of the present invention. In FIG. 1, the pulse signal 1 for measuring the amount of jitter is input to the jitter measuring device after being frequency-divided by the m-frequency dividing circuit 13. The jitter measuring device includes a pulse delay circuit 14 including a buffer, a process variation measuring circuit 15, an n-bit flip-flop circuit 1,
6, a first jitter information latch circuit 17, a second jitter information latch circuit 18, a jitter comparison circuit 19, and a parallel / serial conversion circuit 20. In the figure, reference numeral 21 denotes data, 22 denotes a jitter amount output, and 23 denotes a process variation result.

When the jitter amount measuring pulse signal 1 is frequency-divided by the m frequency dividing circuit 13 and input to the jitter measuring device, the signal is converted into an n-bit delayed pulse by the pulse delay circuit 14, and is converted into an n-bit flip-flop. To the clock 16 as a clock input. Also, 1-bit data 21 is externally input as the data input of the n-bit flip-flop 16. The output of the n-bit flip-flop 16 is stored in the first jitter information latch circuit 17.

Subsequently, the pulse to be measured is similarly input to the pulse delay circuit 14, and is similarly input as a clock input to the bit flip-flop 16 for processing the data 21. Then, the bit flip-flop 16
Is stored in the first jitter information latch circuit 17. At this time, the information previously stored in the jitter information latch circuit 17 is moved to and stored in the second jitter information latch circuit 18.

At this point, the jitter information for two pulses stored in the first and second jitter information latch circuits 17 and 18 is compared by the jitter comparison circuit 19, and the comparison result is compared with the parallel / serial conversion circuit 20. Is output as the jitter amount output 22.

This operation is sequentially performed for each pulse to be measured, and becomes a jitter amount output 22 when the data stored in the parallel / serial conversion circuit 20 is serially output.
In the jitter output 22, the value obtained by multiplying the number of H level outputs by the delay data of one buffer used in the pulse delay circuit 14 corresponds to the jitter amount of the jitter amount measurement pulse signal of 1.

The process variation measuring circuit 15
A process variation result 23 is output as information for externally monitoring delay information of a buffer used in the pulse delay circuit 14.

FIG. 2 is a circuit diagram of a usage example of the jitter measuring apparatus according to the embodiment of the present invention. FIG. 3 shows waveforms at various points in the circuit diagram of FIG. In FIG. 2, reference numeral 24 denotes a divide-by-4 circuit, 25 denotes a reset terminal, 26 denotes a parallel / serial conversion terminal, and 27 denotes a jitter amount.

The pulse signal 1 for measuring the amount of jitter is a pulse signal output from a PLL. It is applied to the clock input of bit flip-flop 16.

After the data 21 is once latched by the divide-by-4 clock, the n-bit flip-flop 16
Data input. As a result, the Q output of the n-bit flip-flop 16 is output as Q0 to Qn,
Is stored in the jitter information latch circuit 17.

Next, data 2 is added to the pulse signal to be measured.
1 is input, the same processing is performed, and the information of Q0 to Qn is stored in the first jitter information latch circuit 17. The signals Q0 to Qn from the previous jitter information latch circuit 17 move to the second jitter information latch circuit 18. The two pulse information of the first and second jitter information latch circuits 17 and 18 are compared by a jitter comparison circuit 19, and the comparison result is stored in a parallel / serial conversion circuit 20. At this time, if the comparison results are different, the H level is stored, and if they match, the L level is stored.

These operations are performed sequentially. If a mismatch occurs when compared by the jitter comparison circuit 19, the clocks of the first and second jitter information latch circuits 18 and 19 are stopped and the data is held. With this function, it is not necessary to provide the jitter information latch circuits as many as the number of measurement pulses, thereby suppressing an increase in circuit scale.

When the parallel / serial conversion terminal 26 is set at the L level after the necessary pulses are measured, the jitter output result 22 is output. By applying this to the equation (Equation 1) and calculating, the jitter amount Xps is calculated.

[0023]

Xps = buffer cell delay time × H of JUO
Number of levels For example, delay time of one buffer is 0.02 ns, JU
When the number of H levels of O is 3, the jitter amount is 0.02n
s × 3 = 0.06 ns.

With this configuration, there is no limitation on the number of pulse signals for measuring the amount of jitter, and the jitter can be measured with the required maximum accuracy. (Embodiment 2) FIG. 4 shows an example of a circuit including a jitter measuring apparatus according to a second embodiment of the present invention and its periphery. In this embodiment, a resistor is provided in the pulse delay circuit 14 in addition to the configuration of the first embodiment. With this resistor, the delay amount is subdivided to increase the jitter measurement accuracy.

In FIG. 4, the pulse delay circuit 28 is configured using a resistor. Compared to the pulse delay circuit 14 composed of the buffer shown in FIG. 2, a resolution in picoseconds is realized, and a more accurate jitter amount measurement becomes possible.

FIG. 5 shows a comparison of waveforms between a case where the pulse delay circuit is constituted by a buffer and a case where the pulse delay circuit is constituted by using a resistor. In FIG. 5, the difference between the two delay amounts is indicated by 29.

(Embodiment 3) In each of the above embodiments, the jitter measuring apparatus is described as an independent apparatus. However, in this embodiment, the jitter measuring apparatus is incorporated in an integrated circuit. The configuration in this case is shown in the block diagram of FIG. FIG.
, 30 is an LSI (integrated circuit) semiconductor chip, 1
1 is a PLL, 1 is a pulse signal for measuring a jitter amount, 12 is a jitter measuring device, 31 is an LSI tester, and 7 is a jitter measurement result.

First, the PLL 1 of the LSI semiconductor chip 30
1 outputs a pulse signal 1 for measuring the amount of jitter, which is input to a jitter measuring device 12 composed of a logic circuit.
The value measured by the jitter measuring device 12 is an LSI tester 31
After being calculated by the LSI tester 31, it is output as the jitter measurement result 7.

By converting the jitter measuring device 12 into a semiconductor and configuring it on the same semiconductor chip as a PLL circuit or the like that outputs a pulse signal whose jitter amount is to be measured, the chip area can be used effectively. Also, the jitter comparison circuit 1
Since the jitter measuring device 9 is used, the jitter measuring device 12 can be built in the integrated circuit without substantially affecting the entire chip area.

[0030]

As described above, the jitter measuring apparatus of the present invention has a pulse delay circuit and a jitter comparing circuit, so that the amount of jitter can be measured without limitation on the number of pulses according to the required measuring accuracy. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a jitter measuring apparatus according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an actual use example of the jitter measuring apparatus shown in FIG.

FIG. 3 is a diagram showing waveforms at various parts in the circuit diagram of FIG. 2;

FIG. 4 is a circuit diagram including the periphery of a jitter measuring apparatus according to a second embodiment of the present invention;

FIG. 5 is a diagram showing a comparison between waveforms in a case where the pulse delay circuit is configured with a buffer and in a case where the pulse delay circuit is configured with a resistor.

FIG. 6 is a block diagram of a jitter measuring apparatus according to a third embodiment of the present invention and an integrated circuit incorporating the same;

FIG. 7 is a diagram showing a configuration of a conventional jitter amount measurement.

FIG. 8 is a diagram showing a concept of a conventional jitter amount measurement.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 pulse signal for measuring amount of jitter 11 PLL circuit 12 jitter measuring device 13 m frequency dividing circuit 14 pulse delay circuit 15 process variation measuring circuit 16 n-bit flip-flop circuit 17, 18 jitter information latch circuit 19 jitter comparing circuit 20 parallel / serial conversion Circuit 21 Data 22 Jitter amount output 23 Process variation result 24 Divide-by-4 circuit 25 Reset terminal 26 Parallel / serial conversion terminal

Claims (4)

[Claims] 1. A pulse delay circuit comprising a buffer and a jitter comparison circuit, wherein a pulse signal whose jitter is to be measured is passed through the pulse delay circuit, and then the preceding and following pulses are compared by the jitter comparison circuit. A jitter measuring device capable of measuring the amount of jitter without limitation on the number of pulses. 2. A pulse delay circuit comprising a plurality of resistance elements and a jitter comparison circuit, wherein a pulse signal whose jitter is to be measured is passed through the pulse delay circuit, and the pulse comparison circuit compares the preceding and succeeding pulses. A jitter measuring device capable of measuring the amount of jitter without limitation on the number of pulses by performing 3. A jitter measuring apparatus characterized in that a circuit such as a PLL for outputting a pulse signal whose jitter amount needs to be measured and the jitter measuring apparatus according to claim 1 or 2 are formed on the same semiconductor chip. Integrated circuit. 4. The integrated circuit according to claim 3, further comprising a process variation measuring circuit for measuring a variation in a diffusion process parameter of the semiconductor chip.