JP2011226975A - Semiconductor device and control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which detects a jitter amount of an internal clock signal during actual operation and can output the detected jitter amount usably at the outside.SOLUTION: A semiconductor device comprises: a jitter detecting part for detecting a jitter component included in a clock signal based on a phase difference between the clock signal output by a clock generation circuit and a delay clock signal delayed by at least one period from the clock signal; an amplifying part having an amplifier circuit which converts the detected jitter component to a voltage signal; and a jitter output terminal for outputting the converted voltage signal to the outside.

Description

  The present invention relates to a semiconductor device and a control circuit that performs control to change the function and operating environment of the semiconductor device.

  There are various types of semiconductor devices such as ASIC (Application Specific IC), FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), etc. Here, these semiconductor devices are referred to as LSI (Large Scale IC). To do. The LSI includes a clock generation circuit that generates a clock signal to be supplied to a logic circuit. As a clock generation circuit, a PLL (Phase Locked Loop) circuit that generates a clock signal based on the output of a crystal oscillator is widely used.

  By the way, as shown in Patent Document 1, for example, a clock signal output from the PLL circuit includes jitter that is a temporal shift or fluctuation. When the amount of jitter of the clock signal output from the PLL circuit increases and deviates from the skew constraint of the logic circuit receiving the clock signal and the eye mask constraint of the transmission signal, a logic malfunction occurs.

  The jitter amount of the clock signal output from the PLL circuit varies mainly due to changes in the operating environment (power supply voltage and ambient temperature) of the PLL circuit. Therefore, conventionally, in order to suppress an increase in the amount of jitter that causes a logic malfunction, a device for keeping the operating environment of the PLL circuit constant has been made. Specifically, for example, a bypass capacitor or a PDN (Power Delivery / Distribution Network) is added as a measure for stabilizing the power fluctuation. Further, as a measure for stabilizing temperature fluctuation, for example, a high-capacity heat spreader is added.

JP 2007-17158 A

  However, the LSI targeted by the present invention is a general-purpose LSI whose usage environment is not fixed, and the above measures cannot be optimized in advance according to the environmental conditions during operation, so that it can cope with the worst operating environment. Redundant measures have been taken. Therefore, there is a problem that the environmental conditions for guaranteeing the operation are limited in accordance with the implemented measures.

  In order to be able to optimize the above measures according to the environmental conditions during operation, it is possible to measure the jitter amount inside the LSI during actual operation and observe the jitter amount measured inside the LSI so that it can be used externally. is required.

  As a method of detecting the amount of jitter, there are a method of measuring with a special LSI tester, a method of measuring a sample with a test bench, and a method of self-testing with built-in jitter measurement in a dedicated circuit (Built-in which embeds the Self Test circuit) Three methods are known: In method: BIST).

  However, the measurement of the tester and the sample is used for evaluating the performance quality of the LSI alone, and the jitter amount cannot be measured in an actual operating environment in which the LSI is incorporated in the product device. In addition, although BIST detects jitter inside the LSI, it only provides a result for a self-test item, and there is a problem that the amount of jitter cannot be observed externally.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a semiconductor device capable of detecting the jitter amount of an internal clock signal during actual operation and outputting the detected jitter amount so as to be usable externally.

  Further, the present invention provides a control circuit capable of performing control to change the operating environment so as to reduce the jitter amount indicated by the output of the semiconductor device according to the above invention and control to change the function of the semiconductor device in accordance with the jitter amount. The purpose is to obtain.

  In order to achieve the above-described object, the present invention provides a semiconductor device having a clock generation circuit that generates a clock signal to be supplied to a logic circuit, the clock signal output from the clock generation circuit, and at least the clock signal. A jitter detector for detecting a jitter component included in the clock signal based on a phase difference from a delayed clock signal delayed by one cycle; an amplifier having an amplifier circuit for converting the detected jitter component into a voltage signal; And a jitter output terminal for outputting the converted voltage signal to the outside.

  According to the present invention, it becomes possible to observe the jitter amount in an actual operating environment of a general-purpose semiconductor device whose use environment is not determined in real time outside the semiconductor device. As a result, the jitter amount can be easily measured even if it is incorporated in a product device, so it is not necessary to rely on the jitter analysis function of an expensive high-speed oscilloscope. There is an effect that analysis becomes possible.

FIG. 1 is a block diagram showing a conceptual configuration of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a block diagram illustrating a specific configuration example of the semiconductor device illustrated in FIG. 1. FIG. 3 is a circuit diagram showing a configuration example of the phase comparison circuit shown in FIG. FIG. 4 is a circuit diagram showing a configuration example of the integrating circuit shown in FIG. FIG. 5 is a waveform diagram for explaining the operation of the jitter detector. FIG. 6 is a block diagram illustrating a configuration example of a control circuit that suppresses power supply fluctuation as the control circuit according to the second embodiment of the present invention. FIG. 7 is a block diagram showing a configuration example of a control circuit that suppresses temperature fluctuations as a control circuit according to the second embodiment of the present invention. FIG. 8 is a block diagram illustrating a configuration example of a control circuit that performs jitter suppression and function change as the control circuit according to the second embodiment of the present invention.

  Embodiments of a semiconductor device and a control circuit according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a conceptual configuration of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, a semiconductor device (LSI) 1 according to this embodiment is, for example, an FPGA.

First, a general LSI configuration will be described.
An LSI generally includes a logic circuit 2 and a PLL circuit 3 that supplies a clock signal CLK to the logic circuit 2 as internal circuits. As external input / output pins, a power supply pin 4, a reference clock input pin 5, a ground pin 6, a data input pin 7, a data output pin 8, a data input / output pin 9 and the like are provided in the package.

  A power supply VDD that supplies power to the PLL circuit 3 is connected to the power supply pin 4. In FIG. 1, a power supply pin to which a power supply for supplying power to the logic circuit 2 is connected is not shown. This is because this embodiment makes the PLL circuit 3 a problem.

  A reference clock signal Xin supplied from a crystal oscillator (not shown) to the PLL circuit 3 is input to the reference clock input pin 5. The ground terminal of the PLL circuit 3 is connected to the ground of the circuit board on which the LSI 1 is mounted via the ground pin 6. The ground terminal of the logic circuit 2 is also connected to the ground of the circuit board on which the LSI 1 is mounted in the same manner. The logic circuit 2 uses the data input pin 7, the data output pin 8, and the data input / output pin 9 to exchange data with the outside.

  The LSI 1 according to this embodiment is provided with a jitter detection unit 10 and an amplification unit 11 as internal circuits in an LSI having such a general configuration, and a jitter output pin 12 provided as a package as an external input / output pin. is there.

The jitter detector 10 detects a jitter component included in the clock signal CLK based on the phase difference between the clock signal CLK output from the PLL circuit 3 and a delayed clock signal obtained by delaying the clock signal CLK by at least one cycle. .
The amplifying unit 11 includes an amplifying circuit 11a that converts the detected jitter component into a voltage signal, and outputs the converted voltage signal (jitter value) from the jitter output pin 12 to the outside.

The jitter detector 10 and the amplifier 11 can be configured as shown in FIG. 2, for example. FIG. 2 is a block diagram illustrating a specific configuration example of the semiconductor device illustrated in FIG. 1.
First, the jitter detector 10 will be described. In FIG. 2, the jitter detection unit 10 includes a delay circuit 14, a phase comparison circuit 15, and an integration circuit 16. The phase comparison circuit 15 is configured, for example, as shown in FIG. For example, the integration circuit 16 is configured as shown in FIG.

The delay circuit 14 generates a delayed clock signal DCLK obtained by delaying the clock signal CLK output from the PLL circuit 3 by at least one cycle.
In FIG. 3, the phase comparison circuit 15 includes flip-flop circuits 25 and 26, exclusive OR circuits 27 and 28, and an adder / subtractor 29.

  The flip-flop circuit 25 takes in the delayed clock signal DCLK input to the data input terminal D at the rising edge of the clock signal CLK output from the PLL circuit 3 input to the clock input terminal.

  A logically inverted clock signal / CLK obtained by logically inverting the clock signal CLK output from the PLL circuit 3 is input to the clock input terminal of the flip-flop circuit 26, and the data output terminal Q of the flip-flop circuit 25 is connected to the data input terminal. Has been. That is, the flip-flop circuit 26 captures the delay data captured by the flip-flop circuit 25 at the rising edge of the previous clock signal CLK at the rising edge of the logically inverted clock signal / CLK.

  The exclusive OR circuit 27 takes an exclusive OR of the delayed clock signal DCLK and the data fetched by the flip-flop circuit 25 and outputs it to the addition input terminal (+) of the adder / subtractor 29. The exclusive OR circuit 28 takes an exclusive OR of the data fetched by the flip-flop circuit 25 and the delayed data fetched by the flip-flop circuit 26 and outputs it to the subtraction input terminal (−) of the adder / subtractor 29. As a result, the phase difference ΔJ between the clock signal CLK and the delayed clock signal DCLK is output from the adder / subtractor 29 in such a manner that the time width is increased or decreased by the jitter present in the clock signal CLK. That is, the phase difference ΔJ represents the amount of change in jitter present in the clock signal CLK.

  Further, the integrating circuit 16 is configured using an OP amplifier 31 in FIG. In the OP amplifier 31, the non-inverting input terminal (+) is connected to the ground, and the phase difference ΔJ detected by the phase comparison circuit 15 is input to the inverting input terminal (−) via the resistor 32. A capacitor 33 and a resistor 34 are provided in parallel between the inverting input terminal (−) and the output terminal.

  Next, FIG. 5 is a waveform diagram for explaining the operation of each part of the jitter detector. In FIG. 5, when the delayed clock signal DCLK (FIG. 5 (2)) output from the delay circuit 14 is delayed by one cycle of the clock signal CLK (FIG. 5 (1)) output from the PLL circuit 3, The phase difference ΔJ (FIG. 5 (3)) detected by the comparison circuit 15 is determined based on the current clock signal CLK (FIG. 5 (1)) and the delayed clock signal DCLK one clock earlier (FIG. 5 (2)). ) Is an amount of change in jitter since it is the time width of the clock pulse increased or decreased by one clock. Therefore, if the change amount of the jitter, which is the phase difference ΔJ (FIG. 5 (3)) detected by the phase comparison circuit 15, is integrated by the integration circuit 16, the jitter amount J (FIG. 5 (4)) is obtained. .

  Next, returning to FIG. 2, the amplifying unit 11 will be described. The amplification circuit 11a included in the amplification unit 11 may have a fixed gain, but FIG. 2 shows an amplification circuit 17 with a gain control function. In addition, the amplifying unit 11 can be provided with a band filter between the amplifier circuit and the jitter output pin 12. The band filter may be a fixed band, but FIG. 2 shows a band filter 18 with a band control function. When one or both of the amplifier circuit 17 with gain control function and the band filter 18 with band control function are provided, a control register 20 is prepared in the logic circuit 2. That is, the gain control function-equipped amplification circuit 17 and the band control function-equipped band-pass filter 18 are controlled by the control values set in the register 20 at predetermined time intervals according to the data rate handled in the input / output processing in the logic circuit 2. The gain and bandwidth are variably controlled.

  That is, the jitter amount J detected by the jitter detector 10 is a voltage signal having a jitter value Vj in the “amplifier 11 composed of an amplifier circuit” or “amplifier 11 composed of an amplifier circuit and a bandpass filter”. And output from the jitter output pin 12 to the outside.

  As described above, according to the first embodiment, the LSI includes a jitter detection unit that detects clock jitter and an amplification unit that outputs the jitter amount as a voltage signal to the outside of the LSI. The jitter amount in the actual operating environment of a general-purpose LSI that cannot be determined can be observed in real time outside the LSI.

  Therefore, even if it is built in a product device, the amount of jitter can be measured easily, so that it is possible to analyze the cause of malfunction caused by jitter with an inexpensive spectrum analyzer, etc. without relying on the jitter analysis function of an expensive high-speed oscilloscope. Is possible.

  Further, if the amplifier circuit included in the amplifier unit is an amplifier circuit with a gain control function, a voltage value suitable for an observation circuit connected outside the LSI can be output. If the band filter is provided in the amplifying unit, it is possible to output jitter information only in the frequency range desired to be detected by the observation circuit connected to the outside of the LSI. This band filter can also have a band control function. As a result, the versatility of the interface with the observation circuit connected to the outside of the LSI can be enhanced.

Embodiment 2. FIG.
In the second embodiment, referring to FIGS. 6 to 8, control for changing the operating environment (power supply voltage, ambient temperature) so as to reduce the jitter amount indicated by the LSI output described in the first embodiment. A control circuit capable of controlling the function of the LSI according to the jitter amount will be described. 6 to 8, only the amplification circuit 17 with a gain control function is shown as the amplification unit 11 in the LSI 1 shown in FIG.

  FIG. 6 is a block diagram illustrating a configuration example of a control circuit that suppresses power supply fluctuation as the control circuit according to the second embodiment of the present invention. In FIG. 6, a power supply VDD supplied to the voltage regulator 35 serving as a control circuit indicates a branch power supply that branches from the common power supply of the LSI 1 and supplies power to the PLL circuit 3.

  The voltage regulator 35 is provided in the power supply path from the branch power supply VDD to the power supply pin 4, the jitter output pin 12 is connected to the control terminal thereof, and the jitter value detected inside the LSI 1 is reduced. The power supply voltage supplied to the PLL circuit 3 is controlled.

  Next, FIG. 7 is a block diagram showing a configuration example of a control circuit that suppresses temperature fluctuations as a control circuit according to the second embodiment of the present invention. In FIG. 7, a Peltier cooler 37 as a cooling means is attached to the back surface of the circuit board on which the LSI 1 is mounted. The temperature regulator 38, which is a control circuit, has a jitter output pin 12 connected to its control terminal, and controls the voltage applied to the Peltier cooler 37 so as to reduce the jitter value detected inside the LSI 1. In addition, as a cooling means, it may replace with the Peltier cooler 37 and the fan cooler etc. which blow cool air to LSI1 may be used.

  Next, FIG. 8 is a block diagram illustrating a configuration example of a control circuit that performs jitter suppression and function change as the control circuit according to the second embodiment of the present invention. In FIG. 8, the control circuit includes a voltage regulator 35, a temperature regulator 38, and a microcomputer 39.

  The voltage regulator 35 is provided in the power supply path from the branch power supply VDD to the power supply pin 4, and controls the power supply voltage supplied to the PLL circuit 3 in accordance with an operation command input from the microcomputer 39 to its control terminal.

  The temperature regulator 38 controls the voltage applied to the Peltier cooler 37 in accordance with an operation command input from the microcomputer 39 to its control terminal. In addition, as a cooling means, it may replace with the Peltier cooler 37 and the fan cooler etc. which blow cool air to LSI1 may be used.

  The microcomputer 39 has the jitter output pin 12 connected to the AD conversion port, and outputs an operation command to one or both of the voltage regulator 35 and the temperature regulator 38 so as to reduce the jitter value detected inside the LSI 1.

  Further, a function control pin 40 used for function control of the LSI 1 is provided in the LSI 1 package. In the process of outputting the operation command to the voltage regulator 35 and the temperature regulator 38 so as to reduce the jitter value detected inside the LSI 1, the microcomputer 39 determines the jitter value detected inside the LSI 1 and the logic circuit 2. A function stop signal for stopping at least a part of the functions of the LSI 1 according to the relationship with the noise margin is output to the logic circuit 2 via the function control pin 40.

  Further, in the configuration shown in FIG. 8, when the control circuit is configured only by the microcomputer 39, the microcomputer 39 determines the LSI 1 according to the relationship between the jitter value detected inside the LSI 1 and the noise margin of the logic circuit 2. A function stop signal for stopping at least a part of the functions is output to the logic circuit 2 via the function control pin 40.

  As described above, according to the second embodiment, when the generation factor of the jitter existing in the output clock of the PLL circuit is a change in the power supply voltage supplied to the PLL circuit or a change in the ambient temperature of the LSI, those operating environments Therefore, it is possible to optimize the operating environment according to the detected amount of jitter during operation and to prevent the occurrence of logic malfunctions. become.

  In addition, since the function of the LSI can be limited according to the relationship between the detected jitter amount during operation and the noise margin of the logic circuit, it is subject to the limit conditions that ensure a marginal noise margin that does not cause a logic malfunction. Thus, the use of the LSI can be continued.

  As described above, the semiconductor device according to the present invention is useful as a semiconductor device capable of detecting the jitter amount of the internal clock signal during actual operation and outputting the detected jitter amount so as to be usable externally.

  In addition, the control circuit according to the present invention performs control for changing the operating environment so as to reduce the jitter amount indicated by the output of the semiconductor device according to the present invention, and control for changing the function of the semiconductor device in accordance with the jitter amount. It is useful as a control circuit that can be used.

1 LSI (semiconductor device)
2 logic circuit 3 PLL circuit (clock generation circuit)
DESCRIPTION OF SYMBOLS 4 Power supply pin 10 Jitter detection part 11 Amplification part 11a Amplification circuit 12 Jitter output pin 14 Delay circuit 15 Phase comparison circuit 16 Integration circuit 17 Amplification circuit with a gain control function 18 Band-pass filter with a band control function 35 Voltage regulator (control circuit)
37 Peltier cooler (cooling means)
38 Temperature regulator (control circuit)
39 Microcomputer (microcomputer: control circuit)
40 Function control pin

Claims (10)

In a semiconductor device having a clock generation circuit that generates a clock signal to be supplied to a logic circuit,
A jitter detector that detects a jitter component included in the clock signal based on a phase difference between a clock signal output from the clock generation circuit and a delayed clock signal obtained by delaying the clock signal by at least one cycle;
An amplification unit having an amplification circuit for converting the detected jitter component into a voltage signal;
And a jitter output terminal for outputting the converted voltage signal to the outside. The amplification unit is
The semiconductor device according to claim 1, further comprising: a band filter that limits a band of the voltage signal generated by the amplifier circuit and outputs the voltage signal to the jitter output terminal.   3. The amplifier circuit according to claim 1, wherein the amplifier circuit is an amplifier circuit having a fixed gain, or an amplifier circuit having a gain control function in which a gain is controlled based on a gain control value generated by the logic circuit. The semiconductor device described.   4. The band filter according to claim 2, wherein the band filter is a band filter having a fixed band or a band filter with a band control function in which a band is controlled based on a band control value generated by the logic circuit. The semiconductor device described. A control circuit that receives a voltage signal output to the jitter output terminal of the semiconductor device according to claim 1,
A control circuit for controlling an operating environment of the semiconductor device so as to reduce a jitter amount indicated by the voltage signal. The control circuit includes:
The control circuit according to claim 5, wherein the control circuit is a voltage regulator that controls a power supply voltage supplied to a clock generation circuit of the semiconductor device so as to reduce an amount of jitter indicated by the voltage signal. The control circuit includes:
6. The control circuit according to claim 5, wherein a cooling unit that cools the semiconductor device is a temperature regulator that controls the amount of jitter indicated by the voltage signal to be reduced. The control circuit includes:
A voltage regulator that controls a power supply voltage that supplies power to the clock generation circuit of the semiconductor device;
A temperature regulator that controls cooling means for cooling the semiconductor device;
The control circuit according to claim 5, further comprising: a microcomputer that outputs an operation command to one or both of the voltage regulator and the temperature regulator so as to reduce an amount of jitter indicated by the voltage signal. .   The microcomputer performs control to stop at least a part of functions of the semiconductor device in accordance with a relationship between a jitter amount indicated by the voltage signal and a noise margin of a logic circuit of the semiconductor device. The control circuit according to claim 8. A control circuit that receives a voltage signal output to the jitter output terminal of the semiconductor device according to claim 1,
A control circuit that performs control to stop at least a part of functions of the semiconductor device in accordance with a relationship between a jitter amount indicated by the voltage signal and a noise margin of a logic circuit of the semiconductor device.

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