JP2004085236A - Jitter testing circuit, semiconductor device mounting the same, and jitter testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a jitter testing circuit that can accurately measure the amount of jitters, without being affected by the manufacturing factors or the usage environment, and is composed of a digital circuit that is strong with respect to noise. <P>SOLUTION: In calibration phases, a test control circuit 12 controls delay in signals in a window signal generating circuit 11 for adjustment so that a signal change edge in a clock signal DCLK for comparison that is the output of the window signal generation circuit 11 coincides with the center of a window in a window signal WS, that is generated by DCLK being delayed by one period. In the quality decision of jitter, the test control circuit 12 controls delay in signals in the window signal generating circuit 11 for setting the window width to a jitter specification value, thus detecting whether the signal change edge in the clock signal DCLK for comparison is within the window by a comparison circuit 13. When the signal change edge does not lie within the window, it is decided as being defective. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a jitter test, and more particularly, to a jitter test circuit for detecting a jitter of a timing signal such as a clock signal that periodically repeats a high level and a low level, a semiconductor device equipped with the jitter test circuit, and a jitter test method.
[0002]
[Prior art]
A PLL (Phase-Locked Loop) circuit is widely used as a circuit for generating a reference frequency such as a clock signal of a microprocessor or a local oscillation signal of a wireless device. As is well known, a PLL circuit compares a reference timing signal (for example, an external input clock signal) with a PLL output timing signal (for example, a clock signal supplied to the inside of a semiconductor device) and has a phase difference. In such a case, the operation is performed so as to match the phases.
[0003]
Generally, a timing signal such as a clock signal output from a PLL circuit that periodically repeats a high level and a low level includes jitter that is a temporal fluctuation of the signal. In a digital logic circuit or the like to which a clock signal is supplied, since jitter causes a malfunction, it is necessary to measure the jitter value of the clock signal and to control the jitter to a certain value or less.
[0004]
An example of a test circuit for measuring jitter is described in JP-A-2001-166007. FIG. 29 is a block diagram of a first conventional example of a jitter test circuit.
[0005]
In FIG. 29, the clock signal CLK output from the PLL circuit and the delayed clock signal DF passed through the reference delay circuit 171 are compared by a comparison circuit 172, and for example, a delay difference signal DK which becomes high level during a period corresponding to the delay difference Is output. The jitter detection circuit 173 calculates a jitter value from the high-level fluctuation width of the delay difference signal DK, and outputs a defective signal NG when the jitter value is larger than the jitter standard value JS.
[0006]
However, in the first conventional example of FIG. 29, since the delay value of the reference delay circuit 171 changes due to manufacturing factors and use environment, the jitter value is calculated from the ratio between the high level width of the delay difference signal DK and the fluctuation width due to jitter. In this case, there is a problem that an accurate jitter value cannot be calculated.
[0007]
As a method of measuring the pulse width, a technique of counting the number of sampling pulses included in the pulse width to be measured using a sampling signal having a period smaller than the pulse width to be measured is described in JP-A-62-131637. I have. This technique is applied to the jitter detection circuit 173 of the first conventional example, and a signal having a constant frequency is externally supplied as a sampling signal. Measurement can be performed without being affected by the environment. However, when the jitter test circuit is configured in this manner, a new problem arises in that the jitter value can be measured only in units of the period of the sampling signal, and can be measured only with rough accuracy.
[0008]
On the other hand, Japanese Patent Application Laid-Open No. 2001-166007 discloses a second conventional example in which the accuracy of jitter measurement is improved by calibrating a change in a delay value of a delay circuit due to a manufacturing factor or a use environment. I have. FIG. 30 is a block diagram of a second conventional example.
[0009]
In FIG. 30, the delay circuit in the measuring section 181 and the voltage controlled oscillator (VCO) in the calibrating section 182 have the same configuration except that the output is fed back to the input. The delay value of the circuit and the oscillation period of the VCO change simultaneously and similarly. In the jitter test circuit of FIG. 30, the calibration of the delay circuit is performed prior to the jitter measurement. When the external calibration signal CG is selected by the selector of the calibration unit 182 and supplied to the VCO as the control signal CD, the VCO outputs an oscillation signal PO having a frequency based on the voltage value of the control signal CD. On the other hand, an analog / digital converter (A / D) in the calibration unit 182 converts the control signal CD from analog to digital, and outputs a digital control signal DC. The VF measurement circuit 24 in the calibration unit 182 measures a VF characteristic which is a relationship between a voltage of the control signal CD corresponding to the digital control signal DC and a frequency of the oscillation signal PO, and outputs a delay calibration signal VF.
[0010]
In the jitter measurement, the selector of the calibration unit 182 selects the delay value detection signal CS from the measurement unit 181 as the control signal CD. When measuring the jitter, the measuring unit 181 compares the phase of the clock signal CLK with the phase of the delay signal DV passed through the delay circuit, and outputs a DC voltage corresponding to the phase shift from the charge pump as the delay value detection signal CS. The delay value detection signal CS is output from the selector as a control signal CD and supplied to the A / D. The A / D converts the voltage value of the control signal CD into a digital signal and sends the digital signal as a digital detection signal DS to the delay value detection circuit in the jitter calculator 183.
[0011]
The delay value detection circuit receives the supply of the digital detection signal DS, and based on the delay calibration signal VF supplied in advance, the maximum delay value MAX and the minimum delay value of the delay signal DV of the delay circuit DV in the measurement unit 181 represented by the digital detection signal. The value MIN is detected, and each of the maximum delay value MAX and the minimum delay value MIN is supplied to an arithmetic circuit in the jitter calculator 183. The arithmetic circuit calculates a jitter value DT which is a delay difference between the maximum delay value MAX and the minimum delay value MIN, and supplies the jitter value DT to the comparison circuit. The comparison circuit compares the supplied jitter value DT with the standard value JS, and outputs a defective signal NG when the jitter value DT exceeds the standard value JS.
[0012]
As described above, in the second conventional example, the VF characteristic, which is the relationship between the voltage of the calibration signal CG and the frequency of the oscillation signal PO, is measured in the calibration mode, and the delay calibration signal VF corresponding to the VF characteristic is measured. Is measured in the jitter measurement mode based on the delay calibration signal VF, and the jitter value is calculated from the maximum value and the minimum value of the clock signal CLK. Since the change in the delay amount of the circuit is calibrated, more accurate jitter measurement can be performed as compared with the first conventional example.
[0013]
[Problems to be solved by the invention]
However, in the second conventional example, a low-pass filter is built in a charge pump in the measuring section 181 and an analog-digital converter is required in the calibrating section. These circuits are sensitive to noise because they handle analog voltages, and their layout must be devised so as not to be affected by noise from surrounding digital circuits, which complicates the design. Also, in addition to the area occupied by the element circuits that constitute each of the measurement unit, calibration unit, and jitter calculation unit, an area is required to isolate the low-pass filter and analog-to-digital conversion circuit from noise from the surroundings. The second conventional example requires a large occupied area.
[0014]
The present invention has been made in view of such a situation, and an object of the present invention is to measure the amount of jitter accurately without being affected by manufacturing factors and use environment as in the second conventional example. An object of the present invention is to provide a jitter test circuit which is configured by a digital circuit, can be designed more easily than the second conventional example, and can be realized with a small occupied area, a semiconductor device equipped with the jitter circuit, and a jitter test method.
[0015]
[Means for Solving the Problems]
A jitter test circuit according to a first aspect of the present invention is a jitter test circuit for detecting a jitter of a timing signal that periodically alternates between a high level and a low level. The delay control information designated as is input, and the comparison timing signal generated by delaying the timing signal by a first time based on the delay control information and the signal obtained by delaying the timing signal by a second time A window signal generation circuit for generating and outputting a window signal provided with a window having a predetermined signal level within a third time width before and after the rising point and the falling point, and the comparison timing signal; And the window signal, and the rising and falling points of the comparison timing signal are C) a comparison circuit for detecting whether or not the data is in the memory, and outputting a comparison result; and inputting a command including an operation mode designation and the comparison result to control generation of the delay control information and execution of a test operation to perform calibration. In the operation mode, the second time is searched for delay control information that is equal to a time obtained by adding one cycle of the timing signal when the first time has no jitter. And a test control circuit for setting the second time based on the delay control information searched in the step, setting the third time to a jitter standard value, and judging pass / fail based on a comparison result from the comparison circuit. Is done. Further, in the calibration mode, the test control circuit sets the second time to a time longer than a time obtained by adding the first time and the third time to one cycle of the timing signal. After the control information is initialized, the delay control information is manipulated to gradually reduce the delay time of the second time in increments of a basic delay unit while monitoring the comparison result from the comparison circuit, and when there is no jitter. Searching for delay control information corresponding to the second time when the rising point and the falling point of the comparison timing signal are located at the center of the window; and in the pass / fail judgment mode, search in the calibration mode. The second time is set based on the received delay control information, the delay control information is generated based on a command input from the outside, and the jitter standard value is set. The third time is set, a plurality of comparison results of the comparison circuit are taken in, and the number of comparison results indicating the deviation of the rising point and the falling point of the comparison timing signal from the window is equal to or more than a predetermined number. May be determined to be defective when.
[0016]
A jitter test circuit according to a second aspect of the present invention is a jitter test circuit for detecting a jitter of a timing signal that periodically alternates between a high level and a low level. The delay control information designated as is input, and the comparison timing signal generated by delaying the timing signal by a first time based on the delay control information and the signal obtained by delaying the timing signal by a second time A window signal generation circuit for generating and outputting a window signal provided with a window having a predetermined signal level within a third time width before and after the rising point and the falling point, and the comparison timing signal; And the window signal, and the rising and falling points of the comparison timing signal are C) a comparison circuit for detecting whether or not the data is in the memory, and outputting a comparison result; and inputting a command including an operation mode designation and the comparison result to control generation of the delay control information and execution of a test operation to perform calibration. In the case of the jitter mode, the second time is searched for delay control information which is equal to the time obtained by adding one cycle of the timing signal when the first time has no jitter. A test control circuit that sets the second time based on the delay control information searched in and determines a jitter value based on a result of comparing the plurality of times by changing the third time by the comparison circuit; A coding circuit for generating and outputting coded jitter information from the jitter value determined by the test control circuit and the delay control information; It is. Further, in the calibration mode, the test control circuit sets the second time to an initial time larger than a time obtained by adding the first time and the third time to one cycle of the timing signal. After setting the delay control information, monitor the comparison result from the comparison circuit while operating the delay control information to gradually reduce the delay time of the second time in increments of a basic delay unit, and when there is no jitter. Searching for delay control information corresponding to the second time when the rising point and the falling point of the comparison timing signal are located at the center of the window, and searching in the calibration mode in the jitter measurement mode. The second time is set based on the delay control information obtained, and the third time is controlled by the delay control information to change the width of the window. It may be configured to determine a comparison result with the jitter value from the delay control information corresponding to a third time threshold value determination changes from good to monitor in correspondence to a defective of said comparator circuit while.
[0017]
According to a third aspect of the present invention, there is provided a test circuit for detecting a jitter in a timing signal output from a clock recovery PLL circuit which inputs a data signal, extracts a timing signal synchronized with the data signal, and reproduces the timing signal. In the test circuit, the timing signal and delay control information for designating the delay time as the number of basic delay units are input, and a comparison signal generated by delaying the timing signal by a first time based on the delay control information is generated. A timing signal and a window signal having a window having a predetermined signal level with a third time width before and after a rising point and a falling point of a signal obtained by delaying the timing signal by a second time. A window signal generation circuit for generating and outputting the comparison timing signal and the window signal; A comparison circuit for detecting whether a rising point and a falling point of the comparison timing signal are within the window and outputting a comparison result; and a data signal having the same sign in the data signal continuously for a predetermined number of data or more. The same-code continuous data detection circuit that outputs the same-code continuous data detection signal when detecting that the operation has been performed, and inputs the command including the operation mode designation and the comparison result to generate the delay control information and execute the test operation In the calibration mode, the second time is searched for delay control information equal to a time obtained by adding one cycle of the timing signal when there is no jitter in the first time. Sometimes, the second time is set based on the delay control information searched in the calibration mode, and the third time is skipped. The comparison result from the comparison circuit sets the standard value constituted and a determining test control circuit acceptability. Further, in the calibration mode, the test control circuit sets the second time to an initial time larger than a time obtained by adding the first time and the third time to one cycle of the timing signal. After setting the delay control information, monitor the comparison result from the comparison circuit while operating the delay control information to gradually reduce the delay time of the second time in increments of a basic delay unit, and when there is no jitter. Searching for delay control information corresponding to the second time when the rising point and the falling point of the comparison timing signal are located at the center of the window; and in the pass / fail judgment mode, search in the calibration mode. The second time is set based on the received delay control information, the delay control information is generated based on a command input from the outside, and the jitter standard value is set. The third time is set, a plurality of comparison results of the comparison circuit are taken in, and the number of comparison results indicating the deviation of the rising point and the falling point of the comparison timing signal from the window is equal to or more than a predetermined number. May be determined to be defective when.
[0018]
A semiconductor device according to a fourth aspect of the present invention includes one of the jitter test circuit according to the first aspect, the jitter test circuit according to the second aspect, and the jitter test circuit according to the third aspect. It is characterized by: A divider circuit may be mounted to input the output of the divider circuit to the jitter test circuit, or a PLL circuit may be mounted to input the output of the PLL circuit to the jitter test circuit, or A multiplication PLL circuit may be mounted to input the output of the multiplication PLL circuit to the jitter test circuit, or a clock recovery PLL circuit may be mounted to input the output of the clock recovery PLL circuit to the jitter test circuit. You may.
[0019]
A jitter test method according to a fifth aspect of the present invention is the jitter test method for detecting the jitter of a timing signal that periodically alternates between a high level and a low level, wherein the jitter signal is generated by delaying the timing signal to be measured. When the rising point and the falling point of the comparison timing signal have no jitter, the number of basic delay units of the delay circuit is adjusted so as to be located at the center of a window having a predetermined width provided for each. A calibration phase for deciding the position of the window, and comparing a window provided at the position adjusted in the calibration phase with a rising point and a falling point of the comparison timing signal a plurality of times, and calculating a rising point or a falling point. Is determined to be outside the window of the predetermined width. Number of times is characterized by comprising a failure and determining quality determination phase in the case where a predetermined number of times or more.
[0020]
A jitter test method according to a sixth aspect of the present invention is the jitter test method for detecting a jitter of a timing signal that periodically alternates between a high level and a low level, wherein the jitter signal is generated by delaying the timing signal to be measured. When the rising point and the falling point of the comparison timing signal have no jitter, the number of basic delay units of the delay circuit is adjusted so as to be located at the center of a window having a predetermined width provided for each. The calibration phase for determining the position of the window, and the rising and falling points of the comparison timing signal and the window adjusted in the calibration phase are changed by changing the width on both sides with respect to the center of the window. A comparison is made multiple times while changing the width The detecting window width is characterized in that it comprises a jitter measurement phase to output the determined coding jitter value.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Note that the following description shows typical embodiments of the present invention, and the present invention is not construed as being limited to the following description.
[0022]
FIG. 1 is a diagram schematically showing a semiconductor device equipped with a jitter test circuit of the present invention. The semiconductor device 200 includes a jitter test circuit 1, a PLL circuit 2, and an internal circuit 3.
[0023]
The PLL circuit receives an input clock signal ICLK as a reference timing signal from the outside and outputs a clock signal CLK as a timing signal synchronized with the input clock signal ICLK.
[0024]
The internal circuit 3 is a digital logic circuit that operates in synchronization with the clock signal CLK, and performs digital logic operation on the input data IDAT to output output data ODAT.
[0025]
The jitter test circuit 1 receives a clock signal CLK and operates in a calibration mode or a pass / fail judgment mode in accordance with an externally input command CMD. In the calibration mode, the jitter test circuit 1 calibrates a delay value of a delay circuit inside the jitter test circuit 1, In the pass / fail judgment mode, the jitter is compared with a jitter standard value JS specified by a command CMD from outside, and a judgment result signal JDG is output.
[0026]
FIG. 2 is a block diagram of one embodiment of the jitter test circuit of the present invention. The jitter test circuit 1a includes a window signal generation circuit 11, a test control circuit 12, and a comparison circuit 13.
[0027]
The window signal generation circuit 11 receives the clock signal CLK and the delay control information DINF, and based on the delay control information DINF, delays the clock signal by the first time D1 and generates a comparison clock signal DCLK and a clock signal. The third time before and after the rising and falling points of the signal obtained by delaying the CLK by (D2−D3) obtained by subtracting the third time D3 from the second time D2 to the first time D1. A window signal WS provided with a window having a predetermined signal level with a width of D3 is generated and output.
[0028]
The window signal generation circuit 11 receives the clock signal CLK and delays it by a time obtained by subtracting the third time D3 from the second time D2, as shown in the window signal generation circuit 11a of FIG. A first variable delay circuit 21 that outputs the generated first delay signal T1, and a second delay signal that is generated by inputting the first delay signal T1 and delaying it by twice the third time D3 A second variable delay circuit 22 for outputting T2, an exclusive OR circuit 23 for receiving the first delay signal T1 and the second delay signal T2, and an output for inverting the exclusive OR circuit 23 And an inverter 24 that outputs the signal as a window signal. The window signal generation circuit 11a in FIG. 3A is an example of the window signal generation circuit when the first time D1 is set to 0. Each of the variable delay circuits is configured such that a plurality of basic delay units composed of, for example, two-stage inverters are connected in series, and the delay value can be made variable by switching the output extraction position.
[0029]
The comparison circuit 13 compares the comparison clock signal DCLK with the window signal WS, detects whether the rising and falling points of the comparison clock signal DCLK are within the window of the window signal WS, and outputs the comparison result. I do.
[0030]
The comparison circuit 13 includes, for example, a flip-flop 31 that takes in the signal level of the window signal WS at the rise of the comparison clock signal DCLK, an inverter 32 that inverts the comparison clock signal DCLK, as shown in the comparison circuit 13a in FIG. The flip-flop 33 which takes in the signal level of the window signal WS at the rising edge of the inverted signal of the comparison clock signal DCLK, the output C1 of the flip-flop 31 and the output C2 of the flip-flop 32 are inputted and ORed, and C1 and C2 are taken. An OR circuit 34 that outputs a failure determination signal NG that goes high when any of them is high.
[0031]
The test control circuit 12 includes a control unit 15 that controls the operation of the entire jitter test circuit and the operation unit according to the state of the failure determination signal NG from the comparison circuit 13 based on the command CMD, and a control unit whose initial value is specified by the command CMD. And an arithmetic unit 14 that generates delay control information DINF by performing an operation under the control of F.15. In the calibration mode, the second time D2 is equal to the first time D1 when there is no jitter in the clock signal CLK. The delay control information that is equal to the time obtained by adding one cycle is searched. In the pass / fail judgment mode, the third time D3 is set to the jitter standard value JS, and the pass / fail judgment is made based on the state of the defect judgment signal NG from the comparison circuit 13. I do.
[0032]
The jitter test circuit 1a specifies the operation mode by the command CMD, and sets the initial value of the delay control information DINF for controlling each delay of the window signal generation circuit in the specified operation mode, the number of repetition measurements, the number of passes, the number of failures, and the like. Done.
[0033]
FIG. 5 is an operation timing chart of the window signal generation circuit 11 and the comparison circuit 13 in the pass / fail judgment mode of the jitter test circuit 1a of FIG. Description will be made assuming that the window signal generation circuit uses the window signal generation circuit 11a shown in FIG. 3A and the comparison circuit uses the comparison circuit 13a shown in FIG.
[0034]
In the calibration mode, the rising and falling of the virtual signal obtained by delaying the comparison clock signal DCLK by the ideal period Dp when there is no jitter are adjusted so as to be located at the center of the window of the window signal WS. Due to the calibration, the first delay signal T1 in the window signal generation circuit 11a of FIG. 3A is delayed by a third delay time D3 (ie, half the window width) from a virtual signal delayed by one cycle from the clock signal CLK. , The second delay signal T2 is set to have a longer delay by a third delay time D3 than the virtual signal delayed by one cycle from the clock signal CLK, and the window signal WS has the first delay signal T1 and the second delay signal T3. When the delay signal T2 is different from the delay signal T2, a low-level window is set.
[0035]
If there is no jitter in the clock signal CLK output from the PLL 2 by the adjustment in the calibration mode, the rising and falling points of the comparison clock DCLK are located at the center of the window of the window signal WS. 4, the output C1 of the flip-flop 31 and the output C2 of the flip-flop 32 in the comparison circuit 13a in FIG. 4 remain at the low level, and the failure determination signal NG is at the low level and the comparison circuit 13a Indicates that the results of the comparison are good.
[0036]
On the other hand, in a range B in which the jitter of a value larger than the third time D3 occurs in the clock signal CLK, the rising point and the falling point of the comparison clock DCLK are out of the window of the window signal WS. In some cases, the output C1 of the flip-flop 31 or the output C2 of the flip-flop 32 in the comparison circuit 13a goes high, and the failure determination signal NG goes high, indicating that the comparison result in the comparison circuit 13a is bad. Show.
[0037]
In the jitter test circuit of the first embodiment of FIG. 2, the window signal generation circuit is a second embodiment instead of the window signal generation circuit 11a of FIG. 3A described as the first embodiment. 3 (b) may be the window signal generation circuit 11b.
[0038]
In other words, the window signal generation circuit 11b receives the clock signal CLK from the PLL 2 and delays it by a time obtained by subtracting the third time D3 from the second time D2 to output the first delay signal T11. , A first delay signal T11, and a variable delay circuit 22 that outputs a second delay signal T12 generated by delaying by a time twice as long as the third time D3; a first delay signal T11; The exclusive OR circuit 23 which receives the delay signal T12 of the exclusive OR circuit and takes an exclusive OR, an inverter 24 which receives and inverts the output of the exclusive OR circuit 23 and outputs the same, and receives the clock signal CLK and receives the first signal. And a variable delay circuit 26 for delaying the output by the variable D circuit 26 for a time D1. The output of the variable delay circuit 26 is output as a comparison clock signal DCLK, and the output of the inverter 24 is Forces. In the window signal generation circuit 11a of FIG. 3A, the second time D2 is adjusted by calibration so as to be an ideal period Dp when there is no jitter of the clock signal CLK. Is different in that the second time D2 is adjusted by calibration so that the second time D2 is the time obtained by adding the period Dp of the clock signal CLK when there is no jitter to the first time D1. The comparison clock signal DCLK and the window signal WS are both input to the comparison circuit 13a of FIG. 4 with a delay of the first time D1. The window signal generation circuit 11a of FIG. 3A corresponds to the case where the first time D1 is set to 0 in the window signal generation circuit 11b of the present embodiment. When the first time D1 is set to a value equal to the third time D3 in the window signal generation circuit 11b of the present embodiment, the delay value after calibration of the variable delay circuit 25 is equal to the period of the clock signal CLK. Dp, and the delay value of the variable delay circuit 26 is the third time D3, so that the setting of the delay value is simple and easy.
[0039]
Similarly, in the jitter test circuit according to the first embodiment of FIG. 2, the window signal generation circuit is replaced with the window signal generation circuit 11a of FIG. The window signal generation circuit 11c shown in FIG.
[0040]
That is, the window signal generation circuit 11c receives the clock signal CLK and outputs a delay signal T21 generated by delaying the clock signal CLK by twice the third time D3, the clock signal CLK and the delay signal T21. , An exclusive-OR circuit 23 for receiving an exclusive-OR to input an exclusive-OR, an inverter 24 for receiving and inverting the output of the exclusive-OR circuit 23, and outputting the inverted signal, and a second time D2 for receiving the output of the inverter 24 and receiving the output. And a variable delay circuit 26 that receives the clock signal CLK and delays it for the first time D1. The output of the variable delay circuit 27 is used for comparison. It outputs the clock signal DCLK and the output of the variable delay circuit 27 as the window signal WS.
[0041]
Also in the window signal generation circuit 11c of the present embodiment, the second time D2 is adjusted by the calibration so that the second time D2 is the time obtained by adding the ideal period Dp when the jitter of the clock signal CLK is not added to the first time D1. Further, the comparison clock signal DCLK and the window signal WS are input to the comparison circuit 13a of FIG. 4 with a delay of the first time D1 as compared with these signals in the window signal generation circuit 11a of the first embodiment. This is the same as the window signal generation circuit 11b of the second embodiment. In the case where the first time D1 is set to a value equal to the third time D3 also in the window signal generation circuit 11c of the present embodiment, the delay value after calibration of the variable delay circuit 27 is equal to the clock signal CLK. Since the delay value is equal to the cycle Dp and the delay value of the variable delay circuit 26 is the third time D3, the setting of the delay value is simple and easy as in the window signal generation circuit 11b of the second embodiment.
[0042]
FIG. 6A is a circuit diagram showing a window signal generation circuit 11d according to a fourth embodiment of the window signal generation circuit 11 in the jitter test circuit 1a of FIG. The window signal generation circuit 11d is obtained by removing the inverter 24 from the window signal generation circuit 11a of FIG. Therefore, in the window signal WS output from the window signal generation circuit 11d, a high-level section is a window.
[0043]
FIG. 7 is a circuit diagram of the comparison circuit 13b configured corresponding to the window signal generation circuit 11d. The only difference is that a NAND circuit 35 is used instead of the OR circuit 34 of the comparison circuit 13a in FIG.
[0044]
FIG. 8 is an operation timing chart of the jitter test circuit 1a when the window signal generation circuit 11d and the comparison circuit 13b are used. As in the operation timing chart of FIG. 5, in the range A where no jitter occurs in the clock signal CLK, both the rising point and the falling point of the comparison clock signal DCLK are at the center of the window, but the window signal WS is in the window section. Is at a high level, the output C1 of the flip-flop 31 and the output C2 of the flip-flop 32 in the comparison circuit 13b in FIG. 7 are both at a high level, and the failure determination signal NG is at a low level as in FIG.
[0045]
In the range B in which a large value of jitter occurs in the clock signal CLK, the rising and falling points of the comparison clock DCLK fall outside the window of the window signal WS, and the output C1 of the flip-flop 31 or the flip-flop 32 in the comparison circuit 13b. Output C2 goes low, and the failure determination signal NG goes high, indicating that the comparison result is bad.
[0046]
FIG. 6B is a circuit diagram showing a window signal generation circuit 11e according to a fifth embodiment of the window signal generation circuit 11 in the jitter test circuit 1a of FIG. The window signal generation circuit 11e is obtained by removing the inverter 24 from the window signal generation circuit 11b of FIG. Therefore, in the window signal WS output from the window signal generation circuit 11e, the high-level section is a window, and thus is used together with the comparison circuit 13b in FIG.
[0047]
FIG. 6C is a circuit diagram showing a window signal generation circuit 11f of the sixth embodiment of the window signal generation circuit 11 in the jitter test circuit 1a of FIG. The window signal generation circuit 11f is obtained by removing the inverter 24 from the window signal generation circuit 11c of FIG. Therefore, in the window signal WS output from the window signal generation circuit 11f, since the high-level section is a window, it is used together with the comparison circuit 13b in FIG.
[0048]
Next, a jitter test method by the jitter test circuit 1a according to the first embodiment of FIG. 2 will be described in detail. As shown in the flow chart of the pass / fail judgment test in FIG. 9, the jitter test is performed when the jitter test circuit 1a is set to the calibration mode by an external command and the second time D2 is equal to the first time D1 when there is no jitter. A calibration phase 41 for adjusting to a value obtained by adding the cycle Dp of the clock signal CLK, and setting the jitter test circuit 1a to a pass / fail judgment mode by an external command and setting a second time D2 to the delay value obtained in the calibration phase And a pass / fail judgment phase 42 in which a third time D3 is set to the jitter standard value JS by an external command and pass / fail judgment is executed.
[0049]
In the pass / fail judgment phase, the jitter test circuit 1a includes one side before and after the comparison clock signal DCLK obtained by delaying the clock signal by the first time D1 and a virtual signal obtained by delaying the comparison clock signal by one cycle. Is compared with a window signal WS provided with a window having a width of the third time D3. Therefore, it is necessary to set the delay values of the variable delay circuits 21, 25, and 27 of the window signal generation circuits 11a to 11f to a value obtained by adding the first time D1 to one cycle of the clock signal CLK and subtracting the third time D3. There is.
[0050]
On the other hand, these variable delay circuits are configured by connecting basic delay units such as two-stage inverters in series, and the delay value is adjusted by adjusting the number of basic delay units connected in series. The unit requires a calibration phase because the delay value changes depending on manufacturing factors and use environment. For example, when the frequency of the clock signal CLK is 100 MHz and the basic delay unit is a standard value of 0.1 ns, one cycle of 10 ns is obtained from the frequency of the clock signal CLK, and this is calculated as the basic delay unit of the standard delay value. If it is configured, 100 series-connected basic delay units will be used. However, if the delay value of the basic delay unit is increased by 25% to 0.125 ns due to manufacturing factors, for example, in order to realize a delay of 10 ns for one cycle of the clock signal CLK, a series of 80 basic delay units is required. It must be connected, and 100 basic delay units simply calculated from the frequency are inappropriate. Here is the need for calibration.
[0051]
In the present invention, the basic delay units connected in series such that the rising point (or falling point) of the comparison clock signal DCLK generated by delaying the clock signal CLK coincides with the center of the window delayed by one cycle. By adjusting the number and adjusting the position of the window, the number of basic delay units for one cycle is calibrated. As a result, the number of basic delay units becomes irrelevant to 100, which is the number of basic delay units for one cycle calculated from the clock frequency of 100 MHz and the standard delay value of the basic delay unit of 0.1 ns. Using a basic delay unit of a delay value of 125 ns, the number is adjusted to 80, which is the number necessary to delay 100 ns, which is one cycle of the comparison clock signal DCLK.
[0052]
FIG. 10 is a flowchart of a calibration phase of the jitter test method by the jitter test circuit 1a, and FIGS. 11A, 11B, and 11C are operation timing diagrams of the calibration phase. In FIG. 10, for simplicity of explanation, it is assumed that calibration is performed for the window signal generation circuit 11a of FIG. 3A in which the first time D1 is 0, and that the first time D1 is not 0. The signal generation circuit will be described after the description of FIG.
[0053]
In FIG. 10, Np is the number of basic delay units corresponding to the period Dp (hereinafter, referred to as the number of basic delay units for one period), that is, (the delay value Du × Np = Dp of the basic delay unit), and Npc Is the number of basic delay units temporarily set at the time of calibration (hereinafter referred to as a temporary number of basic delay units), and N3 is the number of basic delay units (third number of times) that determines the third time D3 that is half the width of the window. ), And Du × N3 = D3.
[0054]
In FIG. 10, first, in step 51, initialization is performed. The test control circuit 12 controls the generation of the delay control information DINF based on the command CMD from the outside, and determines the temporary basic delay unit number Npc from the rising of the comparison clock signal DCLK to the leading edge of the corresponding window. The number is set to be surely larger than the time obtained by adding the third time D3 to one cycle of the clock signal CLK. That is, as shown in FIG. 11A, the time Dc from the rise of the comparison clock signal DCLK to the leading edge of the corresponding window signal WS is set to Dc = Npc × Du = (Dp + n × Du). In addition, the third basic delay unit number N3 is set to be a window that is sufficiently larger than the jitter value of the comparison clock signal DCLK.
[0055]
Next, the routine proceeds to step 52, where it is determined whether the rising point (rising edge) or the falling point (falling edge) of the comparison clock signal DCLK is within the window of the window signal WS. If the edge is not within the window, the process proceeds to step 53, and if the edge is within the window, the process proceeds to step 54. In FIG. 11A, for example, the point C representing the state of the window signal at the rising point of the comparison clock signal DCLK is at a high level and is outside the window, so the process proceeds to step 53.
[0056]
In step 53, the temporary basic delay unit number Npc is reduced by one and updated by changing the delay control information DINF. That is, the time obtained by subtracting the first time D1 from the second time D2 (corresponding to the time from the rising or falling point of the comparison clock signal DCLK to the center of the window generated based on this) is 1 It is reduced by the delay time Du of the basic delay unit. Thereafter, the process returns to step 52.
[0057]
By repeating steps 52 and 53, as shown in FIG. 11A, a window generated based on, for example, a rising edge of the comparison clock signal DCLK indicated by a bold line (displayed by a bold line in the window signal WS) ) Moves to the left in the figure and gradually approaches the rising point C one cycle later in the comparison clock signal DCLK.
[0058]
When it is first determined in step 52 that the comparison clock signal DCLK is within the window, that is, as shown in FIG. 11B, a thick line corresponding to the rising edge of the comparison clock signal DCLK indicated by a thick line is used. When the point D is determined to be low by the comparison circuit 13a at the leading edge of the displayed window slightly before the next rising edge of the comparison clock signal DCLK, and the pass / fail determination signal NG becomes low. Proceed to step 54.
[0059]
In step 54, the temporary basic delay unit number Npc at this time is stored as the maximum basic delay unit number Npmax. Assuming that the maximum delay value based on the maximum number of basic delay units is Dmax, the cycle Dp (when there is no jitter) of the comparison clock signal DCLK, the third time D3, the number Np of basic delay units corresponding to the cycle Dp, the third The third basic delay unit number N3, which is the number of basic delay units corresponding to the time D3 of
Npmax × Du = Dmax = Dp + D3
= (Np + N3) × Du
There is a relationship. In the next step 55, the temporary basic delay unit number Npc is reduced by one and updated by changing the delay control information DINF.
[0060]
In step 56, it is determined whether the rising edge and the falling edge of the comparison clock signal DCLK are inside or outside the corresponding window, respectively. If the rising edge and the falling edge of the comparison clock signal DCLK are not outside the corresponding window, that is, if they are inside the corresponding window, the process proceeds to step 57, where the provisional basic delay unit number Npc is changed by changing the delay control information DINF. Is updated by one, and the process returns to step 56.
[0061]
By repeating steps 56 and 57, the window indicated by the thick line corresponding to the rising edge of the comparison clock signal DCLK shown in FIG. 11B moves to the left.
[0062]
When it is first determined in step 56 that the comparison clock signal DCLK is out of the window, that is, as shown in FIG. 11C, a thick line corresponding to the rising edge of the comparison clock signal DCLK is displayed. When the trailing edge of the displayed window slightly precedes the next rising edge of the comparison clock signal DCLK, the point E is determined to be at the high level by the comparison circuit 13 and the pass / fail determination signal NG is at the high level. Proceed to 58.
[0063]
In step 58, the temporary basic delay unit number Npc at this time is stored as the minimum basic delay unit number Npmin. If the minimum delay value by the minimum basic delay unit number is Dmin,
Npmin × Du = Dmin = Dp−D3 = (Np−N3) × Du
There is a relationship.
[0064]
Next, proceeding to step 59, the number Np of basic delay units corresponding to the cycle Dp is calculated as
Np = (Npmax + Npmin) / 2
And terminates the calibration phase.
[0065]
The number Np of the basic delay units corresponding to one cycle Dp when there is no jitter of the comparison clock signal in this manner is a value corrected by a change in the delay time of the basic delay unit due to manufacturing factors and environmental conditions. In the pass / fail judgment phase, if there is no jitter, calibration can be performed such that the rising and falling points of the comparison clock signal are located at the centers of the corresponding windows.
[0066]
In order to avoid a decrease in calibration accuracy due to sudden jitter caused by strong external noise or the like, and to approach calibration in the case where there is no jitter in the comparison clock signal, step 52 in FIG. In step 52, the comparison between the edge and the window is performed a plurality of times, and when the number of times determined to be within the window is equal to or greater than the predetermined number of times Nin, the step 52 is changed to be determined to be within the window. In step 56, the edge may be compared with the window a plurality of times, and when the number of times of determination as being outside the window is equal to or greater than a predetermined number of times Nout, it may be changed to step 56 to determine that the window is outside the window. Further, in order to prevent a decrease in accuracy due to the influence of the periodic jitter of the comparison clock signal, in the calibration phase, the entire flow of FIG. 10 is executed a plurality of times, and corresponds to the obtained cycle Dp. If the average value of the number Np of the basic delay units is taken as the final value Np, it is possible to reduce a decrease in the accuracy of the calibration due to the influence of the jitter.
[0067]
The number Np of basic delay units corresponding to the cycle Dp is output to the outside of the semiconductor device 200 as delay control information DINF, and the actual delay value Du of the basic delay unit can be obtained by dividing the cycle of the clock signal by Np. . As a result, the third time D3 corresponding to the third basic delay unit number N3 can be accurately calculated, and the desired window width can be accurately set in the pass / fail determination phase.
[0068]
FIG. 10 can be modified to a calibration flow including a window signal generation circuit in which the first time D1 is not 0. In the modified flow, instead of the calibration for determining the basic delay unit number Np for one cycle of the clock signal CLK, a calibrated time is obtained by adding the first time D1 to one cycle Dp of the clock signal CLK. Is performed to determine the second basic delay unit number N2p corresponding to the second time. In the modification of FIG. 10, the temporary basic delay unit number Npc (for one cycle) of steps 51, 53, 54, 55, 57 and 58 is replaced with the temporary basic delay unit number N2c (for the second time). In the initial setting of N2c in 51, the time from the rising or falling of the clock signal CLK to the leading edge of the corresponding window is longer than the time obtained by adding the first time D1 and the third time D3 to one cycle of the clock signal CLK. Is also set so as to be surely large, and the maximum number of basic delay units Npmax (for the second time) in steps 54 and 59 is replaced with the maximum number of basic delay units N2max (for the second time), The minimum basic delay unit number Npmin (for one period) of step 58 is changed to the minimum basic delay unit number N2 (for the second time). Replaced in, it may be replaced with basic delay unit number Np of one cycle of the clock signal CLK in step 59 to the second basic delay unit number N2p corresponding to the second time been calibrated.
[0069]
As a result, Npc, NPmax, and Npmin of each step become N2c, N2max, and N2min, which are larger by the first basic delay unit number N1 corresponding to the first time D1. The second basic delay unit number N2p corresponding to the already completed second time is larger than the basic delay unit number Np for one cycle of the clock signal CLK by the first basic delay unit number N1 corresponding to the first time D1. It becomes the number. To obtain the basic delay unit number Np for one cycle of the clock signal CLK in FIG. 10 from the second basic delay unit number N2p corresponding to the calibrated second time obtained by the above modified flow, Np = N2p-N1.
[0070]
Next, a detailed flow of the pass / fail judgment phase will be described with reference to FIG. FIG. 12 is a flow in the case where the window signal generation circuit 11a in FIG. 3A in which the first time D1 is 0 is used, as in FIG. 10 in the calibration phase. When the first time D1 is extended so that it can be applied to a window signal generation circuit other than 0, the calibrated second delay N1 is set instead of setting the basic delay unit number Np for one cycle of the clock signal CLK in step 61. May be changed so as to set the second number N2p of basic delay units corresponding to the time.
[0071]
In the pass / fail judgment phase, initial settings are first made in step 61. That is, the test control circuit 12 obtains the third number of the basic delay unit Np for one cycle of the clock signal CLK obtained in the calibration phase based on the command CMD from the outside, the jitter standard value and the delay value Du of the basic delay unit. And the third basic delay unit number N3, which is the number of basic delay units corresponding to the time D3 (half of the window width), generates delay control information DINF, sets Np and N3, and sets a predetermined path. The number of times PN and a predetermined number of times of fail FN are set.
[0072]
Then, the process proceeds to a step 62, wherein it is determined whether or not the rising edge and the falling edge of the comparison clock signal DCLK are within the window. If the jitter J1 in FIG. 13A is small, as shown in the operation timing chart in the pass / fail judgment mode, the rising edge and the falling edge fall within the window, and the pass / fail judgment signal NG becomes low level. If it is determined that it is within the window, the process proceeds to step 63, where the count value PCNT of the number of passes is updated by incrementing by 1, and then the process proceeds to step 64.
[0073]
In step 64, it is determined whether the count value PCNT of the number of passes is less than a predetermined number of passes PN. If the count value PCNT of the number of passes is less than the predetermined number of passes PN, the process returns to step 62. If the count value PCNT is not less than the predetermined number of passes PN, the process is determined to be non-defective in step 65 and the process is terminated.
[0074]
In step 62, if the jitter is large J2 as shown in FIG. 13B, many states in which the rising edge and the falling edge are outside the window occur, and the pass / fail judgment signal NG becomes high level. If it is determined that it is not within the window, the routine proceeds to step 66, in which the count value FCNT of the number of times of failure is incremented by 1 and updated, and then the routine proceeds to step 67.
[0075]
In step 67, it is determined whether the count value FCNT of the number of failures is less than a predetermined number of failures FN. If the count value FCNT of the number of failures is less than the predetermined number of failures FN, the process returns to step 62, and if not, the process is determined to be defective in step 68 and the processing ends.
[0076]
Practically, in the pass / fail determination phase, the test control circuit 12 captures the signal level of the pass / fail determination signal NG at appropriate time intervals, although not necessarily continuous, and the signal level of the captured pass / fail determination signal NG is the pass level. When the count value PCNT of the number of times becomes equal to or more than the predetermined number of times of pass PN, the judgment signal JDG is output as a level indicating a non-defective product. When the number of times of failure FN or more is reached, the determination signal JDG may be output as a level indicating a failure.
[0077]
As described above, in the first embodiment of the present invention, the calibration phase is provided before the pass / fail judgment phase, the jitter test circuit 1a is set to the calibration mode by an external command, and the positions of the comparison clock signal and the window signal are set. In an ideal case where there is no jitter, the calibration is performed so that the rising and falling points of the comparison clock signal DCLK are at the center of the corresponding windows, and then the jitter test circuit 1a is set to the pass / fail judgment mode. Then, the comparison clock signal DCLK and the window signal WS are compared to determine whether the rising point and the falling point of the comparison clock signal DCLK are located in the corresponding window or outside the window. Since the pass / fail is determined, similar to the second conventional example of FIG. Concrete factors, can be measured accurately jitter amount without being affected by environmental conditions. Further, since the jitter test circuit 1a is composed of the window signal generation circuit 11, the test control circuit 12, and the comparison circuit 13 which are digital circuits, it is easier to design than the second conventional example having an analog circuit portion. There is an advantage that it can be realized with a small occupied area since no special noise countermeasures are required.
[0078]
In the present invention, the unit of measurement of the jitter is, for example, the delay time of a basic delay unit composed of two stages of inverters, and the jitter is measured by changing the number of sampling pulses falling within the measurement range. Compared with the method described in JP-A-131637, the delay amount of the two-stage inverter can generally be made much smaller than the period of the sampling pulse, and therefore, the present invention enables more accurate measurement.
[0079]
The variable delay circuits 21 and 22 in the window signal generation circuit 11a of FIG. 3A may be configured by one variable delay circuit provided with a plurality of output taps. FIG. 14A is a circuit diagram of a variable delay circuit 71 used in place of the variable delay circuits 21 and 22. The variable delay circuit 71 includes, for example, a delay generation unit 72 in which a plurality of basic delay units 74 each composed of two stages of inverters are connected in series, and a delay selection unit that selects a signal from an output point of each basic delay unit and outputs a signal. In the pass / fail determination mode, as shown in FIG. 14A, the clock signal CLK is directly output as the comparison clock signal DCLK from the first output tap by the delay selection scanning of the delay selection unit 73, From the second output tap, an output point where the clock signal CLK is delayed by the time obtained by subtracting the third time D3 from the cycle Dp is selected and output as the delay signal T1, and the clock signal CLK is output as the delay signal T2 from the third output tap. Selects and outputs an output point delayed by the time obtained by adding the third time D3 to the cycle Dp. Also in the window signal generation circuit 11d of FIG. 6A, the variable delay circuits 21 and 22 can be replaced with the variable delay circuit 71 of FIG.
[0080]
Similarly, in the window signal generation circuit 11b of FIG. 3B, the variable delay circuits 22, 25, and 26 may be configured by one variable delay circuit 71 provided with a plurality of output taps. FIG. 14B is a circuit diagram of the variable delay circuit 71 corresponding to the case where the first time D1 and the third time D3 are made equal in the window signal generation circuit 11b. In the pass / fail determination mode, as shown in FIG. 14B, the clock signal CLK is output as the comparison clock signal DCLK for the third time from the first output tap by the delay selection operation of the delay selection unit 73 based on the delay control information DINF. An output point delayed by D3 is selected and output, an output point whose clock signal CLK is delayed by a period Dp is selected and output from the second output tap as a delay signal T11, and a clock signal CLK is output as a delay signal T12. An output point delayed by a time obtained by adding twice the third time D3 to Dp is selected and output. In the window signal generation circuit 11e of FIG. 6B, the variable delay circuits 22, 25 and 26 can be replaced with the variable delay circuit 71 of FIG. 14B.
[0081]
Next, a second embodiment of the jitter test circuit according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 15 is a block diagram of a jitter test circuit 1b according to the second embodiment of the present invention.
[0082]
The jitter test circuit 1b includes a window signal generation circuit 11, a test control circuit 12, and a comparison circuit 13 similarly to the jitter test circuit 1a of the first embodiment, but further includes an encoding circuit 16. After the calibration, the jitter value of the clock signal CLK is measured by comparing the comparison clock signal DCLK with the window signal WS while changing the window width, and the measurement result is encoded and output to the outside.
[0083]
In the jitter test circuit 1b, the window signal generation circuit 11 and the comparison circuit 13 are the same as in the jitter test circuit 1a of the first embodiment, and the window signal generation circuits 11a, 11b, 11c of FIG. It is used in combination with the comparison circuit 13a, or in combination with the window signal generation circuits 11d, 11e, 11f in FIG. 6 and the comparison circuit 13b in FIG.
[0084]
The test control circuit 12 receives the command CMD including the operation mode designation and the comparison result of the comparison circuit 13 and controls generation of the delay control information DINF and execution of the test operation. In the calibration mode, the delay control information DINF in which the second time D2 is equal to the first time D1 plus the period Dp of the clock signal CLK when there is no jitter is searched for. In the jitter measurement mode, the calibration is performed. The second time D2 is set based on the delay control information searched in the mode, and the jitter value is determined based on the result of the comparison performed a plurality of times while changing the third time D3 by the comparison circuit 13.
[0085]
That is, in the calibration mode, the delay control information DINF is set such that the second time D2 is an initial time longer than one cycle of the clock signal CLK plus the first time D1 and the third time D3. Thereafter, the delay control information DINF is manipulated to monitor the comparison result from the comparison circuit 13 while gradually reducing the delay time of the second time D2 in increments of the basic delay unit. Calibration is performed by searching for delay control information DINF corresponding to a second time D2 when the falling point is located at the center of the window.
[0086]
In the jitter measurement mode, the second time D2 is set based on the delay control information DINF searched in the calibration mode, and the third time D3 is controlled by the delay control information DINF to compare while changing the width of the window. Monitoring is performed in correspondence with the comparison result of the circuit 13, and the jitter value JV is determined from the delay control information DINF corresponding to the third time D3 of the critical value at which the determination changes from non-defective to defective.
[0087]
The encoding circuit 16 generates and outputs encoded jitter information JINF from the jitter value JV determined by the test control circuit 12 and the delay control information DINF.
[0088]
FIG. 16 is an example of encoding of the jitter value JV. The jitter value JV is sent to the encoding circuit 16 as the number of basic delay units corresponding to the measured actual jitter value, and the encoding circuit 16 encodes the number of basic delay units corresponding to the jitter value into a binary representation. And outputs it as encoded jitter information JINF. However, the encoding circuit is not limited to this. If the delay value of one basic delay unit is much smaller than the jitter value, for example, M (M is a positive integer) basic delay units May be encoded as the same jitter value. Alternatively, the delay value Du of the basic delay unit is held in the encoding circuit 16 and the jitter value detected as the third basic delay unit number N3 corresponding to the jitter is multiplied by the delay value Du to convert the jitter value into time. After conversion, it may be encoded and output.
[0089]
Next, a jitter test method by the jitter test circuit 1b according to the second embodiment of FIG. 15 will be described in detail. As shown in the flow chart of the jitter test in FIG. 17, in the jitter test by the jitter test circuit 1b, the jitter test circuit 1b is set to the calibration mode by an external command, and the second time D2 is set to the first time D1. The calibration phase 81 for adjusting to the value obtained by adding the cycle Dp of the clock signal CLK when there is no clock, and the second time D2 is obtained in the calibration phase by setting the jitter test circuit 1b to the jitter measurement mode by an external command. A delay value is set, and the rising and falling points of the comparison clock signal DCLK and the window signal WS are compared a plurality of times while changing the window width by changing the third time D3 which is half the window width. And a jitter value is determined by detecting a third time D3 determined to be defective. It turned into it and a jitter measurement phase 82 to be output.
[0090]
The calibration phase 81 is the same as the calibration phase 41 in the first embodiment, and the calibration is performed by the same method as the flow in FIG.
[0091]
The detailed flow of the jitter measurement phase will be described with reference to FIG. FIG. 18 is a flowchart in the case where the window signal generation circuit 11a of FIG. 3A in which the first time D1 is 0 is used, as in FIG. 10 in the calibration phase. When the first time D1 is extended so that it can be applied to a window signal generation circuit that is not 0, instead of setting the basic delay unit number Np for one cycle of the clock signal CLK in step 91, the calibrated second time is used. May be changed so as to set the second basic delay unit number N2p corresponding to the time.
[0092]
In the jitter measurement phase, first, an initial setting is performed in step 91. That is, the test control circuit 12 calculates the Np obtained in the calibration phase based on the external command CMD and the third basic delay which is the number of basic delay units corresponding to the third time D3 which is half the window width. An initial value of the unit number N3 is set by the delay control information DINF, and a predetermined number of passes PN, a predetermined number of failures FN, and a predetermined number of repetitions MN are set. Next, the routine proceeds to step 92, where 1 is added to the number of times of measurement i and updated.
[0093]
Then, the process proceeds to a step 93, wherein it is determined whether or not the rising edge and the falling edge of the comparison clock signal DCLK are within the window. In the operation timing chart of FIG. 19A, the initial value of the third time D3 is set to be large, so that the window width of the window signal is much larger than the jitter of the comparison clock signal DCLK. Since the rising edge and the falling edge of the clock signal for use DCLK fall within the window, the outputs C1 and C2 of the flip-flop are both at the low level, and the pass / fail judgment signal NG is at the low level. If it is determined that it is within the window, the process proceeds to step 94, where the count value PCNT of the number of passes is updated by incrementing by 1, and then the process proceeds to step 95.
[0094]
In step 95, it is determined whether the count value PCNT of the number of passes is less than a predetermined number of passes PN. If the count value PCNT of the number of passes is less than the predetermined number of times PN, the process returns to step 93, and if not, the process proceeds to step 96 to calculate the basic delay corresponding to the third time D3 by the delay control information DINF. The third basic delay unit number N3, which is the number of units, is reduced and updated by one, the pass count value PCNT and the fail count value FCNT are cleared to 0, and the process returns to step 93.
[0095]
For example, if PN is set to 5, in the state of FIG. 19A, the path determination is repeated four times in step 93, and in the fifth path determination, the process proceeds to step 96, where the third basic delay unit number N3 is set. Is reduced by one. As a result, it is assumed that the state shown in FIG.
[0096]
Step 93 is performed in the state of FIG. 19B. However, since the window width of the window signal is still larger than the jitter of the comparison clock signal DCLK, the rising edge of the comparison clock signal DCLK and the The falling edge enters the window, and the outputs C1 and C2 of the flip-flops are both at the low level, and the pass / fail judgment signal NG is at the low level.
[0097]
If the path determination is repeated four times in step 93 in the state of FIG. 19B, the fifth path determination proceeds to step 96, where the third basic delay unit number N3 is reduced by one. As a result, it is assumed that the state shown in FIG.
[0098]
In step 93, when the jitter is large relative to the window as shown in FIG. 13C, the rising and falling edges are outside the window as shown at point G3, so that the outputs C1 and C2 of the flip-flops are at the high level. , And the pass / fail judgment signal NG becomes high level. As described above, when it is determined in step 93 that the number is not within the window, the process proceeds to step 97, in which the count value FCNT of the number of failures is incremented by 1 and updated, and then the process proceeds to step 98.
[0099]
In step 98, it is determined whether the count value FCNT of the number of failures is less than a predetermined number of failures FN. If the count value FCNT of the number of failures is less than the predetermined number of failures FN, the process returns to step 93, and if not, the flow proceeds to step 99.
[0100]
For example, if FN = 2 is set, FCNT is updated to 1 and the process returns to step 93 at the time of the first fail determination in which the high level of the pass / fail determination signal NG is read for the first time. If the high level of the pass / fail judgment signal NG is read before PCNT reaches 5 times, and the second fail judgment occurs, the process proceeds to step 99.
[0101]
In step 99, the third basic delay unit number N3 at this time is stored in the storage area Z (i) which is predetermined as the jitter basic delay number Nj (i). In addition, the count value PCNT of the pass count and the count value FCNT of the fail count are cleared to zero.
[0102]
Next, the routine proceeds to step 100, where it is determined whether or not the number of measurements i is less than a predetermined number of repeated measurements MN. If the number is smaller than the predetermined number MN, the process returns to step 92 to continue the measurement. If the number is equal to or greater than the predetermined number of repetitions MN, the process proceeds to step 101.
[0103]
In step 101, the average value of the basic delay numbers Nj (1) to Nj (MN) for the MN times stored in each of the storage areas Z (i) is calculated and output from the test control circuit 12 as the jitter value JV. .
[0104]
In step 102, the encoding circuit 16 encodes the jitter value, for example, as shown in FIG.
[0105]
As described above, in the second embodiment of the present invention, the calibration phase is provided before the jitter measurement phase, the jitter test circuit 1b is set to the calibration mode by an external command, and the positions of the comparison clock signal and the window signal are set. In an ideal case where there is no jitter, the calibration is performed so that the rising and falling points of the comparison clock signal DCLK are at the center of the corresponding windows, and then the jitter test circuit 1b is set to the jitter measurement mode. Then, the third time D3 is changed by the delay control information DINF, the jitter is measured by comparing the comparison clock signal DCLK with the window signal WS, and the average value of the plurality of measurements is encoded as the jitter value. Output, accurate jitter amount regardless of manufacturing factors and environmental conditions Can be measured, the amount of jitter can be output to the outside of the semiconductor device mounted with a jitter test circuit 1b in serial or parallel as digital data encoding. As a result, it is possible to evaluate and analyze the jitter such as the evaluation of the distribution of the jitter value by the repeated measurement over a long time. Since the jitter test circuit 1b is constituted by a digital circuit as in the first embodiment, it is easier to design than the second conventional example having an analog circuit portion, and requires special noise countermeasures. Therefore, there is an advantage that it can be realized with a small occupied area.
[0106]
FIG. 20 is a block diagram of the jitter test circuit 1c according to the third embodiment of this invention. The jitter test circuit 1c includes a window signal generation circuit 11, a test control circuit 12, and a comparison circuit 13, similarly to the jitter test circuit 1a of the first embodiment in FIG. A detection circuit 17 is provided. The functions of the window signal generation circuit 11, the test control circuit 12, and the comparison circuit 13 are the same as those of the jitter test circuit 1a, and thus the description is omitted.
[0107]
The same-code continuation data detection circuit 17 outputs the same-code continuation data detection signal CSS when it detects that data of the same code continues for a predetermined data number DN or more in the data signal DATA input from the outside.
[0108]
The same-code continuous data detection circuit 17 includes a same-code continuous data counter 18 that counts the number of times that the same code is continuous, that is, when 0 data is continuous or 1 data is continuous, and a preset same-code continuous data counter 18. A predetermined number of data DN is compared with a count value CCN of the same code continuous data counter 18, and if the count value CCN is equal to or more than a predetermined number of data DN, a same code continuous data detection signal CSS is output. And a vessel 19.
The jitter test circuit 1c operates similarly to the jitter test circuit 1a in the calibration mode and the pass / fail judgment mode, except that the clock signal CLK is replaced with the recovery clock signal RCLK in the jitter test circuit 1a of FIG.
[0109]
The clock recovery PLL circuit 4 extracts and reproduces the recovery clock signal RCLK based on a change in the data signal DATA, and supplies the recovered clock signal RCLK to the window signal generation circuit 11 and an internal circuit. The clock recovery PLL circuit 4 keeps generating the recovery clock signal RCLK while maintaining the cycle and phase of the recovery clock signal RCLK up to that point even when data of the same sign continues in the data signal DATA. Known examples of such a clock recovery PLL circuit include, for example, a phase locked loop described in JP-A-6-315024 and a phase locked loop described in JP-A-10-285150.
[0110]
When the active signal level state continues for both the same code continuous data detection signal CSS and the determination result signal JDG, that is, when the data of the same sign continues in the data signal DATA and the jitter exceeds the specified value in the jitter test circuit 1c. Is continuously detected, there is a strong possibility that the lock frequency of the clock recovery PLL circuit has deviated for some reason. However, since the data signal DATA does not change during reception of the same-code continuous data, the phase shift cannot be detected by the clock recovery PLL circuit 4 itself. Therefore, the phase difference deviates from the phase to be locked and the phase difference continues to increase.
[0111]
FIG. 21 is a timing chart of an operation example when the data signal DATA changes from 1/0 repetition to 1 continuous data. The count value CCN of the same sign continuous data counter is counted up when the data signal DATA becomes continuous data of 1, and the recovery clock RCLK continues to maintain the signal even after the data signal DATA becomes continuous data of 1. When the predetermined data number DN is set to 3, when the count value CCN becomes 3, the same-code continuous data detection signal CSS becomes active high level. If the cycle of the recovery clock RCLK changes and increases at time H, the pass / fail judgment signal NG becomes active high level, and if the pass / fail judgment signal NG continues to be high level, the judgment result signal JDG becomes active high level. . As described above, since the jitter test circuit 1c outputs the same-code continuous data detection signal CSS and the determination result signal JDG, when the lock frequency of the clock recovery PLL circuit is shifted, it can be detected. Occurs.
[0112]
FIG. 22 is a diagram showing another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 201, a frequency dividing circuit 111 is mounted in place of the PLL circuit 2 in the semiconductor device 200 of FIG. 1, and the jitter test circuit 1 performs a jitter test of a divided clock signal DVCLK generated by dividing the input clock signal ICLK. (Pass / fail judgment test or jitter measurement test).
[0113]
FIG. 23 is a diagram showing still another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 202, a multiplication PLL circuit 112 is mounted in place of the PLL circuit 2 in the semiconductor device 200 of FIG. 1, and the jitter test circuit 1 performs a jitter test of the multiplied clock signal NCLK generated by multiplying the input clock signal ICLK by N. Do.
[0114]
FIG. 24 is a diagram showing still another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 203, dedicated PLL circuits 121 and 122 are provided for each of the plurality of internal circuits A and B, and the selector 123 selects the clock signals CLKA and CLKB of the PLL circuits 121 and 122 with the selection signal SEL. The clock signal SCLK is supplied to the jitter test circuit 1. By configuring the semiconductor device 203 in this manner, a plurality of clock signals used inside the device can be tested by one jitter test circuit.
[0115]
FIG. 25 is a diagram showing still another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 204, the clock signal CLK generated by the PLL circuit 2 and the high-quality clock FCLK supplied from the outside are input to the selector 131, and the selected clock SCLK output from the selector is generated by the PLL circuit 2. The configuration is such that the clock signal CLK is determined based on a test result by the jitter test circuit 1. When the jitter of the clock signal CLK generated by the PLL circuit 2 is large and is inconvenient as a clock signal for operation test of the internal circuit, a high-quality clock FCLK with small jitter is supplied from the outside to the internal circuit to operate the internal circuit. Testing can be done.
[0116]
FIG. 26 is a diagram showing still another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 205, one of the input clock signal ICLK and the clock signal CLK generated by the PLL circuit 2 is selected and input by the selector 141, and the selected clock SCLK output from the selector 141 is subjected to the jitter test by the jitter test circuit 1. It is configured to test. In particular, in the jitter measurement test, the jitter of the input clock signal ICLK and the jitter of the clock signal CLK generated by the PLL circuit 2 are measured, and the former is subtracted from the latter, so that the influence of the input jitter is removed and the jitter is caused only by the PLL circuit 2. A jitter value can be obtained.
[0117]
FIG. 27 is a diagram showing still another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. The semiconductor device 206 includes a statistic circuit 151 in addition to the configuration of the semiconductor device 200 in FIG. The clock signal CLK generated by the PLL circuit 2 is measured for jitter by the jitter test circuit 1 and the encoded jitter information JINF is taken into the statistical circuit 151, and the jitter of the clock signal CLK is distributed over a certain period to obtain the distribution of the jitter value of the clock signal CLK. Can be measured.
[0118]
FIG. 28 is a diagram showing still another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. The semiconductor device 207 includes a plurality of clock recovery PLL circuits 161, 162, 163 for generating a recovery clock from the input data signals and output clock signals CLKA, CLKB, CLKC from the clock recovery PLL circuits 161, 162, 163. Is selected as a clock signal to be tested by the selection signal SEL and supplied to the jitter test circuit 1, and one of CLKA, CLKB and CLKC is supplied to the internal circuit as the selected clock signal SCLK by the selection signal SEL. And a selector 164 that performs the operations. The jitter of the clock signals CLKA, CLKB, and CLKC is measured by the jitter test circuit 1, and the clock signal with the least jitter can be supplied to the internal circuit as the selected clock signal SCLK.
[0119]
【The invention's effect】
As described above, in the present invention, the jitter test circuit is set to the calibration mode before performing the pass / fail judgment or the jitter measurement, and the positional relationship between the comparison clock signal and the window signal is compared for an ideal case where there is no jitter. The number of the basic delay units constituting the variable delay circuit is adjusted and calibrated so that the rising point and the falling point of the clock signal DCLK are at the center of the corresponding windows, and then the jitter test circuit is set in the pass / fail judgment mode. Alternatively, the mode is set to the jitter measurement mode, the comparison clock signal DCLK is compared with the window signal WS, and the rising point and the falling point of the comparison clock signal DCLK are located at positions within the corresponding window or outside the window. The jitter test circuit according to the present invention. By using a semiconductor device equipped with this jitter test circuit and a test method using the jitter test circuit of the present invention, the amount of jitter can be accurately measured without being affected by manufacturing factors and environmental conditions as in the second conventional example. There is an effect that can be done.
[0120]
Further, the jitter test circuit of the present invention is constituted by a digital circuit, so that it is easier to design than the second conventional example having an analog circuit portion, and does not require any special noise countermeasures. There is an advantage that you can.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a semiconductor device equipped with a jitter test circuit of the present invention.
FIG. 2 is a block diagram of a first embodiment of the jitter test circuit of the present invention.
FIGS. 3A, 3B, and 3C are circuit diagrams of a window signal generation circuit.
FIG. 4 is a circuit diagram of a comparison circuit.
FIG. 5 is an operation timing chart of the jitter test circuit.
FIGS. 6A, 6B, and 6C are circuit diagrams of a window signal generation circuit.
FIG. 7 is a circuit diagram of a comparison circuit.
FIG. 8 is an operation timing chart of the jitter test circuit.
FIG. 9 is a flowchart of a pass / fail judgment test.
FIG. 10 is a detailed flowchart of a calibration phase.
FIGS. 11A, 11B and 11C are timing charts showing the operation of the jitter test circuit in the calibration phase.
FIG. 12 is a detailed flowchart of a pass / fail judgment phase.
FIGS. 13A and 13B are timing charts showing the operation of the jitter test circuit in the pass / fail judgment phase.
FIG. 14 is a circuit diagram of a configuration example of a variable delay circuit.
FIG. 15 is a block diagram of a jitter test circuit according to a second embodiment of the present invention.
FIG. 16 is a diagram illustrating an example of encoding performed by an encoding circuit.
FIG. 17 is a flowchart of a jitter measurement test.
FIG. 18 is a detailed flowchart of the jitter measurement phase.
FIGS. 19 (a), (b) and (c) are timing charts showing the operation of the jitter test circuit in the jitter measurement phase.
FIG. 20 is a block diagram of a third embodiment of the jitter test circuit of the present invention.
FIG. 21 is an operation flowchart of the jitter test circuit according to the third embodiment;
FIG. 22 is a diagram schematically showing another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 23 is a view schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 24 is a diagram schematically showing another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 25 is a diagram schematically showing another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 26 is a diagram schematically showing another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 27 is a diagram schematically showing another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 28 is a diagram schematically showing another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 29 is a block diagram of a jitter test circuit of a first conventional example.
FIG. 30 is a block diagram of a jitter test circuit of a second conventional example.
[Explanation of symbols]
1,1a, 1b, 1c Jitter test circuit
2 PLL circuit
11, 11a, 11b, 11c, 11d, 11e, 11f Window signal generation circuit
12 Test control circuit
13, 13a, 13b Comparison circuit
16 Encoding circuit
17 Same-code continuous data detection circuit
200, 201, 202, 203, 204, 205, 206, 207 Semiconductor device
CLK clock signal
CMD command
CSS same-code continuous data detection signal
DCLK Comparison clock signal
DINF delay control information
JDG judgment result signal
JINF coded jitter information
NG Pass / fail judgment signal
WS window signal

Claims (28)

In a jitter test circuit that detects a jitter of a timing signal that periodically alternates between a high level and a low level,
The timing signal and delay control information that specifies the delay time as the number of basic delay units are input, and the timing signal for comparison generated by delaying the timing signal by a first time based on the delay control information, and A window signal having a window having a predetermined signal level within a third time width before and after a rising point and a falling point of a signal obtained by delaying a timing signal by a second time is generated and output. A window signal generation circuit to
A comparison circuit that compares the comparison timing signal with the window signal, detects whether a rising point and a falling point of the comparison timing signal are within the window, and outputs a comparison result;
A command including an operation mode designation and the comparison result are input to control generation of the delay control information and execution of a test operation. In the calibration mode, the second time has no jitter at the first time. Search for delay control information equal to the time obtained by adding one cycle of the timing signal in the case, and set the second time based on the delay control information searched for in the calibration mode in the pass / fail determination mode. A test control circuit that sets a third time to a jitter standard value and determines pass / fail based on a comparison result from the comparison circuit. The test control circuit includes:
In the calibration mode, the delay control information is initialized after setting the second time to a time longer than one cycle of the timing signal plus the first time and the third time. The delay control information is operated to gradually reduce the delay time of the second time in increments of a basic delay unit, and the comparison result from the comparison circuit is monitored. Searching for delay control information corresponding to the second time when a point and a falling point are located in the center of the window;
In the pass / fail determination mode, the second time is set based on the delay control information searched in the calibration mode, delay control information is generated based on a command input from the outside, and the third time is set to the jitter standard value. When the number of times of occurrence of the comparison result indicating the deviation of the rising point and the falling point of the comparison timing signal from the window is greater than or equal to a predetermined number, 2. The jitter test circuit according to claim 1, wherein the circuit is determined to be defective. In a jitter test circuit that detects a jitter of a timing signal that periodically alternates between a high level and a low level,
The timing signal and delay control information that specifies the delay time as the number of basic delay units are input, and the timing signal for comparison generated by delaying the timing signal by a first time based on the delay control information, and A window signal having a window having a predetermined signal level within a third time width before and after a rising point and a falling point of a signal obtained by delaying a timing signal by a second time is generated and output. A window signal generation circuit to
A comparison circuit that compares the comparison timing signal with the window signal, detects whether a rising point and a falling point of the comparison timing signal are within the window, and outputs a comparison result;
A command including an operation mode designation and the comparison result are input to control the generation of the delay control information and the execution of the test operation. In the calibration mode, the second time has no jitter in the first time. In the case of jitter measurement mode, the second time is set based on the delay control information searched for in the calibration mode. A test control circuit for determining a jitter value based on a result of comparison a plurality of times by changing the third time by a comparison circuit;
A jitter test circuit comprising: an encoding circuit that generates and outputs encoded jitter information from the jitter value determined by the test control circuit and the delay control information. The test control circuit includes:
In the calibration mode, the delay control information is set after setting the second time to an initial time longer than a time obtained by adding the first time and the third time to one cycle of the timing signal. The delay control information is operated to gradually reduce the delay time of the second time in increments of a basic delay unit, and the comparison result from the comparison circuit is monitored. Searching for delay control information corresponding to the second time when a point and a falling point are located in the center of the window;
In the jitter measurement mode, the second time is set based on the delay control information searched in the calibration mode, and the third time is controlled by the delay control information to change the width of the window. 4. The jitter according to claim 3, wherein the jitter value is determined from delay control information corresponding to a third time of a critical value at which a determination is made from a non-defective product to a defective product in accordance with a comparison result of the comparison circuit. Test circuit. 5. The test control circuit according to claim 1, wherein the first time is 0, and the predetermined signal level is a low level. The window signal generation circuit,
A first variable delay circuit that inputs the timing signal and outputs a first delay timing signal generated by delaying the second time by subtracting the third time from the second time;
A second variable delay circuit that inputs the first delay timing signal and outputs a second delay signal generated by delaying the delay time by twice the third time;
A gate circuit that inputs the first delay timing signal and the second delay timing signal, performs an exclusive OR operation, and inverts the output;
The jitter test circuit according to claim 5, wherein the timing signal is output as the comparison timing signal, and an output of the gate circuit is output as the window signal. 5. The test control circuit according to claim 1, wherein the first time is equal to the third time, and the predetermined signal level is a low level. The window signal generation circuit,
A first variable delay circuit that inputs the timing signal and outputs a first delay timing signal generated by delaying the second time by subtracting the third time from the second time;
A second variable delay circuit that receives the first delay timing signal and outputs a second delay signal generated by delaying the delay time by twice the third time;
A gate circuit that inputs the first delay timing signal and the second delay timing signal, performs an exclusive OR operation, and inverts the output;
A third variable delay circuit that receives the timing signal and delays the timing signal by a first time equal to the third time,
The jitter test circuit according to claim 7, wherein an output of the third variable delay circuit is output as the comparison timing signal, and an output of the gate circuit is output as the window signal. The window signal generation circuit,
A first variable delay circuit that inputs the timing signal and outputs a delay timing signal generated by delaying the timing signal by twice the third time;
A gate circuit that inputs the timing signal and the delay timing signal, performs an exclusive OR operation, and inverts the output;
A second variable delay circuit that receives an output of the gate circuit and delays the output by a time obtained by subtracting the third time from the second time;
A third variable delay circuit that receives the timing signal and delays the timing signal by a first time equal to the third time,
The jitter test circuit according to claim 7, wherein an output of the third variable delay circuit is output as the comparison timing signal, and an output of the second variable delay circuit is output as the window signal. The comparison circuit includes:
A first flip-flop that captures a signal level of the window signal at a rise of the comparison timing signal;
A second flip-flop that captures the signal level of the window signal at the fall of the comparison timing signal;
10. The logic circuit according to claim 6, further comprising: a logical sum circuit that inputs an output of the first flip-flop and an output of the second flip-flop, performs a logical sum, and outputs a failure determination signal. The described jitter test circuit. 5. The test control circuit according to claim 1, wherein the first time is 0, and the predetermined signal level is a high level. The window signal generation circuit,
A first variable delay circuit that inputs the timing signal and outputs a first delay timing signal generated by delaying the second time by subtracting the third time from the second time;
A second variable delay circuit that inputs the first delay timing signal and outputs a second delay signal generated by delaying the delay time by twice the third time;
An exclusive OR circuit that inputs the first delay timing signal and the second delay timing signal and takes an exclusive OR,
12. The jitter test circuit according to claim 11, wherein the timing signal is output as it is as the comparison timing signal, and an output of the exclusive OR circuit is output as the window signal. 5. The test control circuit according to claim 1, wherein the first time is equal to the third time, and the predetermined signal level is a high level. The window signal generation circuit,
A first variable delay circuit that inputs the timing signal and outputs a first delay timing signal generated by delaying the second time by subtracting the third time from the second time;
A second variable delay circuit that receives the first delay timing signal and outputs a second delay signal generated by delaying the delay time by twice the third time;
An exclusive OR circuit that inputs the first delay timing signal and the second delay timing signal and takes an exclusive OR,
A third variable delay circuit that receives the timing signal and delays the timing signal by a first time equal to the third time,
14. The jitter test circuit according to claim 13, wherein an output of the third variable delay circuit is output as the comparison timing signal, and an output of the exclusive OR circuit is output as the window signal. The window signal generation circuit,
A first variable delay circuit that inputs the timing signal and outputs a delay timing signal generated by delaying the timing signal by twice the third time;
An exclusive-OR circuit that receives the timing signal and the delayed timing signal and takes an exclusive-OR,
A second variable delay circuit that receives an output of the exclusive OR circuit and delays the output by a time obtained by subtracting the third time from the second time;
A third variable delay circuit that receives the timing signal and delays the timing signal by a first time equal to the third time,
14. The jitter test circuit according to claim 13, wherein an output of the third variable delay circuit is output as the comparison timing signal, and an output of the second variable delay circuit is output as the window signal. The comparison circuit includes:
A first flip-flop that captures a signal level of the window signal at a rise of the comparison timing signal;
A second flip-flop that captures a signal level of the window signal at a fall of the comparison timing signal;
13. A NAND circuit which receives an output of the first flip-flop and an output of the second flip-flop, performs an AND operation, inverts the output, and outputs a failure determination signal, and outputs a NAND circuit. 16. The jitter test circuit according to 14 or 15. A jitter test circuit for inputting a data signal, extracting a timing signal synchronized with the data signal, and retrieving the timing signal output from a clock recovery PLL circuit for reproducing the timing signal.
The timing signal and delay control information that specifies the delay time as the number of basic delay units are input, and the timing signal for comparison generated by delaying the timing signal by a first time based on the delay control information, and A window signal having a window having a predetermined signal level within a third time width before and after a rising point and a falling point of a signal obtained by delaying a timing signal by a second time is generated and output. A window signal generation circuit to
A comparison circuit that compares the comparison timing signal with the window signal, detects whether a rising point and a falling point of the comparison timing signal are within the window, and outputs a comparison result;
A homo-code continuity data detection circuit that outputs a homo-code continuation data detection signal when detecting that data of the same code is continued for a predetermined number of data or more in the data signal,
A command including an operation mode designation and the comparison result are input to control generation of the delay control information and execution of a test operation. In the calibration mode, the second time has no jitter at the first time. Search for delay control information equal to the time obtained by adding one cycle of the timing signal in the case, and set the second time based on the delay control information searched for in the calibration mode in the pass / fail determination mode. A test control circuit that sets a third time to a jitter standard value and determines pass / fail based on a comparison result from the comparison circuit. The test control circuit includes:
In the calibration mode, the delay control information is set after setting the second time to an initial time longer than a time obtained by adding the first time and the third time to one cycle of the timing signal. The delay control information is operated to gradually reduce the delay time of the second time in increments of a basic delay unit, and the comparison result from the comparison circuit is monitored. Searching for delay control information corresponding to the second time when a point and a falling point are located in the center of the window;
In the pass / fail determination mode, the second time is set based on the delay control information searched in the calibration mode, delay control information is generated based on a command input from the outside, and the third time is set to the jitter standard value. When the number of times of occurrence of the comparison result indicating the deviation of the rising point and the falling point of the comparison timing signal from the window is greater than or equal to a predetermined number, 18. The jitter test circuit according to claim 17, wherein the circuit is determined to be defective. 17. A semiconductor device comprising any one of the jitter test circuits according to claim 1. A frequency dividing circuit for dividing a reference timing signal input from the outside to generate a timing signal;
A jitter test circuit according to any one of claims 1 to 16,
A semiconductor device, wherein the timing signal is supplied to the jitter test circuit as a test target signal. A PLL circuit for generating a timing signal synchronized in phase with a reference timing signal input from the outside;
A jitter test circuit according to any one of claims 1 to 16,
A semiconductor device, wherein the timing signal is supplied as a test target signal to the jitter test circuit. 22. The semiconductor device according to claim 21, wherein the PLL circuit is a multiplying PLL circuit that generates a timing signal synchronized in phase with a frequency multiplied by a reference timing signal. A clock recovery PLL circuit for inputting a data signal from outside and extracting and reproducing a timing signal synchronized with the data signal;
A jitter test circuit according to claim 17 or 18,
A semiconductor device, wherein the timing signal is supplied as a test target signal to the jitter test circuit. In a jitter test method for detecting a jitter of a timing signal that periodically repeats a high level and a low level alternately,
If there is no jitter, the rising and falling points of the comparison timing signal generated by delaying the jitter measurement target timing signal should be positioned at the center of the window of a predetermined width provided for each. A calibration phase for adjusting the number of basic delay units of the delay circuit to determine the position of the window,
The window provided at the position adjusted in the calibration phase is compared a plurality of times with the rising point and the falling point of the comparison timing signal, and at least one of the rising point and the falling point is the window having the predetermined width. A jitter test method, comprising: a pass / fail judgment phase for judging a defect when the number of times judged to be outside is equal to or more than a predetermined number. In a jitter test method for detecting a jitter of a timing signal that periodically repeats a high level and a low level alternately,
If there is no jitter, the rising and falling points of the comparison timing signal generated by delaying the jitter measurement target timing signal should be positioned at the center of the window of a predetermined width provided for each. A calibration phase for adjusting the number of basic delay units of the delay circuit to determine the position of the window,
The rising and falling points of the comparison timing signal and the window adjusted in the calibration phase are compared a plurality of times while changing the width of the window by changing the width on both sides with respect to the center of the window. A jitter measurement phase for detecting a critical window width to be determined, determining a jitter value, encoding and outputting the jitter value. The calibration phase includes:
A timing signal for jitter measurement is delayed by a first time to generate a comparison timing signal, and the timing signal is longer than a time obtained by adding the first time and the third time to one cycle of the timing signal. A first step of providing a window having the third time width before and after a rising point and a falling point of a signal delayed by a second time set to a large value, respectively;
A second step of comparing and determining whether a rising point of the comparison timing signal is within the window and whether a falling point is within the window; and, in the second step, the comparison timing signal. A third step of reducing the second time by one basic delay unit and returning to the second step when it is determined that neither the rising point nor the falling point is within the window;
If it is determined in the second step that either the rising point or the falling point of the comparison timing signal is within the window, the number of basic delay units corresponding to the second time at that time is determined. A fourth step of storing as a maximum basic delay unit number;
A fifth step of reducing the second time by one basic delay unit;
A sixth step of determining whether a rising point of the comparison timing signal is outside the window and a falling point of the comparison timing signal outside the window; and A seventh step of reducing the second time by one basic delay unit and returning to the sixth step when it is determined that both the rising point and the falling point are within the window;
When it is determined in the sixth step that either the rising point or the falling point of the comparison timing signal is outside the window, the number of basic delay units corresponding to the delay value at that time is set to the minimum basic delay. An eighth step of storing the number of units;
By adding the maximum basic delay unit number and the minimum basic delay unit number and dividing by two, a second time that has been calibrated, which is a time obtained by adding the first time to one cycle of the timing signal, is obtained. 26. The jitter test method according to claim 24, further comprising: calculating a number of corresponding basic delay units. In the second step, the number of times that it is determined that the rising point and the falling point of the comparison timing signal are within the window as a result of a plurality of comparisons is a predetermined number of times. When it is the above, the judgment that it is in the window is valid,
In the sixth step, it is determined whether or not the rising and falling points of the comparison timing signal are within the window. 27. The jitter test method according to claim 26, wherein when the number of times is equal to or more than the number of times, the determination of being outside the window is made valid. The jitter measurement phase includes:
The timing signal for comparison is generated by delaying by a first time determined by the number of basic delay units specified in a command input from the outside from the timing signal to be measured and the rising or falling point of the timing signal From the center of the window to both sides from the center of the window by setting the second time from the center of the window to the center of the corresponding window by adding the first time to the time determined by the number of basic delay units calculated in the calibration phase. A first step of setting a third time for determining one side width of the widening window width to be equal to the first time and setting the number of measurements;
A second step of comparing and determining whether a rising point of the comparison timing signal is within the window and whether a falling point is within the window;
When the rising and falling points of the comparison timing signal are determined to be within the window in the second step, and the number of times determined to be within the window reaches the first predetermined number, A third step of reducing the third time by one basic delay unit and returning to the second step;
In the second step, when it is determined that either the rising point or the falling point of the comparison timing signal is not within the window, the number of times that the comparison signal is determined not to be within the window has reached the second predetermined number. A fourth step of storing the number of basic delay units corresponding to the third time as the number of basic delay units corresponding to the jitter value,
A fifth step of determining whether or not the steps from the second step to the fourth step have been performed the number of times measured;
When it is determined in the fifth step that the number of measurements has been performed, the number of basic delay units corresponding to the stored jitter values for the number of measurements is read out, and the number of basic delay units corresponding to the averaged jitter value is read out. A sixth step of calculating
26. The jitter test method according to claim 25, further comprising: a seventh step of encoding and outputting a basic delay unit number corresponding to the averaged jitter value.

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