JP2010021912A - Jitter measuring circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To digitally output a jitter quantity without measuring a cycle of a cyclic signal. <P>SOLUTION: A jitter measuring circuit 10 includes: an inter-edge pulse generation section 1 for generating an inter-edge pulse signal 6 by delaying an input signal 5 to be measured by a first time, that is a prescribed time unit, from an edge of the signal to be measured; a pulsewidth remainder division section 2 for dividing the inter-edge pulse signal 6 by a value, obtained by multiplying a second time that is a prescribed time unit by an integer to output remainder results of the division arithmetic operation as a remainder result signal M; and an one-hot-state section 4 to output a value of the integer when a value of the remainder result signal M becomes minimum, as a cycle jitter value signal D of the inter-edge pulse signal 6. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a jitter measurement circuit that measures the amount of jitter (frequency, phase) of a signal.

  In recent years, a phase-locked-loop (PLL) circuit is built in a system integrated circuit for optical discs. The PLL circuit is widely used for generating a reference timing signal for internal operation of an integrated circuit such as serial communication or recording on a disk.

  If the reference timing signal generated from the PLL circuit includes jitter, which is a temporal fluctuation, a communication error occurs during serial communication. In addition, recording on a disc causes problems such as deterioration of recording quality. As described above, when jitter is included, the integrated circuit causes a malfunction of the logic circuit, and therefore, it is necessary to manage the amount of jitter to a certain value or less. Here, the amount of jitter is standardized in serial communication, and the amount of jitter included in the data after recording is also provided for recording on the disc, so that the jitter amount of the reference timing signal can be easily It is required to be able to measure.

  Furthermore, when the steady jitter inherent in the integrated circuit is large, it is necessary to remove the defective product that does not satisfy the standard at the time of product shipment with an LSI tester or the like.

  Conventionally, for example, when measuring the jitter amount of a reference timing signal and recognizing the result, the reference timing signal itself, a divided signal of the reference timing signal, or a data signal generated by the reference timing signal is integrated. Measurement was performed using a dedicated measuring instrument (TIA (time interval analyzer), sampling oscilloscope, etc.) output from the circuit and connected to the outside of the integrated circuit and a measuring instrument having a jitter measuring function.

  When measuring a circuit specialized for the jitter measurement function inside an integrated circuit, the pulse width obtained by detecting the phase difference between the reference timing signal and the measurement signal with a phase comparator is extremely small. Therefore, using a charge pump circuit driven by the output of a phase comparator or the like and an integrator for accumulating the output charge of the charge pump circuit, a method for converting the minimum time into a current or voltage and outputting it as an analog value Measurements can be made by connecting a simpler measuring instrument (such as a voltmeter or frequency counter) to the outside, such as converting to a periodic signal that fluctuates the frequency or period according to the amount of jitter, and outputting it. Had gone.

  In particular, when a circuit specialized for the jitter measurement function is built in an integrated circuit, an analog-to-digital converter is installed in the analog circuit in order to capture the amount of jitter quantitatively and manage the amount of jitter easily. It is necessary to convert the value into a digital value or mount a counter to convert the period of the periodic signal into a digital value and output it.

  Hereinafter, a jitter detection circuit disclosed in Patent Document 1 will be described with reference to the drawings. FIG. 15 is a block diagram showing a configuration of a conventional jitter detection circuit. The configuration and operation will be described with reference to FIG. The jitter detection circuit includes a comparison pulse generation circuit 103, a periodic signal generation circuit 104, and a counter 105.

  First, the comparison pulse generation circuit 103 receives the input signals 101 and 102 and outputs a phase difference comparison pulse 1031. When the input signals 101 and 102 have the same stable frequency, the comparison pulse generation circuit 103 is configured by a circuit shown in FIG. 16, for example. As shown in the figure, the EXOR circuit 1032 outputs a phase difference comparison pulse 1031 whose pulse width is the phase difference between the rising edges and the falling edges of each other by using the two inputs as input signals 101 and 102. .

  Next, the phase difference comparison pulse 1031 is input to the periodic signal generation circuit 104. FIG. 17 is a block diagram showing a configuration of the periodic signal generation circuit 104. As shown in the figure, the periodic signal generation circuit 104 includes a charge pump circuit 1042, a triangular wave generation circuit 1043, and a comparator 1044.

  Hereinafter, the operation of the periodic signal generation circuit 104 will be described with reference to FIG. First, the charge pump circuit 1042 outputs the charge from the current source 10421 to the triangular wave generation circuit 1043 through the switch 10422 controlled by the phase difference comparison pulse 1031. In the triangular wave generation circuit 1043, charges output from the charge pump circuit 1042 are sequentially stored in the capacitor 10431. Through the above process, the amount of time given by the phase difference comparison pulse 1031, that is, the phase difference between the input signals 101 and 102 of this circuit is converted into a current pulse and then converted into a charge amount.

  FIG. 19 is a diagram showing how jitter is accumulated. FIG. 19 shows the relationship between the output of the capacitor 10431, that is, the potential of the node 10433 and the phase difference comparison pulse 1031. As described above, the charge pump circuit 1042 and the triangular wave generation circuit 1043 are time / voltage conversion circuits. Since the pulse width of the phase difference comparison pulse 1031 is a time for charging the capacitor 10431, as shown in the figure, when the pulse width is large, the potential of the node 10433 increases greatly, and when the pulse width is narrow, the increased potential is small. Accordingly, the output of the capacitor 10431, that is, the node 10433 has a potential determined by the accumulation of the capacitance value and the phase difference between the input signals 101 and 102. The node 10433 is input to the comparator 1044.

  Node 10433 is the first input to comparator 1044 and any reference input 1042 is the second input. Therefore, the output of the comparator 1044 changes when the potential of the node 10433 exceeds the potential of the reference input 1045.

  In addition, the triangular wave generation circuit 1043 includes a switch 10432 for resetting the capacitor 10431. The triangular wave generation circuit 1043 uses the comparator output 1041 as an input to the switch 10432, thereby releasing the accumulated charge and setting the potential of the node 10433 to zero.

  That is, in the triangular wave generation circuit 1043, as described above, the potential of the node 10433 increases according to the phase difference between the two signals because it indicates the accumulated amount of the phase difference between the input signals 101 and 102. When this exceeds the reference voltage 1042, the output of the comparator 1044 changes, the switch 10432 is turned on, and the capacitor 10431 is refreshed. Simultaneously with the refresh, the comparator output 1044 changes again, and the next accumulation starts again from this point.

Therefore, as a result of the above, the output 1041 becomes a periodic signal. The period of the periodic signal 1041 is counted by an arbitrary clock 1051 using the counter 105, and the count result is used as the digital numerical value 106 as the jitter detection circuit output.
JP 2001-127623 A

  However, with the conventional jitter measurement technology, in order to capture the amount of jitter quantitatively and make it easy to manage the amount of jitter, the counter is operated with a constant counting clock and the period of the periodic signal is converted to a digital value. There is a problem that it must be output.

  The reason is that the phase difference between the two input signals is converted into a pulse width, a periodic signal is generated by accumulating the converted phase difference, and the jitter amount is measured based on the generated periodic signal. It is. In order to measure the jitter of the input signal, the phase difference between the two input signals is converted into a pulse width. However, since the pulse width converted from the phase difference between the two input signals is very small, a very fast sampling clock is required to measure this pulse width, and the pulse width is further converted into current and voltage. Even in this case, since the voltage or current is very small, it cannot be observed accurately. For this reason, in the conventional jitter measurement technology, the pulse width is sequentially accumulated to convert it into a periodic signal having a period corresponding to the amount of jitter, but the period of the converted periodic signal is measured by a counter. Otherwise, the jitter amount cannot be detected.

  Since the period (frequency) of the converted periodic signal varies according to the phase difference, the count value increases when the phase difference is large, and conversely the count value decreases when the phase difference is small. Here, in order to operate the counter, a count clock is required, and the magnitude of the phase difference can be determined for the first time based on the count value indicated by the counter. Alternatively, although it is possible to perform a counting operation using the periodic signal itself as a counter clock, in such a case, a configuration in which the count value is read at a constant interval is required. By reading at a constant interval, it is possible to determine the magnitude of the phase difference based on the count value at each interval or the increase / decrease in the count value at each interval. Therefore, by installing the counter, it is possible to store and manage the jitter amount by converting the period of the periodic signal into a digital value, but the count value is updated only at regular intervals or read at regular intervals. There is a need.

  The jitter measuring circuit according to the present invention includes an inter-edge pulse generator that generates an inter-edge pulse signal by delaying an input signal under measurement by a first time that is a predetermined time unit from the edge of the signal under measurement. A pulse width remainder dividing unit that divides the inter-edge pulse signal by a value obtained by multiplying a second time, which is a predetermined time unit, by an integer, and outputs a remainder result of the division operation as a remainder result signal, and the remainder A one-hot state unit that outputs the integer value when the value of the result signal is minimum as a cycle jitter value signal of the inter-edge pulse signal.

  As a result, a cycle jitter value signal indicating how many times the pulse signal between edges corresponds to a predetermined time unit can be calculated. For this reason, since the jitter amount can be digitally output without measuring the period of the periodic signal, a counter for measuring the periodic signal and a clock for operating the counter become unnecessary.

  According to the jitter measuring circuit of the present invention, it is possible to easily manage the jitter amount by quantitatively capturing the jitter amount without requiring a counter or a clock for operating the counter.

Embodiment 1 FIG.
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. First, the configuration of the jitter measurement circuit according to the present embodiment will be described with reference to FIG.

  FIG. 1 is a block diagram showing a configuration of a jitter measurement circuit 10 according to the first embodiment. As shown in the figure, the jitter measurement circuit 10 includes an inter-edge pulse generation circuit 1 as an inter-edge pulse generation unit, a pulse width remainder division circuit 2 as a pulse width remainder division unit, and a one-hot state part. A state circuit 3 and an accumulation holding circuit 4 as an accumulation holding circuit unit are provided.

  A signal under measurement 5 is supplied to the inter-edge pulse generation circuit 1. The inter-edge pulse generation circuit 1 calculates an inter-edge pulse for each rising edge of the supplied signal 5 to be measured by calculating a rising edge delayed by a predetermined first time and an inter-edge width to the next rising edge. The signal 6 is supplied to the pulse width remainder dividing circuit 2. Details of processing by the inter-edge pulse generation circuit 1 will be described later.

  FIG. 2 is a circuit diagram showing a detailed configuration of the inter-edge pulse generation circuit 1 according to the first embodiment. As shown in the figure, the inter-edge pulse generation circuit 1 includes PMOS transistors MP101 and MP102, NMOS transistors MN101 to MN112, a Td time delay element 120 that delays an input signal by Td time, and a resistance element. Is done. The signal under measurement 5 is connected to the gate terminals of MP101, MN106 and MN102, the drain terminals of MP101 and MN106 are short-circuited, connected to the input terminal of the Td time delay element 120, and also connected to the gate terminal of MN101. The The drain terminal of MN101 is connected to the power supply through a resistor and also connected to the gate terminal of MN110. The drain terminals of MN102 and MN104 are short-circuited and connected to the power supply through a resistor and also connected to the gate terminal of MN112. The source terminals of MN101 and MN102 are short-circuited and connected to the drain terminal of MN103, and the source terminals of MN103 and MN105 are short-circuited and grounded via a resistor. The gate terminal of MN104 is connected to a power supply through a resistor, and the source terminal is connected to the drain terminal of MN105.

  The output terminal of the Td time delay element 120 is connected to the gate terminals of MP102, MN107, and MN108, and the drain terminals of MP102 and MN107 are short-circuited and connected to the gate terminal of MN109. The drain terminal of the MN 108 becomes the inter-edge pulse signal 6, but is connected to the power supply through a resistor and also connected to the gate terminal of the MN 103. The drain terminals of MN109 and MN111 are short-circuited and connected to the power supply through a resistor and also connected to the gate terminal of MN105. The source terminals of MN108 and MN109 are short-circuited and connected to the drain terminal of MN110, and the source terminals of MN110 and MN112 are short-circuited and grounded via a resistor. The gate terminal of MN111 is connected to a power supply through a resistor, and the source terminal is connected to the drain terminal of MN112. The source terminals of MP101 and MP102 are directly connected to the power source, and the source terminals of MN106 and MN107 are grounded as they are.

  When the rising edge of the signal under measurement 5 occurs, the MP 101 enters the Off state, and the MN 102 and the MN 106 enter the On state, so that the MN 101 enters the Off state. As a result, the MN 110 enters the On state, but the signal under measurement 5 is delayed by the time Td through the Td time delay element 120 and supplied to the MPs 102, MN107, MN108, and MN109. At the time when the MN 107 and the MN 108 are in the On state, the MP 102 and the MN 109 are in the Off state. Therefore, at the time when the rising edge of the signal under measurement 5 occurs, the pulse signal 6 between edges becomes 0 because the MN 108 and MN 110 are in the On state.

  Next, when the rising edge potential of the signal under measurement 5 reaches the gate terminals of the MP102, MN107, and MN108 at the time when Td time has elapsed from the time when the rising edge of the signal under measurement 5 occurs, MP102 and MN109 are in the On state. Since MN107 and MN108 are in the off state, the inter-edge pulse signal 6 is 1, and the MN105 is in the off state. Further, since the MN 103 is in the On state and the MN 102 is in the On state, the MN 112 is in the Off state.

  Subsequently, when the falling edge of the signal under measurement 5 occurs, the MN 102 and the MN 106 are turned off, and the MP 101 is turned on, so that the MN 101 is also turned on. Further, the MN 110 is in the Off state and the MN 105 is in the On state. However, since the MN 108 is in the Off state, the inter-edge pulse signal 6 also remains at 1.

  Thereafter, when the falling edge potential of the signal under measurement 5 reaches the gate terminals of the MP102, MN107, and MN108 at the time when the time Td has elapsed from the time when the trailing edge of the signal under measurement 5 occurs, MP102 and MN109 are in the off state. MN107 and MN108 are in the On state, but since the MN110 remains in the Off state, the inter-edge pulse signal 6 also remains at 1.

  As described above, the inter-edge pulse generation circuit 1 outputs 0 to the inter-edge pulse signal 6 only until the time Td elapses after the rising edge of the signal under measurement 5 is generated, and during other periods, the inter-edge pulse signal 1 is output. It operates to output 1 to the pulse signal 6.

  The pulse width remainder dividing circuit 2 divides the supplied inter-edge pulse signal by a value obtained by multiplying a predetermined second time by an integer, and outputs a remainder result obtained by the division operation as a remainder result signal. More specifically, when the second time is a multiplicand and a non-negative integer that is an integer is a multiplier, the pulse width remainder dividing circuit 2 converts the supplied inter-edge pulse signal 6 into the second time and a non-negative integer. Subtract by product with. Then, the pulse width remainder dividing circuit 2 divides the subtracted positive remainder into non-negative integers, and uses the divided signal group as a remainder result signal M [0: n] (n is a natural number of 1 or more). This is supplied to the state circuit 3. Details of processing by the pulse width remainder dividing circuit 2 will be described later.

  FIG. 3 is a circuit diagram showing a detailed configuration of the pulse width remainder dividing circuit 2 according to the first embodiment. As shown in the figure, the pulse width remainder dividing circuit 2 includes an inverter INV200 that receives the inter-edge pulse signal 6, a cell M0 including NMOS transistors MN201 to MN205, and a cell M1 including NMOS transistors MN206 to MN210. A cell M2 including NMOS transistors MN211 to M215 and a cell Mn (not shown) are connected in cascade, and the cells M0, M1, M2, and Mn have the same configuration.

  In addition to being connected to the input of the INV 200, the inter-edge pulse signal 6 is connected to the gate terminals of the MN 201, MN 203, MN 206, and MN 211, and is similarly connected to Mn (not shown). In addition, the output of the INV 200 that receives the inter-edge pulse signal 6 is connected to the gate terminals of the MN 202, MN 205, MN 207, and MN 212, and is similarly connected to Mn (not shown).

  The drain terminal of MN201 is output as MB [0], is connected to the gate terminal of MN210, and is connected to the power supply through a resistor. The drain terminals of MN202 and MN204 are short-circuited, connected to the gate terminal of MN208 as an M [0] output, and connected to the power supply via a resistor. The source terminals of MN201 and MN202 are short-circuited and connected to the drain terminal of MN203, and the source terminals of MN203 and MN205 are short-circuited and grounded via a resistor. The gate terminal of the MN 204 is connected to the power supply through a resistor, and the source terminal is connected to the drain terminal of the MN 205. The drain terminal of the MN 206 is output as MB [1], is connected to the gate terminal of the MN 215, and is connected to the power supply through a resistor. The drain terminals of MN 207 and MN 209 are short-circuited, connected to the gate terminal of MN 213 as an M [1] output, and connected to the power supply via a resistor. The source terminals of MN206 and MN207 are short-circuited and connected to the drain terminal of MN208, and the source terminals of MN208 and MN210 are short-circuited and grounded via a resistor. The gate terminal of MN209 is connected to a power supply through a resistor, and the source terminal is connected to the drain terminal of MN210. The drain terminal of the MN 211 is output as MB [2] and is connected to a power source through a resistor. The drain terminals of MN212 and MN214 are short-circuited and output as an M [2] output, and are connected to a power source via a resistor. The source terminals of MN211 and MN212 are short-circuited and connected to the drain terminal of MN213, and the source terminals of MN213 and MN215 are short-circuited and grounded via a resistor. The gate terminal of the MN 214 is connected to the power supply through a resistor, and the source terminal is connected to the drain terminal of the MN 215.

  When the rising edge of the inter-edge pulse signal 6 occurs, the MN 201 and MN 203 of the cell M0, the MN 206 of the cell M1, and the MN 211 of the cell 2 are simultaneously turned on. Further, since the output of INV200 is 0, MN202 and MN205 of cell M0, MN207 of cell M1, and MN212 of cell M2 are simultaneously turned off. When the MN 201 and MN 203 of the cell M0 are in the On state, 0 is output from MB [0] that is the output of the cell M0, and when MN 202 and MN 205 are in the Off state, 1 is output from M [0]. .

  Next, when M [0] changes to 1, the MN 208 of the cell M1 enters the On state, so that MB [1] outputs 0, and when MB [0] changes to 0, the MN 210 of the cell M1 turns Off. In order to enter the state, 1 is output from M [1].

  Further, when M [1] changes to 1, the MN 213 of the cell M2 enters the On state, so that MB [2] outputs 0, and when MB [1] changes to 0, the MN 215 of the cell M1 changes to the Off state. Therefore, 1 is output from M [2].

  As described above, when the pulse width remainder dividing circuit 2 changes M [N−1] (N is a natural number between 1 and n) to 1 and MB [N−1] changes to 0, the cell width sequentially It operates so that 0 is output from MB [N] of Mn and 1 is output from M [N].

  In addition, when the falling edge of the inter-edge pulse signal 6 occurs, the pulse width remainder dividing circuit 2 simultaneously turns off the MN 201 in the cell M0, the MN 206 in the cell M1, and the MN 211 in the cell 2, so that MB [0: n] all output 1 simultaneously. Also, when the output of INV200 becomes 1, the MN205 of the cell M0 is turned off, and MB [0: n] simultaneously changes to 1, so that the MN210 of the cell M1 and the MN215 of the cell M2 are simultaneously turned on. , M [0: n] all output 0 simultaneously.

  The one-hot state circuit 3 outputs an integer value when the value of the supplied remainder result signal is minimum as a cycle jitter value signal of the inter-edge pulse signal 6. More specifically, the one hot state circuit 3 uses the supplied remainder result signal M [0: n] to calculate the quotient of division from the smallest positive remainder, whereby the inter-edge pulse signal 6 is obtained. A non-negative integer indicating how many times the second time is equivalent is calculated. The one-hot state circuit 3 supplies the calculated non-negative integer as the cycle jitter value signal D [0: n−1] to the cumulative holding circuit 4 and outputs it as the cycle jitter value signal D [0: n−1]. To do. The details of the processing by the one hot state circuit 3 will be described later.

  The accumulation holding circuit 4 accumulates and holds the cycle jitter value for each supplied inter-edge pulse signal. That is, the cycle jitter value signal D [0: n−1] calculated each time the inter-edge pulse signal 6 is generated is accumulated and held as the accumulated jitter amount, and the accumulated jitter value signal Q [0: n−1]. Output as. Details of the processing by the cumulative holding circuit 4 will be described later.

  FIG. 4 is a circuit diagram showing a detailed configuration of the one-hot state circuit 3 and the cumulative holding circuit 4 according to the first embodiment. As shown in the figure, the one-hot state circuit 3 is composed of 2-input ExclusiveOR gates EXOR300 to EXOR [300 + n-1] having M [0: n] as inputs, and outputs D [0: n-1]. . M [J] and M [J + 1] are input to EXOR [300 + J] (J is an integer greater than or equal to 0 and less than n), and D [J] is output. The accumulation holding circuit 4 includes an inverter INV400 that receives the inter-edge pulse signal 6, an NAND gate ND400 to ND [400 + n−1], and a D type flip-flop FF400 to FF [400 + n−1]. The output of INV400 and the output of ND [400 + J] with D [J] as input are connected to the clock input of FF [400 + J]. Further, a power source is connected to the D input of FF [400 + J], and the Q output is Q “J”.

  EXOR [300 + J] outputs the exclusive logic of the input M [J] and M [J + 1] as D [J]. ND [400 + J] that receives D [J] and the output of INV400 outputs 1 when D [J] is 1 and the inter-edge pulse signal 6 is 0. Therefore, ND [400 + J] FF [400 + J] having the output as the clock input and Q [J] as the Q output is only Q [J] corresponding to D [J] which becomes 1 during the period when the inter-edge pulse signal 6 is 0. It operates to output 1 and continue to hold it thereafter.

  Next, the operation of the jitter measurement circuit according to the first embodiment will be described with reference to FIGS. First, the operation of the inter-edge pulse generation circuit 1 will be described with reference to FIG. FIG. 5 is a timing chart showing the operation of the inter-edge pulse generation circuit 1.

  FIG. 5 shows the measured signal 5 to be supplied and the inter-edge pulse signal 6 output from the inter-edge pulse generation circuit 1. FIG. 5A is a diagram illustrating an example in the case where the supplied signal under measurement 5 does not have jitter that is temporal fluctuation. FIG. 5B is a diagram showing an example in the case where the supplied signal under measurement 5 has jitter that is temporal fluctuation.

First, the operation of the inter-edge pulse generation circuit 1 when there is no jitter in the signal under measurement 5 will be described with reference to FIG. As shown in the figure, the signal under measurement 5 is generated at time T1. The edge-to-edge pulse generation circuit 1 generates a rising edge of the edge-to-edge pulse signal 6 at time T2 obtained by delaying the rising edge of the signal under measurement 5 generated at time T1 by a first time. The inter-edge pulse generation circuit 1 generates the falling edge of the inter-edge pulse signal 6 at time T3 when the next rising edge of the signal under measurement 5 occurs. Here, the Td time which is the first time can be expressed by the following formula 1 using the time T1, the time T2, and the time T3.
Td = (T3-T1)-(T3-T2) = T2-T1 Formula 1

Further, assuming that the time from time T1 to time T3, which is the cycle time of the signal under measurement 5, is Tcyc time, the Tcyc time can be expressed by the following Equation 2.
Tcyc = T3-T1 ... Formula 2

When the pulse width of the inter-edge pulse signal 6 generated from the rising edge of the signal under measurement 5 generated at time T1 and the rising edge of the signal under measurement 5 generated at time T3 is Teg, the pulse width Teg is Using Equation 1 and Equation 2 described above, it can be expressed by Equation 3 below.
Teg = T3-T2 = Tcyc-Td Equation 3

The inter-edge pulse generation circuit 1 generates an inter-edge pulse signal 6 every time a rising edge of the signal under measurement 5 occurs. For this reason, the inter-edge pulse signal 6 is similarly generated from the time T4 in which the rising edge of the signal under measurement 5 generated at time T3 is delayed by the time Td to the time T5 when the next rising edge occurs. . Further, the inter-edge pulse signal 6 is sequentially applied in a similar manner from time T6 where the rising edge of the signal under measurement 5 generated at time T5 is delayed by Td time to time T7 when the next rising edge occurs. appear. Therefore, when there is no jitter in the signal under measurement 5, the pulse width of the inter-edge pulse signal 6 from time T4 to time T5 and the pulse width of the inter-edge pulse signal 6 from time T6 to time T7 are: It is the same as Teg and can be represented by the following equation 4.
T5−T4 = T7−T6 = Teg Expression 4

  In the above description, the rising edge of the inter-edge pulse signal 6 is generated from the time when the rising edge of the signal under measurement 5 is delayed by Td time, and the next rising edge of the signal under measurement 5 is generated. Although the falling edge of the inter-edge pulse signal 6 is generated, the present invention is not limited to this. That is, the rising edge of the inter-edge pulse signal 6 is generated from the time when the falling edge of the signal under measurement 5 is delayed by Td time, and the inter-edge pulse is generated at the time when the falling edge of the next signal under measurement 5 is generated. The falling edge of the signal 6 may be generated.

  Next, the operation of the inter-edge pulse generation circuit 1 when the signal under measurement 5 has jitter will be described with reference to FIG. Times T1, T2, T3, T4, and T5 are the same as the time shown in FIG. For this reason, the Tcyc time from the time T1 to T3, which is the cycle time of the signal under measurement 5, is expressed by the above-described equation 2. Further, the pulse width Teg of the inter-edge pulse signal 6 from the time T2 to the time T3 is expressed by the above-described Expression 3.

As shown in FIG. 5B, the inter-edge pulse generation circuit 1 starts the time T8 when the next rising edge occurs from the time T4 obtained by delaying the rising edge of the signal under measurement 5 generated at time T3 by the time Td. The inter-edge pulse signal 6 is generated during the period up to. As shown in the figure, it is assumed that jitter that is longer in time than Tcyc time is included from time T3 to time T8, which is the cycle time of the signal under measurement 5. In this case, the time from the time T3 to the time T8, which is the cycle time of the signal under measurement 5, is the Tcyc time that is the difference time from the time T3 to the time T5 and the jitter caused by the jitter from the time T5 to the time T8. Using the time Tjt1 time, it can be expressed by the following equation 5.
T8-T3 = (T5-T3) + (T8-T5) = Tcyc + Tjt1
... Formula 5

Further, the inter-edge pulse signal 6 generated between the time T4 and the time T8 can be expressed by the following Expression 6.
T8-T4 = (T8-T3) -Td = Tcyc + Tjt1-Td
... Equation 6

Further, when the inter-edge pulse signal 6 generated between the time T4 and the time T8 shown in the above-described expression 6 is expressed using the pulse width Teg based on the above-described expression 3, the following expression 7 is expressed. be able to.
T8-T4 = Teg + Td + Tjt1-Td = Teg + Tjt1
... Equation 7

The inter-edge pulse generation circuit 1 also performs the inter-edge pulse signal from time T9 obtained by delaying the rising edge of the signal under measurement 5 generated at time T8 by Td time to time T10 when the next rising edge occurs. 6 is generated. As shown in the figure, it is assumed that jitter that is shorter in time than the Tcyc time is included from the time T8 to the time T10, which is the cycle time of the signal under measurement 5. In this case, the time from the time T8 to the time T10, which is the cycle time of the signal under measurement 5, is the Tcyc time that is the difference time from the time T8 to the time T11 and the jitter caused by the jitter from the time T10 to the time T11. Using the time Tjt2 time, it can be expressed by the following formula 8.
T10-T8 = (T11-T8)-(T11-T10)
= Tcyc-Tjt2 Equation 8

Further, the inter-edge pulse signal 6 generated between the time T9 and the time T10 can be expressed by the following Expression 9.
T10-T9 = (T10-T8) -Td
= Tcyc-Tjt2-Td Equation 9

Furthermore, when the inter-edge pulse signal 6 generated between the time T9 and the time T10 shown in the above-described Expression 9 is expressed using the pulse width Teg based on the above-described Expression 3, it is expressed by the following Expression 7. be able to.
T10-T9 = Teg + Td-Tjt1-Td
= Teg-Tjt2 Equation 10

  Therefore, from the above-described Equation 5, Equation 7, Equation 8, and Equation 10, when the signal under measurement 5 includes jitter, the inter-edge pulse signal 6 generated by the inter-edge pulse generation circuit 1 is Regardless of the rising edge time (T1, T3, T5, T7) of the measurement signal 5, the pulse width Teg of the inter-edge pulse signal 6 when there is no jitter, and the time when the cycle time of the signal under measurement 5 varies due to jitter ( Tjt1, Tjt2).

  Next, the operation of the pulse width remainder dividing circuit 2 will be described with reference to FIG. FIG. 6 is a timing chart showing the operation of the pulse width remainder dividing circuit 2.

  FIG. 6 shows the inter-edge pulse signal 6 supplied and the residue result signal M [0: n] output from the pulse width remainder dividing circuit 2. FIG. 6A is a diagram illustrating an example in the case where the supplied signal under measurement 5 does not have jitter that is temporal fluctuation. FIG. 6B is a diagram illustrating an example in the case where the supplied signal under measurement 5 has jitter that is temporal fluctuation. The Td time and pulse width Teg shown in FIG. 6 are the same as the Td time and pulse width Teg shown in FIG.

  First, the operation of the pulse width remainder dividing circuit 2 when there is no jitter in the signal under measurement 5 will be described with reference to FIG. When the rising edge of the supplied inter-edge pulse signal 6 occurs at time T2, the pulse width remainder dividing circuit 2 sets 1 to the remainder result signal M [0] at time T11 obtained by adding the second time to time T2. Output. Here, the second time is defined as Ts time. When the remainder result signal M [0] changes to 1 at time T11, the pulse width remainder dividing circuit 2 outputs 1 to the remainder result signal M [1] at time T12 obtained by adding Ts time to time T11. Further, when the remainder result signal M [1] changes to 1 at time T12, the pulse width remainder dividing circuit 2 outputs 1 to the remainder result signal M [2] at time T13 obtained by adding Ts time to time T12.

  As described above, the pulse width remainder dividing circuit 2 outputs 1 to the remainder result signal M [0] at the time obtained by adding the Ts time to the rising edge time starting from the rising edge time of the inter-edge pulse signal 6. Following that output, 1 is sequentially output to the residue result signal M [N + 1] at the time when the Ts time is added to the time when the residue result signal M [N] (N is a natural number between 1 and n) changes to 1. To do.

  On the other hand, when the pulse width remainder dividing circuit 2 detects the falling edge of the inter-edge pulse signal 6, the falling edge regardless of the state immediately before all outputs of the remainder result signal M [0: n]. 0 is output to the remainder result signal M [0: n] at the time obtained by adding the Ts time to the detection time. For example, 0 is output to all outputs of the remainder result signal M [0: n] at time T14 obtained by adding Ts time to time T3 when the falling edge of the inter-edge pulse signal 6 occurs.

Adding the Ts time to the time T2 when the rising edge of the inter-edge pulse signal 6 occurs is equivalent to subtracting the Ts time from the pulse width Teg. On the other hand, adding the Ts time to the time T3 when the falling edge occurs is equivalent to adding the Ts time to the pulse width Teg. Accordingly, the pulse width remainder dividing circuit 2 subtracts the Ts time from the pulse width Teg of the inter-edge pulse signal 6 and outputs a signal having a width obtained by adding the Ts time to the subtracted data as the remainder result signal M [0]. . Then, the pulse width remainder dividing circuit 2 subtracts (Ts × 2) time from the pulse width Teg of the inter-edge pulse signal 6 and adds a signal having a width obtained by adding the Ts time to the subtracted data, the remainder result signal M [1 ] Is output. Further, for the remainder result signal M [N] after the remainder result signal M [2], Ts × (N + 1) time is subtracted from the pulse width Teg of the inter-edge pulse signal 6, and the Ts time is added to the subtracted data. The signal having the width is output as the remainder result signal M [N]. For this reason, the width of the signal output to the remainder result signal M [0: n] can be expressed by the following equations X0 to Xn.
Residue result signal M [0] pulse width = Teg− (Ts × 1) + Ts
= Teg− (Ts × 0) Formula X0
Residue result signal M [1] pulse width = Teg− (Ts × 2) + Ts
= Teg- (Ts × 1) Formula X1
Residue result signal M [2] pulse width = Teg− (Ts × 3) + Ts
= Teg− (Ts × 2) Formula X2
・
・
・
Residue result signal M [n] pulse width = Teg− (Ts × n) + Ts
= Teg− (Ts × n) Formula Xn

  As shown by the above-described equations X0 to Xn, the pulse width remainder dividing circuit 2 subtracts the pulse width of the inter-edge pulse signal 6 by the product of the Ts time and the non-negative integer n, and a positive remainder by subtraction. Are output as the remainder result signal M [0: n] for each non-negative integer n.

  In the example shown in FIG. 6A, the pulse width Teg of the inter-edge pulse signal 6 corresponds to 10 times the Ts time. For this reason, the pulse width is zero in the remainder result signal M [10], which is an output corresponding to Teg− (Ts × 10) having a non-negative integer “10” as a multiplier.

  Next, the operation of the pulse width remainder dividing circuit 2 when the signal under measurement 5 has jitter will be described with reference to FIG. Note that time T2 and time T3 indicate the same time as time T2 and time T3 shown in FIGS. 5 and 6A. Further, the pulse width Teg of the inter-edge pulse signal 6 indicated by the time T2 and the time T3 can be expressed by the above-described Expression 3.

  First, the case where the rising edge of the inter-edge pulse signal 6 occurs at time T4 and the falling edge occurs at time T8 will be described. Time T4 and time T8 indicate the same time as time T4 and time T8 shown in FIG. Further, the pulse width indicated by the time T4 and the time T8 can be expressed by the above-described Expression 7, which is an expression including the pulse width Teg and the time Tjt1 caused by the jitter.

  As shown in the figure, when the rising edge of the supplied inter-edge pulse signal 6 occurs at time T4, the pulse width remainder dividing circuit 2 generates a remainder result signal at time T4 plus Ts time (T4 + Ts time). 1 is output to M [0]. Further, when the remainder result signal M [0] changes to 1 at time (T4 + Ts time), the pulse width remainder dividing circuit 2 adds time Ts to time (T4 + Ts time) (T4 + (Ts × 2) time). 1 is output to the remainder result signal M [1].

  As described above, the pulse width remainder dividing circuit 2 starts from the time when the rising edge of the inter-edge pulse signal 6 occurs, and at the time obtained by adding the Ts time to the time when the rising edge occurs, the remainder result signal M [0 ] Is output to [1]. Then, the pulse width remainder dividing circuit 2 sequentially outputs 1 to the remainder result signal M [N + 1] at the time when the Ts time is added to the time when M [N] changes to 1.

  On the other hand, when the pulse width remainder dividing circuit 2 detects the falling edge of the inter-edge pulse signal 6, the falling edge regardless of the state immediately before all outputs of the remainder result signal M [0: n]. 0 is output to the remainder result signal M [0: n] at the time obtained by adding the Ts time to the detection time. For this reason, 0 is output to all outputs of the remainder result signal M [0: n] at a time obtained by adding Ts time to time T8 when the falling edge of the inter-edge pulse signal 6 occurs.

Adding the Ts time to the time T4 when the rising edge of the inter-edge pulse signal 6 occurs is equivalent to subtracting the Ts time from the pulse width Teg + Tjt1. On the other hand, adding the Ts time to the time T8 when the falling edge occurs is equivalent to adding the Ts time to the pulse width Teg + Tjt1. Therefore, the pulse width remainder dividing circuit 2 subtracts the Ts time from the pulse width Teg + Tjt1 of the inter-edge pulse signal 6, and outputs a signal having a width obtained by adding the Ts time to the subtracted data as the remainder result signal M [0]. . Then, (Ts × 2) time is subtracted from the pulse width Teg + Tjt1 of the inter-edge pulse signal 6, and a signal having a width obtained by adding the Ts time to the subtracted data is output as the remainder result signal M [1]. Further, for the remainder result signal M [N] after the remainder result signal M [2], Ts × (N + 1) time is subtracted from the pulse width Teg + Tjt1 of the inter-edge pulse signal 6, and the Ts time is added to the subtracted data. A signal with the specified width is output. For this reason, the width of the signal output to the remainder result signal M [0: n] can be expressed by the following equations Y0 to Yn.
Residue result signal M [0] pulse width = Teg + Tjt1− (Ts × 1) + Ts
= Teg + Tjt1- (Ts × 0)... Y0
Residue result signal M [1] pulse width = Teg + Tjt1− (Ts × 2) + Ts
= Teg + Tjt1- (Ts × 1)... Y1
Residue result signal M [2] pulse width = Teg + Tjt1− (Ts × 3) + Ts
= Teg + Tjt1- (Ts × 2) Expression Y2
・
・
・
Residue result signal M [n] pulse width = Teg + Tjt1− (Ts × n) + Ts
= Teg + Tjt1- (Ts × n)... Yn

  In the example shown in FIG. 6B, the pulse width of the inter-edge pulse signal 6 from time T4 to time T8 is the pulse width Teg + Tjt1 time. Therefore, the pulse width becomes 0 in the remainder result signal M [10+ (Tjt1 / Ts)], which is larger by (Tjt1 / Ts) than the remainder result signal M [10] shown in FIG.

  Next, the case where the rising edge of the inter-edge pulse signal 6 occurs at time T9 and the falling edge occurs at time T10 will be described. Time T9 and time T10 indicate the same time as time T9 and time T10 illustrated in FIG. Further, the pulse width indicated by the time T9 and the time T10 can be expressed by the above-described expression 10, which is an expression including the pulse width Teg and the Tjt2 time generated by the jitter.

  As shown in the figure, when the rising edge of the supplied inter-edge pulse signal 6 occurs at time T9, the pulse width remainder dividing circuit 2 generates a remainder result signal M at a time (T9 + Ts time) obtained by adding Ts time to time T9. 1 is output to [0]. Further, when the remainder result signal M [0] changes to 1 at time (T9 + Ts time), the pulse width remainder dividing circuit 2 adds time Ts to time (T9 + Ts time) (T9 + (Ts × 2) time) 1 is output to the remainder result signal M [1]. The pulse width remainder dividing circuit 2 also performs the remainder result signal M [N + 1] after the remainder result signal M [2] and after the time Ts is added to the time when the remainder result signal M [N] changes to 1. 1 is output sequentially.

  On the other hand, the pulse width remainder dividing circuit 2 outputs 0 to all outputs of the remainder result signal M [0: n] at the time obtained by adding the Ts time to the time T10 when the falling edge of the inter-edge pulse signal 6 occurs. To do.

Adding the Ts time to the time T9 when the rising edge of the inter-edge pulse signal 6 occurs is equivalent to subtracting the Ts time from the pulse width Teg-Tjt2. On the other hand, adding the Ts time to the time T10 when the falling edge occurs is equivalent to adding the Ts time to the pulse width Teg-Tjt2. Therefore, the pulse width remainder dividing circuit 2 subtracts the Ts time from the pulse width Teg−Tjt2 of the inter-edge pulse signal 6, and uses a signal having a width obtained by adding the Ts time to the subtracted data as the remainder result signal M [0]. Output. Then, (Ts × 2) time is subtracted from the pulse width Teg−Tjt2 of the inter-edge pulse signal 6, and a signal having a width obtained by adding the Ts time to the subtracted data is output as the remainder result signal M [1]. Further, also with respect to the remainder result signal M [N] after the remainder result signal M [2], Ts × (N + 1) time is subtracted from the pulse width Teg−Tjt2 of the inter-edge pulse signal 6, and Ts time is added to the subtracted data. A signal with a width obtained by adding is output. For this reason, the width of the signal output to the remainder result signal M [0: n] can be expressed by the following equations Z0 to Zn.
Residue result signal M [0] pulse width = Teg−Tjt2− (Ts × 1) + Ts
= Teg−Tjt2− (Ts × 0)... Z0
Residue result signal M [1] pulse width = Teg−Tjt2− (Ts × 2) + Ts
= Teg−Tjt2− (Ts × 1) Expression Z1
Residue result signal M [2] pulse width = Teg−Tjt2− (Ts × 3) + Ts
= Teg−Tjt2− (Ts × 2) Expression Z2
・
・
・
Residue result signal M [n] pulse width = Teg−Tjt 2 − (Ts × n) + Ts
= Teg-Tjt2- (Ts × n) Formula Zn

  In the example shown in FIG. 6B, the pulse width of the inter-edge pulse signal 6 from time T9 to time T10 is the pulse width Teg−Tjt2 hours. Therefore, the pulse width becomes 0 in the remainder result signal M [10− (Tjt2 / Ts)], which is smaller by (Tjt2 / Ts) than the remainder result signal M [10] shown in FIG. .

  Next, the operation of the one hot state circuit 3 will be described with reference to FIGS. FIG. 7 is a state transition diagram of the cycle jitter value signal D [N] generated by the one-hot state circuit 3. FIG. 8 is a timing chart showing the operation of the one-hot state circuit 3.

  The state transition diagram of the one-hot state circuit 3 shown in FIG. 7 includes two states (STATE 1 and STATE 2). In the state transition diagram of the one-hot state circuit 3, transition from each state when the remainder result signal M is given is defined.

  STATE 1 indicates a state in which the cycle jitter value signal D [N] generated by the one-hot state circuit 3 is zero. STATE 2 indicates a state in which the cycle jitter value signal D [N] is 1.

  When the residue result signal M [N] input to the one hot state circuit 3 is 0 and the residue result signal M [N + 1] is 0, or the residue result signal M [N] is 1, and The transition when the remainder result signal M [N + 1] is 1 is LOOP1. The transition when the remainder result signal M [N] is 1 and the remainder result signal M [N + 1] is 0 is LOOP2. When the residue result signal M [N] is 0 and the residue result signal M [N + 1] is 0, or the residue result signal M [N] is 1 and the residue result signal M [N + 1] is also 1 Let TRANS1 be the transition when. A transition when the remainder result signal M [N] is 1 and the remainder result signal M [N + 1] is 0 is referred to as TRANS2.

  Of the remainder result signal M [0: n] input to the one-hot state circuit 3, the remainder result signal M [N] is 0 and the remainder result signal M [N + 1] is 0. Regardless of the state of the cycle jitter value signal D [N] to be performed, the condition of LOOP1 or TRANS1 is satisfied, and the state of STATE1 in which the cycle jitter value signal D [N] is 0 is obtained.

  Further, when the one-hot state circuit 3 is in the state 1 and the remainder result signal M [N] is 1 and the remainder result signal M [N + 1] is 1, the condition of LOOP1 is satisfied. . Therefore, the one hot state circuit 3 maintains the state of STATE1. When the remainder result signal M [N] is 1 and the remainder result signal M [N + 1] is 0, the condition of TRANS2 is satisfied. Therefore, the one hot state circuit 3 transits to the state 2 of STATE 2 in which the cycle jitter value signal D [N] is 1.

  When the one-hot state circuit 3 is in the state 2 and the remainder result signal M [N] is 1 and the remainder result signal M [N + 1] is 0, the condition of LOOP1 is satisfied. . Therefore, the one hot state circuit 3 maintains the state of STATE2. When the remainder result signal M [N] is 1 and the remainder result signal M [N + 1] is 1, the condition of TRANS1 is satisfied. Therefore, the one hot state circuit 3 makes a transition to the state 1 in which the cycle jitter value signal D [N] is 0.

  As described above, the cycle jitter value signal D [N] generated by the one hot state circuit 3 depends on the combination of the input remainder result signal M [N] and the remainder result signal M [N + 1]. Hold state or transition.

  Next, details of the operation of the one-hot state circuit 3 will be described with reference to FIG. FIG. 8 shows an inter-edge pulse signal 6 generated by the inter-edge pulse generation circuit 1 and a cycle jitter value signal D [0: n−1] generated by the one-hot state circuit 3. The time T2, time T3, time T4, time T8, time T9, time T10, Td time, pulse width Teg, pulse width Teg + Tjt1, and pulse width Teg−Tjt2 shown in FIG. This is the same as that shown in FIG.

  As shown in the figure, the one-hot state circuit 3 generates a rising edge of the residue result signal M [0] at time (T2 + Ts time) from the state where the supplied residue result signal M [0: n] is all zero. Then, 1 is output to the cycle jitter value signal D [0]. Further, when the rising edge of the remainder result signal M [1] occurs at time (T2 + (Ts × 2) time), the one-hot state circuit 3 outputs 1 to the cycle jitter value signal D [1], and 0 is output to the jitter signal D [0].

  Also in the cycle jitter signal D [N] after the cycle jitter signal D [2], the one hot state circuit 3 has a rising edge of the residue result signal M [N] when the residue result signal M [N + 1] is 0. When it occurs, the condition of TRANS2 shown in FIG. 7 is satisfied. For this reason, the one hot state circuit 3 transits to the state STATE 2 and outputs 1 to the cycle jitter value signal D [N]. The one-hot state circuit 3 holds the state of STATE2 according to the condition of LOOP2 until the states of the remainder result signal M [N + 1] and the remainder result signal M [N] change.

  When the rising edge of the remainder result signal M [N + 1] is generated Ts after the rising edge of the remainder result signal M [N] occurs, the cycle jitter value signal D [N] is shown in FIG. This is a condition for TRANS1. For this reason, the one hot state circuit 3 transitions to the state 1 of STATE 1 and becomes 0, and at the same time, the cycle jitter value signal D [N + 1] becomes a condition of TRANS2. Therefore, the one hot state circuit 3 changes to the state 2 and becomes 1. Further, since all the outputs of the remainder result signal M [0: n] become 0 at time (T3 + Ts time), the one hot state circuit 3 becomes the condition of LOOP1 or TRANS1 shown in FIG. 7, and the cycle jitter value signal D [ All outputs of 0: n−1] are 0.

  As described above, in the one hot state circuit 3, only the cycle jitter value signal D [N] that matches the condition of TRANS2 or LOOP2 shown in FIG. 7 is in the state STATE2. For this reason, 1 is output to only one of the cycle jitter value signals D [0: n−1] generated according to the state of the input remainder result signal M [0: n].

  The remainder result signal M [0: n] is a positive remainder obtained by subtracting the pulse width of the inter-edge pulse signal 6 by the product of the Ts time and the non-negative integer. For this reason, the cycle jitter value signal D [N−1] having the remainder result signal M [N] and the remainder result signal M [N−1] in which the remainder is not generated as a condition for holding or transitioning is represented by an edge. A quotient obtained by dividing the inter-pulse signal 6 by the Ts time is shown, and a non-negative integer indicating how many times the pulse width of the inter-edge pulse signal 6 corresponds to the Ts time can be calculated by N + 1.

  In the cycle jitter measurement, one period of the signal under measurement 5 is measured from the rising edge to the next rising edge. For this reason, when the period from the rising edge to the falling edge of the inter-edge pulse signal 6 is one cycle, the pulse width Teg of the inter-edge pulse signal 6 shown in FIG. 8 is changed from the cycle jitter value signal D [9] to Ts. It can be seen that this corresponds to 10 times the time. Further, it can be seen that the pulse width Teg + Tjt1 time corresponds to 14 times the Ts time from the cycle jitter value signal D [13]. Further, it can be seen that the pulse width Teg−Tjt2 time corresponds to eight times the Ts time from the cycle jitter value signal D [7]. Furthermore, by reading the cycle jitter value signal D [0: n−1] for each period, a non-negative integer that is a period deviation for each period of the signal under measurement 5 can be obtained.

  Next, the operation of the cumulative holding circuit 4 will be described with reference to FIG. FIG. 7 is a timing chart showing the operation of the cumulative holding circuit 4. FIG. 9 shows the inter-edge pulse signal 6 generated by the inter-edge pulse generation circuit 1 and the cumulative jitter value signal Q [0: n−1] generated by the cumulative holding circuit 4. The time T2, time T3, time T4, time T8, time T9, time T10, Td time, pulse width Teg, pulse width Teg + Tjt1, and pulse width Teg−Tjt2 shown in FIG. 6B and FIG. 8 are the same as those shown in FIG. Hereinafter, the operation of the cumulative holding circuit 4 will be described with reference to FIGS.

  First, the accumulation holding circuit 4 latches the cycle jitter value signal D [9] in which 1 is output between the time T3 and the time Ts when the falling edge of the inter-edge pulse signal 6 occurs, and the accumulated jitter value signal 1 is output to Q [9]. The cumulative holding circuit 4 latches the cycle jitter value signal D [13], in which 1 is output during the time T8 to Ts time when the falling edge of the next inter-edge pulse signal 6 occurs, and the cumulative jitter value signal 1 is output to Q [13]. The cumulative holding circuit 4 latches the cycle jitter value signal D [7], in which 1 is output between the time T10 and the time Ts when the falling edge of the next inter-edge pulse signal 6 occurs, and the cumulative jitter value signal 1 is output to Q [7].

  As described above, the accumulation holding circuit 4 has the Ts time from the time when the falling edge of the inter-edge pulse signal 6 occurs in the cycle jitter value signal D [0: n−1] supplied by the one-hot state circuit 3. Only the cycle jitter value signal D [N] for which 1 is output during the period is latched. As a result, the accumulation holding circuit 4 accumulates and holds the output of the cycle jitter value signal D [0: n−1] for each period of the signal under measurement 5, and sets 1 to the accumulated jitter value signal Q [N]. Output. Further, the cumulative holding circuit 4 can acquire the maximum and minimum values of the period deviation of the signal under measurement 5 by reading the cumulative holding result Q [0: n−1].

  The Td time of the inter-edge pulse signal 6 generated by the inter-edge pulse generation circuit 1 is a non-measurement time and represents one cycle of the signal under measurement 5. For this reason, the Td time can be used as a read timing of the cycle jitter value signal D [0: n-1] or the cumulative holding result Q [0: n-1], or the data update timing is detected. It can also be used as a means.

  As described above, the jitter measurement circuit 10 according to the first embodiment includes the inter-edge pulse generation unit 1 that generates the inter-edge pulse signal 6 from the edge of the input signal under measurement 5, and the inter-edge pulse signal 6. Is divided by a value obtained by multiplying a predetermined time unit by an integer, and a pulse width remainder dividing unit 2 that outputs a remainder result of the division operation as a remainder result signal M, and an integer when the value of the remainder result signal M is minimized And a one-hot state unit 4 that outputs the value of as a cycle jitter value signal D of the inter-edge pulse signal 6. As a result, a cycle jitter value signal indicating how many times the pulse signal between edges corresponds to a predetermined time unit can be calculated. Therefore, since the jitter amount can be digitally output without measuring the period of the periodic signal, a counter for measuring the periodic signal and a clock for operating the counter become unnecessary.

  More specifically, the inter-edge pulse generation circuit 1 is an arbitrary fixed time that is generated by the inter-edge pulse generation circuit 1 of the input signal under measurement 5 and is shorter than the rising edge interval of the signal under measurement 5. An inter-edge pulse signal 6 from the rising edge delayed by time (showing the first time Td described above) to the next rising edge is generated. The pulse width remainder dividing circuit 2 generates the inter-edge pulse signal 6 for an arbitrary fixed time (the second time described above) which is the time generated by the pulse width remainder dividing circuit 2 and shorter than the rising edge interval of the signal under measurement 5. Ts.) And the product of the non-negative integer n. Then, the pulse width remainder dividing circuit 2 divides and outputs the subtracted positive remainder as a remainder result signal M [0: n] for each non-negative integer n. The one hot state circuit 3 uses the remainder result signal M [0: n] indicating the smallest positive remainder in the remainder result signal M [0: n], and the inter-edge pulse signal 6 becomes the second time Ts. A non-negative integer n which is a quotient of division indicating how many times it corresponds is calculated. The accumulation holding circuit 4 accumulates and holds the non-negative integer n calculated by the one hot state circuit 3. The non-negative integer n calculated by the one hot state circuit 3 is output as the cycle jitter value signal D [0: n−1] to obtain the cycle jitter amount. Further, the result of the cumulative holding by the cumulative holding circuit 4 is output as the cumulative jitter value signal Q [0: n−1].

  Hereinafter, effects of the jitter measurement circuit 10 according to the first embodiment will be described. First, as a first effect, the jitter amount can be digitally output without measuring the period of the periodic signal. This eliminates the need for a counter for measuring a periodic signal and a clock for operating the counter. In the conventional technique, a periodic signal is generated from the phase difference between the signal under measurement and the measurement signal, and the period of the generated periodic signal is measured. In the jitter measurement circuit 10, an inter-edge pulse signal 6 is generated from an edge of the input signal 5 to be measured, the inter-edge pulse signal 6 is divided by a value obtained by multiplying a predetermined time unit by an integer, and the division operation is performed. By outputting the remainder result as the residue result signal M and outputting the integer value when the value of the residue result signal M is the minimum as the cycle jitter value signal D of the edge-to-edge pulse signal 6, the edge-to-edge pulse signal is obtained. This is because the magnitude of the jitter amount can be acquired by calculating a cycle jitter value signal indicating how many times the predetermined time unit corresponds.

  As a second effect, the jitter measurement circuit 10 according to the first embodiment calculates the cycle jitter amount for each period of the signal under measurement, the maximum amount of cycle jitter at any time, and the accumulated jitter. can do. This is a configuration in which only the accumulated jitter amount is detected by accumulating the phase difference in the prior art, whereas the jitter measurement circuit 10 according to the first embodiment indicates one cycle of the signal under measurement. , Generates a pulse signal between edges from the rising edge to the next rising edge, calculates a cycle jitter amount by calculating a quotient obtained by dividing the pulse between edges by an arbitrary time, and accumulates the cycle jitter amount every period This is because the maximum value of the cycle jitter amount and the cumulative jitter at an arbitrary time can be obtained.

  As a third effect, the jitter measurement circuit 10 according to the first embodiment can calculate the jitter amount based only on the signal under measurement. This is a configuration in which the phase difference between the signal under measurement and the measurement signal is converted into a pulse width and the period is measured in the prior art, whereas in the jitter measurement circuit 10 according to the first embodiment, the signal under measurement is This is because the cycle jitter amount is calculated by generating an inter-edge pulse signal from the rising edge to the next rising edge, and calculating a quotient obtained by dividing the inter-edge pulse by an arbitrary time. In addition, when using a measurement signal for jitter measurement, the signal under measurement and the measurement signal must have the same frequency, so that only the signal under measurement having the same frequency as the measurement signal can be used for jitter measurement. It is necessary to prepare measurement signals for each limit or frequency of the signal under measurement to be measured. On the other hand, since the jitter measurement circuit 10 according to the first embodiment does not require a measurement signal for jitter measurement, it is possible to measure jitter without limitation on the frequency of the signal under measurement. In addition, since a phase comparator for detecting the phase difference between the measurement signal and the signal under measurement is not required, it is not affected by the jitter contained in the measurement signal. As a result, more accurate jitter measurement is performed. be able to.

  As a fourth effect, the jitter measurement circuit 10 according to the first embodiment can calculate the jitter amount regardless of the duty ratio of the signal under measurement. This is because, in the jitter measurement circuit 10 according to the first embodiment, the rising edge and the next rising edge delayed by the first time of the signal under measurement, the delayed falling edge and the next falling edge, or the like. This is because the jitter amount is obtained using only edges in the same direction, and the jitter amount can be calculated regardless of the duty ratio.

  As a fifth effect, since the jitter measurement circuit 10 according to the first embodiment does not require a decode circuit, a charge pump circuit, or the like, the circuit scale can be reduced. In contrast to the conventional technique, the phase difference between the signal under measurement and the measurement signal is converted into a pulse, and the charge pump circuit is driven by the converted pulse to accumulate charges and generate a periodic signal. Thus, the jitter measurement circuit 10 according to the first embodiment generates an inter-edge pulse signal using the rising edge obtained by delaying the signal under measurement by the first time and the next rising edge, and generates an inter-edge pulse signal. Since the pulse signal and the quotient of the second time division are output as a cycle jitter value signal in n bits, the MSB side can indicate the phase lag of the signal under measurement due to jitter, and the LSB side can also be subject to jitter due to jitter. This is because the phase advance of the measurement signal can be indicated.

Embodiment 2. FIG.
FIG. 10 is a block diagram showing a configuration of the jitter measuring circuit 20 with a calibration function according to the second embodiment. As shown in the figure, a jitter measuring circuit 20 with a calibration function controls a calibration function to make the first time and the second time variable, and as a variable inter-edge pulse generation unit. A variable inter-edge pulse generation circuit 1A, a variable pulse width remainder division circuit 2A as a variable pulse width remainder division section, a one hot state circuit 3 as a one hot state section, and an accumulation holding circuit 4 as an accumulation holding circuit section It has. The calibration unit 15 includes a CAL switching circuit 14 as a CAL switching unit that controls the validity / invalidity of the calibration function, a current value control signal generation circuit 7 as a current value control signal generation unit, and a variable current unit. And a variable current source 8. Furthermore, the variable current source 8 includes a first variable current source 81 that converts the edge current control signal 11 into VBPD and VBND, and a second variable current source 82 that converts the pulse current control signal 12 into VBPW and VBNW. ing. The calibration unit 15 performs a calibration operation for calibrating the first time and the second time according to the fluctuation of the remainder result signal using the inter-edge pulse signal as a timing signal.

  The CAL signal 13 is a signal indicating an operation mode, which is a normal operation mode or a calibration operation. The CAL switching circuit 14 selects the signal under measurement 5 when the normal operation mode is indicated by the input CAL signal 13 among the signal under measurement 5 supplied and the REF signal 9 as the reference signal. When the calibration operation mode is indicated, the REF signal 9 is selected, converted into a differential signal, and supplied to the variable inter-edge pulse generation circuit 1A as the measured positive signal 5A and the measured negative signal 5B.

  The variable edge-to-edge pulse generation circuit 1A delays the rising edge of the supplied positive signal to be measured 5A or the falling edge of the negative signal to be measured 5B by a Td time set by the input VBPD and VBND. The difference between the rising edge of the measured positive signal 5A or the falling edge of the measured negative signal 5B and the next rising edge of the measured positive signal 5A or the falling edge of the measured negative signal 5B It is converted into a motion signal and supplied to the variable pulse width remainder dividing circuit 2A as an inter-edge pulse positive signal 6A and an inter-edge pulse negative signal 6B.

  The Td time is a time obtained by converting VBPD and VBND, and VBPD and VBND are voltages. By controlling the current of the MOS transistor with the voltage, the signal slew rate is changed. The time transmitted to the stage is adjusted.

  The variable pulse width remainder dividing circuit 2A divides the supplied inter-edge pulse positive signal 6A and inter-edge pulse negative signal 6B by a value obtained by multiplying the Ts time set by the input VBPW and VBNW by an integer, The remainder result obtained by the division operation is output as a remainder result signal. More specifically, when the time indicated by VBPW and VBNW is a multiplicand, and a non-negative integer that is an integer is a multiplier, the variable pulse width remainder dividing circuit 2A provides the supplied inter-edge pulse positive signal 6A and inter-edge pulse. The negative signal 6B is subtracted by the product of the time indicated by VBPW and VBNW and a non-negative integer. Then, the variable pulse width remainder dividing circuit 2A divides the subtracted positive remainder into non-negative integers, and sets the divided signal group as a remainder result signal M [0: n] (n is a natural number of 1 or more). The hot state circuit 3 is supplied.

  The Ts time is a time obtained by converting VBPW and VBNW, and VBPW and VBNW are voltages. By controlling the current of the MOS transistor with the voltage, the signal slew rate is changed. The time transmitted to the stage is adjusted.

  The one-hot state circuit 3 and the cumulative holding circuit 4 are the same as those in the first embodiment, and thus detailed description thereof is omitted.

  When the calibration operation mode is indicated by the input CAL signal 13, the current value control signal generation circuit 7 and the edge current control signal 11 based on the supplied remainder result signal M [0: n] The pulse current control signal 12 is changed at the timing of the falling edge of the supplied inter-edge pulse positive signal 6A, and when the normal operation mode is indicated, the edge current control signal 11 and the pulse current control signal 12 are changed immediately before. The value is held and supplied to the first variable current source 81 and the second variable current source 82.

  The first variable current source 81 generates VBPD and VBND from the variable current source controlled by the input edge current control signal 11, and supplies the generated VBPD and VBND to the variable edge pulse generation circuit 1A. The second variable current source 82 generates VBPW and VBNW from the variable current source controlled by the input pulse current control signal 12, and supplies VBPW and VBNW to the variable pulse width remainder dividing circuit 2A.

  More specifically, first, the jitter measuring circuit 20 with the calibration function is set to the calibration operation mode by the CAL signal 13. At that time, the edge current control signal 11 is set to an initial value that minimizes the Td time that is the first time, and the pulse current control signal 12 is set to an initial value that maximizes the Ts time that is the second time. Is set.

  Subsequently, the current value control signal generation circuit 7 prevents the pulse width of the remainder result signal M [0] from becoming 0 among the remainder result signals M [0: n] output at every rising edge of the REF signal 9. Further, the edge current control signal 11 is changed to increase the Td time. Then, the current value control signal generation circuit 7 changes the pulse current control signal 12 so that the pulse width of the remainder result signal M [n] of the remainder result signal M [0: n] does not become 1, and Ts Reduce time.

  For example, when the calibration operation mode is set by the CAL signal 13, the CAL switching circuit 14 selects the REF signal 9, so that the Td time is set in accordance with the shortest cycle of the REF signal 9, and subsequently, Ts The time is set in accordance with the longest period of the REF signal 9. Next, when the normal operation mode is set by the CAL signal 13, the CAL switching circuit 14 selects the signal under measurement 5, so that the jitter measurement circuit 20 with the calibration function is the signal under measurement based on the REF signal 9. Operates to measure 5 jitter.

  By operating as described above, the jitter measuring circuit 20 with the calibration function obtains the jitter amount based on the optimum Td time and Ts time.

As an effect of the jitter measurement circuit 20 with the calibration function, since it has a function capable of changing the Td time as the first time, jitter measurement independent of the period of the signal under measurement 5 is possible. The relationship between the Td time, which is the first time, and the pulse width Teg time of the inter-edge pulse signal 6 when the cycle of the signal under measurement 5 is Tcyc time is as shown in Equation 3 above. In other words, when there are a plurality of frequencies of the signal under measurement 5 to be measured, the period difference can be canceled by changing the Td time according to each period, so the pulse width Teg time is kept almost constant. be able to. If the period change is α, the pulse width Teg can be made constant as shown in the following expression 3A by changing the Td time by α time.
Teg = (Tcyc + α) − (Td + α) Equation 3A

  Furthermore, since the jitter measuring circuit 20 with the calibration function has a function of changing the Ts time that is the second time, it is possible to arbitrarily set the sampling period when measuring the cycle jitter amount of the signal under measurement 5. Is possible. This is because the cycle jitter value is calculated as a cycle jitter value, which is a non-negative integer N indicating how many times the pulse width of the inter-edge pulse signal 6 corresponds to the Ts time.

  In the calibration operation mode, since the Td time and the Ts time are set including the manufacturing variation of the jitter measuring circuit 20 with the calibration function, the same conditions are always used when the input REF signal 9 has the same quality. Jitter measurement becomes possible.

  Furthermore, when the signal under measurement 5 includes jitter and the period of the signal under measurement 5 is temporally fluctuated, a signal including the shortest period and the longest period is calibrated as the REF signal 9. If the operation is input, the jitter measurement range of the jitter measurement circuit 20 with the calibration function can be preset.

  FIGS. 11A and 11B are circuit diagrams showing detailed configurations of the first variable current source 81 and the second variable current source 82 according to the second embodiment. As shown in FIG. 11A, the first variable current source 81 includes a variable current source 801, a PMOS transistor MP801, and NMOS transistors MN801 and 802.

  The variable current source 801 controls the current flowing through the MN 801 by the supplied edge current control signal 11 and outputs VBND as the edge delay NMOS transistor bias control voltage. Further, MN 801 and MN 802 have a current mirror structure, and a similar current flows through MP 801, so VBPD is output as an edge delay PMOS transistor bias control voltage.

  On the other hand, as shown in FIG. 11B, the second variable current source 82 includes a variable current source 802, a PMOS transistor MP802, and NMOS transistors MN803 and 804.

  The variable current source 802 controls the current flowing through the MN 803 by the supplied pulse current control signal 12 and outputs VBNW as a pulse width control NMOS transistor bias control voltage. Further, since MN803 and MN804 have a current mirror structure, and a similar current flows through MP802, VBPD is output as a pulse width control PMOS transistor bias control voltage.

  FIG. 12 is a circuit diagram showing the detailed configuration of the variable inter-edge pulse generation circuit 1A according to the second embodiment. As shown in the figure, the variable edge pulse generation circuit 1A includes PMOS transistors MP103 to MP106 and MPD, NMOS transistors MN101 to MN105, MN108 to MN112, MN113 to MN116 and MND, and a resistance element. Is done.

  The measured positive signal 5A is connected to the gate terminals of MP103, MN113, and MN102, and the measured negative signal 5B is connected to the gate terminals of MP106, MN116, and MN101. In the MPD to which VBPD is supplied to the gate terminal, the source terminal is connected to the power supply, and the drain terminal is connected to the source terminals of MP103 to MP106. The drain terminal of MN101 is connected to the power supply through a resistor and also connected to the gate terminal of MN110. The drain terminals of MN102 and MN104 are short-circuited and connected to the power supply via a resistor and also connected to the gate terminal of MN112. The source terminals of MN101 and MN102 are short-circuited and connected to the drain terminal of MN103, and the source terminals of MN103 and MN105 are short-circuited and grounded via a resistor. The gate terminal of MN104 is connected to a power supply through a resistor, and the source terminal is connected to the drain terminal of MN105. In the MND to which VBND is supplied to the gate terminal, the source terminal is grounded, and the drain terminals are connected to the source terminals of the MN113 to MN116. The drain terminals of MP103, MP104, MN113, and MN114 are short-circuited and connected to the gate terminals of MP105 and MN115 and also to the gate terminal of MN108. The drain terminals of MP105, MP106, MN115 and MN116 are short-circuited and connected to the gate terminals of MP104 and MN114 and also to the gate terminal of MN109. The drain terminal of the MN 108 becomes the inter-edge pulse positive signal 6A, but is connected to the power source through a resistor and also to the gate terminal of the MN 103. The drain terminals of MN109 and MN111 are short-circuited and connected to the power supply via a resistor and also connected to the gate terminal of MN105. The source terminals of MN108 and MN109 are short-circuited and connected to the drain terminal of MN110, and the source terminals of MN110 and MN112 are short-circuited and grounded via a resistor. The gate terminal of MN111 is connected to a power supply through a resistor, and the source terminal is connected to the drain terminal of MN112.

  In the variable inter-edge pulse generation circuit 1A and the inter-edge pulse generation circuit 1, the NMOS transistors with the same number operate in the same manner. In the inter-edge pulse generation circuit 1, the rising edge delay portion of the signal under measurement 5 constituted by the MP101, MP102, MN106, MN107 and the Td time delay element 120 is changed to MP103 to MP106 in the variable inter-edge pulse generation circuit 1A. , MN113 to MN116, MPD and MND.

  When the rising edge of the measured positive signal 5A is generated, the MP 103 is turned off and the MN 113 is turned on. At the same time, since the falling edge of the negative signal 5B to be measured is generated, the MP 106 is turned on and the MN 116 is turned off. Next, when the MN 113 is turned on, the gate potentials of the MP 105 and the MN 115 become 0. However, since the source terminals of the MN 113 to MN 116 are grounded via the MND having the VBND connected to the gate terminal, the MP 105 The time when the gate potential of MN115 becomes 0 is determined by the current limited by VBND. Similarly, when the MP 106 is turned on, the gate potentials of the MP 104 and the MN 114 become 1, but the source terminals of the MP 103 to MP 106 are connected to the power supply via the MPD in which the VBPD is connected to the gate terminal. The time when the gate potentials of MP104 and MN114 become 1 is determined by the current limited by VBPD. As described above, when the rising edge of the measured positive signal 5A is generated and at the same time the falling edge of the measured negative signal 5B is generated, the MN113, MN113, The operation is stabilized when MN114, MP105, and MP106 are turned on, but the delay time of the potential supplied to the gate terminals of MN108 and MN109 is determined by the amount of current limited by VBPD and VBND. Become.

  Next, when the falling edge of the measured positive signal 5A occurs, the MP 103 is turned on and the MN 113 is turned off. At the same time, since the rising edge of the negative signal 5B to be measured is generated, the MP 106 is turned off and the MN 116 is turned on. Next, when the MP 103 is turned on, the gate potentials of the MP 105 and the MN 115 become 1, but the source terminals of the MP 103 to the MP 106 are connected to the power source through the MPD in which the VBPD is connected to the gate terminal. The time when the gate potentials of MP105 and MN115 become 1 is determined by the current limited by VBPD. Similarly, the gate potential of MP104 and MN114 becomes 0 when MN116 is turned on, but the source terminals of MN113 to MN116 are grounded via the MND whose VBND is connected to the gate terminal. The time when the gate potential of MN114 becomes 0 is determined by the current limited by VBND. As described above, when the falling edge of the measured positive signal 5A is generated and at the same time the rising edge of the measured negative signal 5B is generated, the MP103 among the MP103 to MP106 and the MN113 to MN116 configured in a scissors shape. , MP104, MN115, and MN116 are in the on state, but the operation is stabilized, but the delay time of the potential supplied to the gate terminals of MN108 and MN109 is determined by the amount of current limited by VBPD and VBND It will be.

  FIG. 13 is a diagram showing a detailed configuration of the variable pulse width remainder dividing circuit 2A according to the second embodiment. As shown in the figure, the variable pulse width remainder dividing circuit 2A includes PMOS transistors MPW0 and MPW1 having VBPW as gate inputs, a cell VM0 including NMOS transistors MN201 to MN205, and a PMOS transistor MPW2 having VBPW as a gate input. MPW3, a cell VM1 composed of NMOS transistors MN206 to MN210, PMOS transistors MPW4 and MPW5 having VBPW as a gate input, a cell VM2 composed of NMOS transistors MN211 to M215, and a plurality of cells VMn (not shown) cascaded The cell VM0, the cell VM1, the cell VM2, and the cell VMn have the same configuration.

  The inter-edge pulse positive signal 6A is connected to the gate terminals of MN201, MN203, MN206, and MN211 and is similarly connected to VMn (not shown). Further, the inter-edge pulse negative signal 6B is connected to the gate terminals of MN202, MN205, MN207, and MN212, and is similarly connected to VMn (not shown).

  The drain terminal of MN201 is output as MB [0] and is connected to the gate terminal of MN210, and is connected to the power supply via MPW0 in which VBPW is connected to the gate terminal. The drain terminals of MN202 and MN204 are short-circuited, connected to the gate terminal of MN208 as an M [0] output, and connected to the power supply via MPW1 in which VBPW is connected to the gate terminal. The source terminals of MN201 and MN202 are short-circuited and connected to the drain terminal of MN203, the source terminals of MN203 and MN205 are short-circuited, and VBNW is grounded via MNW0 connected to the gate terminal. The gate terminal of the MN 204 is connected to the power supply through a resistor, and the source terminal is connected to the drain terminal of the MN 205. The drain terminal of the MN 206 is output as MB [1] and is connected to the gate terminal of the MN 215, and is connected to the power supply via the MPW 2 in which VBPW is connected to the gate terminal. The drain terminals of MN 207 and MN 209 are short-circuited and connected to the gate terminal of MN 213 as an M [1] output, and connected to the power supply via MPW 3 in which VBPW is connected to the gate terminal. The source terminals of MN206 and MN207 are short-circuited and connected to the drain terminal of MN208, and the source terminals of MN208 and MN210 are short-circuited and grounded via MNW1 in which VBNW is connected to the gate terminal. The gate terminal of MN209 is connected to a power supply through a resistor, and the source terminal is connected to the drain terminal of MN210. The drain terminal of the MN 211 is output as MB [2] and is connected to a power source via the MPW 4 having the VBPW connected to the gate terminal. The drain terminals of MN212 and MN214 are short-circuited and output as M [2] output, and VBPW is connected to the power supply via MPW5 connected to the gate terminal. The source terminals of MN211 and MN212 are short-circuited and connected to the drain terminal of MN213, the source terminals of MN213 and MN215 are short-circuited, and VBNW is grounded via MNW2 connected to the gate terminal. The gate terminal of the MN 214 is connected to the power supply through a resistor, and the source terminal is connected to the drain terminal of the MN 215.

  In the variable pulse width remainder dividing circuit 2A and the pulse width remainder dividing circuit 2, the NMOS transistors having the same numbers operate in the same manner. M [0] is connected to the power source by MPW0 having VBPW connected to the gate terminal, and grounded by MNW0 having VBNW connected to the gate terminal. Therefore, the time when the potential of M [0] changes is VBPW And the current limited by VBNW. Also, since MB [0] is connected to the power source by MPW1 having VBPW connected to the gate terminal and grounded by MNW0 having VBNW connected to the gate terminal, the time for the potential of MB [0] to change is , Determined by the current limited by VBPW and VBNW. Similarly, since M [1] is connected to the power source by MPW2 having VBPW connected to the gate terminal and grounded by MNW1 having VBNW connected to the gate terminal, M [1] is a time during which the potential of M [1] changes. Is determined by the current limited by VBPW and VBNW. Also, since MB [1] is connected to the power source by MPW3 with VBPW connected to the gate terminal, and VBNW is grounded with MNW1 connected to the gate terminal, the time for the potential of MB [1] to change is , Determined by the current limited by VBPW and VBNW. Further, since M [2] is connected to the power source by MPW4 having VBPW connected to the gate terminal and grounded by MNW2 having VBNW connected to the gate terminal, the time for the potential of M [2] to change is , Determined by the current limited by VBPW and VBNW. In addition, since MB [2] is connected to the power source by MPW5 having VBPW connected to the gate terminal and grounded by MNW2 having VBNW connected to the gate terminal, the time during which the potential of MB [2] changes is , Determined by the current limited by VBPW and VBNW. As described above, the delay time during which the edge-to-edge pulse positive signal 6A and the edge-to-edge pulse negative signal 6B change to change the potentials of M [0] and MB [0], and M [0] and MB [0] The delay time when the potential of M [1] and MB [1] changes, and the delay time when the potential of M [2] and MB [2] changes when M [1] and MB [1] change Will be determined by the amount of current limited by VBPW and VBNW.

  FIG. 14 is a diagram showing a detailed configuration of the current value control signal generation circuit 7 according to the second embodiment. As shown in the figure, the current value control signal generation circuit 7 is composed of an inverter INV700 that receives an inter-edge pulse positive signal 6A, D-type flip-flops FF700 to FF [700 + n-1], and an up / down count decoder 16. Is done. The output of INV700 is connected to the clock input of FF [700 + J]. Further, the residue result signal M [J] is connected to the D input of FF [700 + J], and the Q output is the residue result holding signal A “J”. The up / down count decoder 16 receives the remainder result holding signal A [J] and the CAL signal 13 and outputs the edge current control signal 11 and the pulse current control signal 12.

  When the calibration operation mode is set by the input CAL signal 13, the up / down count decoder 16 sets the control signal that maximizes the current value in the variable current source 801 of the variable current source 8 as the initial value of the edge current control signal 11. Set as. When the current value of the variable current source 801 is maximized, the edge delay PMOS transistor bias control voltage VBPD and the edge delay NMOS transistor bias control voltage VBND are maximized. Is maximized and the time for transmission to the next stage is minimized, so that the Td time is minimized. When the calibration operation mode is set by the input CAL signal 13, the up / down count decoder 16 sets the control signal that minimizes the current value in the variable current source 802 of the variable current source 8 to the pulse current control signal 12. Set as initial value. When the current value of the variable current source 802 is minimized, the pulse delay PMOS transistor bias control voltage VBPW and the pulse delay NMOS transistor bias control voltage VBNW are minimized. Is minimized and the time for transmission to the next stage is maximized, so that the Ts time is maximized.

  Next, FF [700 + J] latches the remainder result signal M [J] every time a falling edge of the inter-edge pulse positive signal 6A occurs, and sends it to the up / down count decoder 16 as a remainder result holding signal A [J]. Supply. The up / down count decoder 16 changes the edge current control signal 11 so that the remainder result holding signal A [0] of the remainder result holding signal A [0: n−1] is not 0, thereby changing the variable current source 801. Current value is decreased and Td time is increased. Subsequently, the up / down count decoder 16 changes the pulse current control signal 12 so that the remainder result holding signal A [n−1] of the remainder result holding signal A [0: n−1] does not become 1. Thus, the current value of the variable current source 802 is increased and the Ts time is decreased.

  While the current value control signal generation circuit 7 is set to the calibration operation mode by the CAL signal 13, the remainder result holding signal A [0: n that changes every time the falling edge of the inter-edge pulse positive signal 6A occurs. -1], the edge current control signal 11 is changed so that the remainder result holding signal A [0] does not become 0, and the pulse current control signal 12 so that the remainder result holding signal A [n-1] does not become 1. To change.

  That is, since the CAL switching circuit 14 selects the REF signal 9 while the calibration operation mode is set by the CAL signal 13, the remainder result holding signal A [0] is maintained even in the shortest cycle of the REF signal 9. The edge current control signal 11 is changed so as not to become 0, and the pulse current control signal 12 is changed so that the remainder result holding signal A [n−1] does not become 1 even in the longest period of the REF signal 9. The time is set according to the shortest cycle of the REF signal 9, and the Ts time is set according to the longest cycle of the REF signal 9.

  As described above, the jitter measuring circuit 20 with the calibration function operates by adjusting the Td time and the Ts time based on the shortest cycle and the longest cycle of the REF signal 9, and therefore the REF signal 9 is used as a reference. The operation is to measure the jitter of the signal under measurement 5.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows the structure of the jitter measurement circuit which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the detailed structure of the pulse generation circuit between edges which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the detailed structure of the one hot state circuit based on Embodiment 1 of this invention. It is a circuit diagram which shows the detailed structure of the pulse generation circuit between edges which concerns on Embodiment 1 of this invention. 3 is a timing chart showing an operation of the inter-edge pulse generation circuit according to the first embodiment of the present invention. 3 is a timing chart showing the operation of the pulse width remainder dividing circuit according to the first embodiment of the present invention. 3 is a timing chart showing the operation of the pulse width remainder dividing circuit according to the first embodiment of the present invention. It is a figure for demonstrating the state transition of the one hot state circuit which concerns on Embodiment 1 of this invention. 4 is a timing chart showing an operation of the one-hot state circuit according to the first embodiment of the present invention. 3 is a timing chart showing the operation of the cumulative holding circuit according to the first embodiment of the present invention. It is a block diagram which shows the structure of the jitter measuring circuit with a calibration function which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the detailed structure of the 1st variable current source which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the detailed structure of the 2nd variable current source which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the detailed structure of the pulse generation circuit between variable edges which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the detailed structure of the variable pulse width remainder division circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the detailed structure of the electric current value control signal generation circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the jitter detection circuit of related technology. It is a figure which shows the relationship between the comparison pulse generation circuit of related technology, and input / output. It is a block diagram which shows the periodic signal generation circuit of related technology. It is a figure which shows the detailed structure of the periodic signal generation circuit of related technology. It is a timing chart which shows the mode of accumulation | storage of the jitter of a related technique.

Explanation of symbols

1 pulse generation circuit between edges, 2 pulse width remainder division circuit,
3. One hot state circuit, 4. Accumulation holding circuit, 5. Signal to be measured,
6 Inter-edge pulse signal,
M residue result signal, D cycle jitter signal, Q cumulative jitter signal,
Tcyc period time, Teg pulse width, Tjt1 difference time, Tjt2 difference time,
Td first time, Ts second time,
LOOP1 loop condition, LOOP2 loop condition, STATE1 state,
STATE2 state, TRANS1 transition condition, TRANS2 transition condition,
10 Jitter detection circuit, 103 Comparison pulse generation circuit, 1032 EXOR circuit,
104 periodic signal generation circuit, 10420 charge pump circuit, 10421 current source,
10422 switch, 10432 switch, 1043 triangular wave generation circuit,
10431 capacitance, 10433 capacitance output node, 1044 comparator,
1046 switch, 105 counter, 106 counter output signal 1A variable edge pulse generation circuit, 2A variable pulse width remainder dividing circuit 5A measured positive signal, 5B measured negative signal,
6A Positive pulse signal between edges, 6B Negative pulse signal between edges,
7 current value control signal generation circuit,
8 variable current source, 81 first variable current source, 82 second variable current source, 9 REF signal 11 edge current control signal, 12 pulse current control signal, 13 CAL signal 14 CAL switching circuit, 15 calibration unit 16 up / down count Decoder 20 Jitter measurement circuit with calibration function 801 Variable current source, 802 Variable current source, 120 Td time delay element EXOR 2-input ExclusiveOR gate, FF D type flip-flops INV200, INV400, INV700 Inverters M0, M1, M2, and Mn Cells MN101 to MN116, MN201 to MN215, MN801 to 804 NMOS transistors MP101 to MP106, MP801 and MP802, MPW0 to MPW5 PMOS transistor N NAND gate VM0, VM1, VM2, and VMn cell

Claims (10)

An inter-edge pulse generator that generates an inter-edge pulse signal by delaying an input signal under measurement by a first time that is a predetermined time unit from an edge of the signal under measurement;
Dividing the inter-edge pulse signal by a value obtained by multiplying the second time, which is a predetermined time unit, by an integer, and outputting a remainder result by the division operation as a remainder result signal; and
A one-hot-state unit that outputs the integer value when the value of the remainder result signal is minimum as a cycle jitter value signal of the inter-edge pulse signal;
A jitter measuring circuit. When the second time is a multiplicand and the non-negative integer that is the integer is a multiplier,
The pulse width remainder dividing unit subtracts the inter-edge pulse signal by a product of the multiplicand and a multiplier, and divides and outputs the subtracted positive remainder as a remainder result signal for each non-negative integer,
The one hot state unit is a quotient obtained by dividing the inter-edge pulse signal by the second time using the value of the remainder result signal indicating the smallest positive remainder among the values of the remainder result signal. The jitter measurement circuit according to claim 1, wherein a non-negative integer value is calculated, and the calculated non-negative integer value is output as a cycle jitter value signal of the inter-edge pulse signal. The pulse width remainder dividing unit is configured by a gate element in which delay elements that delay the second time are connected in multiple stages,
The inter-edge pulse signal is input to at least one input to the pulse width remainder dividing unit, and the pulse width output from each of the multi-stage connected gate elements indicates a positive remainder for each non-negative integer. The jitter measuring circuit according to claim 2, wherein: The one-hot state unit calculates the smallest positive remainder by detecting that the positive remainder for each non-negative integer output from the pulse width remainder division unit is zero. Item 4. The jitter measuring circuit according to Item 2 or 3. 5. The jitter measurement circuit according to claim 1, further comprising an accumulation holding unit that accumulates and holds the cycle jitter value for each inter-edge pulse signal. The cumulative holding unit is
The jitter measurement circuit according to claim 5, wherein the cycle jitter value is accumulated and held using a timing signal corresponding to a non-measurement time generated in the first time in the inter-edge pulse generation unit. The inter-edge pulse generator generates an inter-edge pulse signal that is a pulse signal from the rising edge delayed by the first time to the next rising edge in the input signal under measurement. The jitter measuring circuit according to any one of claims 1 to 6. The jitter measuring circuit according to any one of claims 1 to 7, further comprising a calibration unit that makes the first time and the second time variable. When the calibration operation mode is set to calibrate the first time and the second time based on the residue result signal and the inter-edge pulse signal,
The inter-edge pulse generator is
An inter-edge pulse signal is generated by delaying the input signal under measurement by a first time which is a predetermined time unit from the edge of the signal under measurement;
The pulse width remainder dividing unit is
Dividing the inter-edge pulse signal by a value obtained by multiplying the second time, which is a predetermined time unit, by an integer, and outputting a remainder result by the division operation as a remainder result signal;
The calibration unit
Using the inter-edge pulse signal generated by the inter-edge pulse generator as a timing signal, the first time and the second time are calibrated according to the variation of the remainder result signal output by the pulse width remainder divider. The jitter measuring circuit according to claim 8. The calibration unit
A switching unit that selects the reference signal among the input signal under measurement and the reference signal and outputs the selected signal to the inter-edge pulse generation unit;
When the calibration operation mode is set, the edge current control is performed according to the fluctuation of the remainder result signal output from the pulse width remainder division section using the inter-edge pulse signal generated by the edge-to-edge pulse generation section as a timing signal. A current value control signal generator for outputting a signal and a pulse current control signal;
A first variable current source that calibrates the first time based on an edge current control signal generated by the current value control signal generator;
A second variable current source that calibrates the second time based on the pulse current control signal generated by the current value control signal generator;
The jitter measuring circuit according to claim 8 or 9, characterized by comprising:

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