JP4415748B2 - Sample hold circuit - Google Patents

Description

  The present invention relates to a sample and hold circuit that can be configured without using a hold capacitor.

  Conventionally, a sample and hold circuit using a hold capacitor and a switch as described in FIG. 4 of Patent Document 1 has been used. Since this sample and hold circuit is greatly affected by a leakage current flowing from the hold capacitor through the switch and a feedthrough offset generated when the switch is switched from on to off, these effects are reduced in FIG. 1 and FIG. A sample and hold circuit is disclosed.

That is, the sample hold circuit shown in FIG. 1 of Patent Document 1 includes a hold capacitor, a buffer amplifier that outputs a voltage held in the hold capacitor, a first switch that switches between an input signal and an output signal of the buffer amplifier, And a second switch for controlling writing / holding of an input signal to the hold capacitor. In the sampling period, the first switch is switched to the input signal side and the second switch is turned on. In the hold period, the second switch is turned off and the first switch is switched to the buffer amplifier output signal side. According to this, since the potential difference between the source and the drain of the switch SW2 including the transistors M5 and M6 shown in FIG. 2 of Patent Document 1 becomes 0 V at the time of holding, the source to the drain (or the drain to the source) The leak current that flows is zero.
JP-A-7-262789

  However, since the transistor leakage current path exists not only between the source and drain, but also at the well-source and well-drain reverse-biased PN junctions, the leakage current that flows out (or flows in) from the hold capacitor during holding is completely eliminated. Cannot be zero. Therefore, in the conventional sample-and-hold circuit that holds the sampled voltage by holding the charge of the capacitor, fluctuation of the hold voltage due to leakage current is inevitable, and long-time holding is difficult. In addition, since the leakage current increases exponentially as the temperature increases, the influence is particularly great in an in-vehicle system that is required to operate at a high temperature, for example, an IC mounted in an engine control ECU or the like.

  In a sample-and-hold circuit composed of a capacitor and a switch, it is caused by the charge injected into the capacitor through the gate-drain (source) capacitance of the transistor that constitutes the switch at the moment of transition from the sample operation to the hold operation. It is difficult to completely eliminate the effect of so-called feedthrough, which is an offset error, and to make the offset error zero.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a sample-and-hold circuit in which variation in hold voltage is extremely small and high in accuracy.

  According to the first aspect of the present invention, in the pulse circuit in which a plurality of delay elements whose delay times change according to the power supply voltage are connected in a ring shape, the pulse signal is changed to the delay time of the delay elements, that is, the power supply voltage. Rotate at the appropriate speed. This circulation speed is obtained by counting the number of delay elements through which the pulse signal passes within a certain counting time by the passing element number counting circuit. During the sampling period, the input voltage that is the sampling target voltage becomes the power supply voltage of the delay element through the switching circuit, and the passing element count circuit is the number of delay elements (number of passing elements) through which the pulse signal has passed at least once in the sampling period. And the count value is held in the holding circuit. The held count value corresponds to the sampled input voltage, that is, the sampling voltage.

  When the sampling period shifts to the hold period, the feedback voltage generation circuit generates a feedback voltage based on the comparison between the count value output from the passing element count circuit and the count value held in the holding circuit. Is applied as a power supply voltage of the delay element of the pulse circuit through the switching circuit. By this feedback control, the count value held in the holding circuit and the count value sequentially output from the passing element number counting circuit coincide with each other during the hold period, and the feedback voltage, that is, the hold voltage becomes equal to the sampling voltage.

  According to this means, the analog input voltage is converted to a digital number of passing elements and held, and the count value feedback control is performed in the hold period. Therefore, compared to the conventional method using a hold capacitor, In addition, a highly accurate hold operation is possible. In addition, the analog circuit used in the feedback path does not require high accuracy, and thus has an advantage that it is easy to configure. Furthermore, according to this means, the influence of feedthrough, which has been a problem in the past, does not appear.

  According to the means described in claim 2, the feedback voltage generation circuit compares the count value output from the passing element number counting circuit with the count value held in the holding circuit in the hold period, and according to the comparison result The feedback voltage is generated by integrating the measured voltage. When the integration circuit is used, the deviation of the count value can be constantly controlled to zero, so that the sampling voltage and the hold voltage can be matched with high accuracy.

  According to the third aspect of the present invention, the feedback voltage generation circuit calculates the difference between the count value output from the passing element number counting circuit and the count value held in the holding circuit during the hold period. The feedback voltage is generated by integrating the difference between the counted values. When the integration circuit is used, the deviation of the count value can be constantly controlled to zero, so that the sampling voltage and the hold voltage can be matched with high accuracy.

  According to the means described in claim 4, the passing element number counting circuit counts the number of laps of the pulse signal in the pulse circulator circuit, detects the position of the pulse signal in the pulse circulator circuit, and detects the pulse at a constant counting time. The number of delay elements through which the pulse signal has passed is calculated based on the number of signal laps and the change in position.

  According to the means described in claim 5, in the ring oscillator in which a plurality of delay elements whose delay times change according to the power supply voltage are connected in a ring shape, the pulse signal corresponds to the delay time of the delay elements, that is, the power supply voltage. Orbit at a different speed. This orbital speed is measured by the orbital speed measuring circuit. During the sampling period, the input voltage, which is the sampling target voltage, is applied as a power supply voltage to the delay element through the switching circuit. The circuit speed measurement circuit measures the circuit speed at least once during the sampling period, and the circuit speed is stored in the holding circuit. Hold. The held circulation speed corresponds to the sampled input voltage, that is, the sampling voltage.

  When the sampling period shifts to the hold period, the feedback voltage generation circuit generates a feedback voltage based on the comparison between the rotation speed measured by the rotation speed measurement circuit and the rotation speed held in the holding circuit. Is applied as a power supply voltage of the delay element of the pulse circuit through the switching circuit. By this feedback control, during the hold period, the revolution speed held in the holding circuit and the revolution speed sequentially measured by the revolution speed measurement circuit coincide with each other, and the feedback voltage, that is, the hold voltage becomes equal to the sampling voltage.

  According to this means, the hold operation can be performed for a long time and with high accuracy as compared with the method using the conventional hold capacitor. In addition, the analog circuit used for the feedback path does not require high accuracy and is easy to configure. Furthermore, there is no influence of feedthrough.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows an electrical configuration of a sample and hold circuit used in a semiconductor integrated circuit device mounted on an in-vehicle ECU. The sample hold circuit 1 samples the input voltage Vin applied to the signal input terminal 2 during the sampling period, and outputs the sampling voltage from the signal output terminal 3 as the hold voltage Vh during the hold period. The sample-and-hold circuit 1 includes a ring oscillator 100, a passing element number counting circuit 4, a register 5 (corresponding to a holding circuit), a feedback voltage generating circuit 6, a switch 7 (corresponding to a switching circuit), and an operational amplifier 8. The signal input terminal 2 is connected via a switch 7 to a non-inverting input terminal of an operational amplifier 8 having a voltage follower connection form.

  The ring oscillator 100 (corresponding to a pulse circuit) is connected in series so that 31 (that is, odd number) inverters 101 to 131 (corresponding to delay elements) form a ring shape as a whole. The signal goes around. The power supply line 9 of the inverters 101 to 131 is connected to the output terminal of the operational amplifier 8, and the power supply line 10 is connected to the ground. A capacitor 11 is connected between the power supply lines 9 and 10. The inversion operation time td (corresponding to the delay time) of the inverters 101 to 131 becomes smaller as the voltage between the power supply lines 9 and 10 (hereinafter referred to as power supply voltage) becomes higher, and accordingly, the circulation speed of the pulse signal becomes faster. .

  For each cycle of the clock CKL, the passing element count circuit 4 counts the number of inverters through which the pulse signal has passed in the ring oscillator 100 in one cycle of the clock CKL (corresponding to a certain counting time) (hereinafter referred to as the number of passing elements). Called). This passing element number counting circuit 4 includes a counting circuit 12 for counting the number of laps of the pulse signal in the ring oscillator 100, a position detecting circuit 13 for detecting the position of the pulse signal in the ring oscillator 100, and a signal processing circuit 14 (passing element). And a register 19. The circuit counting circuit 12 includes a 10-bit counter 15 and a register 16, and the position detection circuit 13 includes a pulse selector 17 and an encoder 18.

  The clock terminal of the counter 15 is connected to the output terminal of the inverter 131, and the data output terminal is connected to the data input terminal of the register 16. The clock CKL is input to the clock terminal of the register 16, and the data output terminal is connected to the data input terminal of the signal processing circuit 14. The pulse selector 17 includes a flip-flop having the outputs of the inverters 101 to 131 as data inputs and CKL as a clock input, and an exclusive OR circuit having two outputs from the adjacent flip-flops (both are inputs). (Not shown), each of the output signals of the inverters 101 to 131 is input, and the position of a pulse signal (circulation pulse signal) that circulates the ring oscillator 100 is output. The encoder 18 converts (encodes) the pulse position output from the pulse selector 17 into 5-bit position data and outputs it.

  The signal processing circuit 14 inputs the number of laps output from the register 16 as the upper 10 bits and the pulse position output from the encoder 18 as the lower 5 bits, obtains the difference from the previously input value, and uses it as the pass element It is output as a number. The register 19 holds the output value from the signal processing circuit 14 in synchronization with the up edge of the clock CKB, and the register 5 holds the output value from the register 19 in synchronization with the up edge of the clock CKA. It has become. The clocks CKA and CKB are clock signals having a phase opposite to that of the clock CKL. The clocks CKL and CKB are always applied during the sampling period and the hold period, whereas the clock CKA is applied only during the sampling period.

  The feedback voltage generation circuit 6 includes a comparison circuit 20 and an integration circuit 21. The comparison circuit 20 always compares the output value of the register 19 with the output value of the register 5, and if the output value of the register 19 is smaller than or equal to the output value of the register 5, the L level voltage Vc (for example, 0V) When the output value of the register 19 is higher than the output value of the register 5, an H level voltage Vc (for example, 5V) is output.

  FIG. 2 shows the electrical configuration of the integrating circuit 21. The input terminal to which the voltage Vc is input is connected to the inverting input terminal of the operational amplifier 24 through the switch 22 and the resistor 23, and the reference voltage Vref is applied to the non-inverting input terminal of the operational amplifier 24. A resistor 25 is connected between the inverting input terminal of the operational amplifier 24 and the output terminal of the hold voltage Vh, and a series circuit of a capacitor 26 and a switch 27 is connected in parallel with the resistor 25. A common connection point between the capacitor 26 and the switch 27 (output node of the feedback voltage VFB) is connected to the non-inverting input terminal of the operational amplifier 8 (see FIG. 1). The switches 7, 22, and 27 are composed of analog switches, and are on / off controlled by a control circuit (not shown).

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG.
As described above, the clocks CKL and CKB are clock signals having a constant period Tc that are in an opposite phase relationship to each other, and are constantly input in the sampling period and the hold period. On the other hand, the clock CKA is the same clock signal as the clock CKB during the sampling period, and is a signal fixed to the H level or the L level during the hold period. The period Tc is set to 1 μsec, for example. Hereinafter, the operation will be described by dividing it into a sampling period and a hold period.

(1) Sampling period A control circuit (not shown) turns on the switch 7 connected to the signal input terminal 2, turns off the switches 22 and 27 of the integrating circuit 21, and repeatedly samples the input voltage Vin every cycle Tc. . That is, in the ring oscillator 100, for example, when the input level of the inverter 101 changes from H level to L level, the output of the inverter 101 changes from L level to H level after being delayed by the inversion operation time td. The output of the inverter 102 of the stage changes from the H level to the L level with a delay of the inversion operation time td.

  The pulse signal generated by such inversion operation proceeds to the next inverter in order while being delayed by the inversion operation time td. Eventually, the output of the inverter 131 changes from the L level to the H level after being delayed by (31 × td) from the time when the input level of the inverter 101 changes from the H level to the L level. Since the output of the inverter 131 is connected to the input of the inverter 101, the output of the inverter 101 changes from the H level to the L level.

  That is, the level of the connection node (hereinafter simply referred to as the connection node) of each inverter constituting the ring oscillator 100 is inverted every time (31 × td). For this reason, the 10-bit counter 15 connected to the output node of the inverter 131 counts up every period (31 × td) in synchronization with the rise and fall of the output of the inverter 131. This count value is the number of rounds of the pulse signal.

  On the other hand, the ring oscillator 100 is composed of an odd number of inverters 101 to 131, and the level of the connection node of each of the inverters 101 to 131 changes sequentially while being delayed by the inversion operation time td. Looking at the input / output levels of the inverters 101 to 131, there is only one inverter in which the input level and the output level are the same voltage level. In this inverter, the output is about to change at this moment, and can be regarded as the current position of the circulating pulse signal.

  The pulse selector 17 is a circuit for detecting the position of the circular pulse signal, holds the voltage of each connection node at the rising point of the clock CKL in an internal flip-flop, and outputs these outputs to the exclusive OR circuit. The position of the circulating pulse signal is detected by inputting and comparing the voltage levels of adjacent connection nodes. The output of the pulse selector 17 is encoded into 5-bit data by the encoder 18.

  The clock CKL is also input to the clock terminal of the 10-bit register 16, and the register 16 holds the output value of the counter 15 in synchronization with the rising edge of the clock CKL. The signal processing circuit 14 generates 15-bit data in which the number of laps output from the register 16 is the upper 10 bits and the pulse position output from the encoder 18 is the lower 5 bits, and is synchronized with the previous rise of the clock CKL. Then, the difference from the 15-bit data input is obtained. This data is the number of inverters through which the circular pulse signal has passed during the period Tc, that is, the number of passing elements.

  For example, the number N4 of passing elements of the circulating pulse signal during the period Tc from time t10 to time t20 is determined after the processing time of the encoder 18 and the signal processing circuit 14 with respect to time t20, and is held in the register 19 at time t21. Is done. Similarly, the number N5 of passing elements of the circulating pulse signal during the period Tc from time t20 to time t30 is determined after the processing time of the encoder 18 and the signal processing circuit 14 with respect to time t30, and is stored in the register 19 at time t31. Retained. Since the register 19 and the register 5 are in a shift register relationship, the previous passing element number N4 is moved from the register 19 to the register 5 at time t31. The reason why the clock CKL and the clocks CKA and CKB are shifted by a half cycle is due to the delay due to the processing time.

  By the operation described above, the registers 19 and 5 output the number of passing elements in the preceding cycle Tc as a binary digital value in synchronization with the rising edges of the clocks CKB and CKA. The number of passing elements has a characteristic of increasing monotonously with an increase in power supply voltage between the power supply lines 9 and 10, and corresponds to the sampling voltage.

(2) Hold period When the clock CKA rises and is fixed at the H level at time t31, the output value N4 of the register 5 (the count value during the period from time t10 to t20) is held after time t31. At time t40, when the switch 7 connected to the signal input terminal 2 is turned off and the switches 22 and 27 of the integrating circuit 21 are turned on by a control circuit (not shown), the hold operation starts. During the hold period, the integration circuit 21 integrates the output voltage of the comparison circuit 20 updated every cycle Tc, and the feedback voltage VFB output from this integration circuit passes through the operational amplifier 8 that operates as a buffer circuit. It is given between the power supply lines 9 and 10.

  More specifically, when the clocks CKA and CKB rise at time t31, the number N4 of passing elements that have been held in the register 19 so far is held in the register 5, and the cyclic pulse signal between time t20 and time t30 The number N5 of passing elements is newly held in the register 19. The comparison circuit 20 compares the value N5 of the register 19 with the value N4 of the register 5, and outputs an L level (0V) voltage Vc if N5 <N4, for example. After time t40 when the hold period starts, the integration circuit 21 performs an integration operation with the voltage Vc as an input. In the hold period in which the switch 27 is on, the feedback voltage VFB and the hold voltage Vh are equal.

  Thereafter, when the clock CKB rises at time t41, the number of passing elements N6 of the circulating pulse signal between time t30 and time t40 is held in the register 19. The comparison circuit 20 compares the value N6 of the register 19 with the value N4 of the register 5, and outputs an H level (5V) voltage Vc if N6> N4, for example. As a result, the feedback voltage VFB output from the integrating circuit 21 gradually decreases. Thereafter, the feedback voltage VFB is similarly generated.

  According to this feedback operation, when the number of passing elements N6, N7, N8,... Sequentially measured in the hold period becomes larger than the number N4 of passing elements measured in the sampling period, the power supply voltage of the inverters 101 to 131 is lowered. On the contrary, when it becomes smaller, the power supply voltage of the inverters 101 to 131 is raised. As a result, the number of passing elements measured in the sampling period and the number of passing elements sequentially measured in the hold period coincide with each other with high accuracy. That is, the input voltage Vin (sampling voltage) that was the power supply voltage of the inverters 101 to 131 during the sampling period from time t10 to time t20 and the power supply voltage (feedback voltage VFB) of the inverters 101 to 131 during the hold period. This means that the hold voltage Vh of () matches with high accuracy.

  According to the present embodiment described above, the characteristics in which the inversion operation time td of the inverters 101 to 131 constituting the ring oscillator 100 is dependent on the power supply voltage are used, and the input voltage Vin to be sampled is set as the circular pulse signal in the ring oscillator 100. Is measured and held as the peripheral speed, and the power supply voltage of the inverters 101 to 131 is feedback-controlled so that the peripheral speed during the hold period coincides with the retained peripheral speed. Then, the circulation speed is obtained by measuring the number of inverters (number of passing elements) through which the circulation pulse signal has passed during a certain period Tc.

  According to this configuration, the analog input voltage Vin is converted into a digital number of passing elements and held, and feedback control of the number of passing elements is performed in the hold period. Therefore, compared to a method using a conventional hold capacitor, A long-time and highly accurate hold operation is possible. Further, there is an advantage that it is easy to configure because it is not affected by the offset error of the operational amplifier 8 and high accuracy is not required for the analog circuit (for example, the operational amplifier 8) used in the feedback path. Furthermore, there is no influence of feedthrough, which has been a problem in the past.

  In the sampling period, the input voltage Vin is applied to one end of the capacitor 26 with the switches 22 and 27 of the integrating circuit 21 being turned off, and the capacitor 26 is initially charged with the input voltage Vin. Thereby, a transient phenomenon immediately after the transition from the sampling period to the hold period is suppressed, and a stable hold voltage Vh can be obtained immediately after the transition.

  In the method using the conventional hold capacitor, the leakage current increases exponentially as the temperature becomes higher. On the other hand, the sample hold circuit 1 according to the present embodiment does not use the hold capacitor, and therefore requires an operation at a high temperature. This is suitable for an in-vehicle system such as an IC mounted on an engine control ECU. Since the inversion operation time td of the inverters 101 to 131 changes depending on the temperature, it is necessary to keep the temperature constant in order to make the hold voltage Vh coincide with the sampling voltage accurately. However, since the change in the junction temperature of the chip is very small within the normal hold time, the influence on the accuracy is very small.

By dividing the system clock of the IC on which the sample-and-hold circuit 1 is mounted by a fraction of an integer to generate clocks CKL, CKA, and CKB, clock noise caused by the system clock can be removed.
The present invention is not limited to the embodiment described above and shown in the drawings. For example, the present invention can be modified or expanded as follows.

  The pulse circuit is not limited to the ring oscillator 100. In general, a plurality of delay elements whose delay time varies depending on the power supply voltage are connected in a ring shape, and the pulse signal may circulate around these delay elements. The delay element is not limited to an inverter, and the number of connections may be either an even number or an odd number. However, in the above-described ring oscillator 100, it is necessary to use an odd number of inverters in order to satisfy the oscillation condition.

  In the above embodiment, the number of pass elements is periodically determined during the sampling period. However, the number of pass elements may be determined at least once during the sampling period. However, sampling of the input voltage Vin, that is, counting of the number of passing elements is preferably performed immediately before shifting to the hold period.

  The feedback voltage generation circuit obtains a difference between the number of passing elements successively held in the register 19 of the passing element number counting circuit 4 and the number of passing elements held in the register 5 by a difference calculation circuit (for example, a subtraction circuit). The feedback voltage VFB may be generated by integrating the difference value with an integration circuit. Further, instead of the integrating circuit 21 used in the feedback voltage generating circuit 6, a proportional circuit, a proportional / integrating circuit, or other regulators may be used.

The circulating speed of the circulating pulse signal in the ring oscillator 100 may be measured based on the oscillation frequency or the oscillation cycle of the ring oscillator 100.
The capacitor 11 may be provided as appropriate for noise removal.

1 is an electrical configuration diagram of a sample-and-hold circuit showing an embodiment of the present invention. Electrical configuration diagram of integration circuit Timing chart of sampling period and hold period

Explanation of symbols

  1 is a sample and hold circuit, 4 is a passing element number counting circuit (circulation speed measuring circuit), 5 is a register (holding circuit), 6 is a feedback voltage generation circuit, 7 is a switch (switching circuit), 12 is a circulation number counting circuit, 13 is a position detection circuit, 14 is a signal processing circuit (passage element number calculation circuit), 20 is a comparison circuit, 21 is an integration circuit, 100 is a ring oscillator (pulse circuit), and 101 to 131 are inverters (delay elements). .

Claims (5)

A plurality of delay elements whose delay time varies depending on the power supply voltage are connected in a ring shape, and a pulse circuit in which a pulse signal circulates these delay elements,
A passing element number counting circuit that counts the number of delay elements that the pulse signal has passed through the pulse circuit within a predetermined counting time at least once in the sampling period and periodically in the hold period;
A holding circuit for holding the count value output from the passing element number counting circuit before the transition from the sampling period to the hold period;
A feedback voltage generation circuit that generates a feedback voltage based on a comparison between the count value output from the passing element number counting circuit and the count value held in the holding circuit in the hold period;
A switching circuit that performs switching control so that the input voltage is used as the power supply voltage of the delay element during the sampling period and the feedback voltage is used as the power supply voltage of the delay element during the hold period. A sample-and-hold circuit. The feedback voltage generation circuit includes:
A comparison circuit that compares the count value output from the passing element number counting circuit with the count value held in the holding circuit in the hold period, and outputs a voltage according to the comparison result;
2. The sample and hold circuit according to claim 1, wherein the sample and hold circuit comprises an integrating circuit for integrating a voltage output from the comparison circuit. The feedback voltage generation circuit includes:
A difference calculation circuit for calculating a difference between the count value output from the passing element number counting circuit and the count value held in the holding circuit in the hold period;
2. The sample and hold circuit according to claim 1, wherein the sample and hold circuit comprises an integrating circuit that integrates a difference between count values calculated by the difference calculating circuit. The passing element number counting circuit,
A circulation number counting circuit for counting the number of circulations of the pulse signal in the pulse circulation circuit;
A position detection circuit for detecting a position of the pulse signal in the pulse circuit;
2. A passing element number calculating circuit that calculates the number of delay elements that the pulse signal has passed based on the number of laps and the change in position of the pulse signal in the fixed counting time. 4. The sample hold circuit according to any one of 1 to 3. A ring oscillator in which a plurality of delay elements whose delay time varies depending on a power supply voltage is connected in a ring shape, and a pulse signal circulates around these delay elements;
A revolving speed measurement circuit for measuring a revolving speed of the pulse signal in the ring oscillator at least once in the sampling period and repeatedly in the hold period;
A holding circuit for holding the circulation speed measured by the circulation speed measurement circuit in the sampling period;
In the hold period, a feedback voltage generation circuit that generates a feedback voltage based on a comparison between the rotation speed measured by the rotation speed measurement circuit and the rotation speed held in the holding circuit;
A switching circuit that performs switching control so that the input voltage is used as the power supply voltage of the delay element during the sampling period and the feedback voltage is used as the power supply voltage of the delay element during the hold period. A sample-and-hold circuit.

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