WO2009122843A1

WO2009122843A1 - Frequency synthesizer and method for controlling oscillation frequency of oscillator

Info

Publication number: WO2009122843A1
Application number: PCT/JP2009/053987
Authority: WO
Inventors: 正前多
Original assignee: 日本電気株式会社
Priority date: 2008-03-31
Filing date: 2009-03-03
Publication date: 2009-10-08
Also published as: JPWO2009122843A1; JP5333439B2

Abstract

Frequency control with a high accuracy is carried out by means of a high-speed PLL circuit driven at low voltage. A frequency control word (FCW) represents a target multiplier of a reference signal (FREF) with respect to an oscillator output (CVK). A phase detector (51) accumulates the frequency control word (FCW) at the timing of the reference signal (FREF) to detect the phase φR01 of the reference signal (FREF). A phase detector (52) accumulates the number of clocks of the oscillator output (CVK) at the timing of the reference signal (FREF) to detect the phase φV01 of the oscillator output (CVK). A phase detector (53) accumulates the number of clocks of the oscillator output (CVK) at the timing fR1 of the reference signal (FREF) which is delayed by a delay element (61) to detect the phase φV02 of the oscillator output (CVK). A phase detector (57) accumulates the number of clocks of the oscillator output (CVK) at the timing fR2 of the reference signal (FREF) which is delayed by the delay element (61) and a delay element (62) to detect the phase φV00 of the oscillator output (CVK). The sum of the phase φV00 and the phase φV01 and the difference between them are calculated. The results are divided by a divider (86) to calculate the number of clocks φ0 of the oscillator output (CVK) for the time delayed by one delay element. The sum of the phase φR01 and the phase φV01 and the difference between them are calculated to obtain a first phase error signal. The sum of the phase φR01, the phase φ0, and the phase φV02 and the difference between the sum of the phase φR01 and the phase φ0 and the phase φV02 are calculated to obtain a second phase error signal. The first and second phase error signals are combined into a composite signal, and the frequency of the oscillator is controlled by the composite signal.

Description

Frequency synthesizer and method of controlling oscillation frequency of oscillator

The present invention relates to a frequency synthesizer and an oscillation frequency control method of an oscillator, and in particular, a phase for detecting a phase difference between an oscillation clock of a voltage controlled oscillator built in a phase locked loop (PLL) and a reference clock as a digital signal. The present invention relates to a frequency synthesizer having a comparator, a voltage controlled oscillator digitally controlled by the output of the phase comparator, and a method of manufacturing an oscillation frequency of the oscillator.

High-speed wireless communication methods such as IEEE 802.11a / g WLAN introduce advanced modulation such as 16 QAM and 64 QAM in order to efficiently perform large-capacity signal transmission within a limited frequency band. In these wireless chips, because of the large power consumption of the digital signal processing unit, they have not been incorporated into terminals such as mobile phones except for the relatively low speed IEEE 802.11b. In recent years, in order to perform such signal processing with low power consumption, application to a baseband of a fine CMOS device is advanced. Along with that, the power supply voltage of the baseband is low. In the future, there is a tendency to accelerate so-called system-on-chip (SoC) integration in which the digital part and the RF part are integrated in order to reduce the cost. In this case, the RF circuit also needs to operate at a low voltage because it is necessary to form an RF unit with a fine device. However, in the RF circuit based on the related analog method, it is difficult to lower the voltage beyond this in consideration of the element characteristic fluctuation due to the miniaturization. One of the RF blocks that are greatly affected by the reduction in voltage is the PLL. FIG. 5 is an example of a related analog PLL. In FIG. 5, 1 is a phase comparator, 2 is a charge pump, 3 'is a loop filter, 4 is a voltage controlled oscillator (VCO), and 5 is a divider.

The operation of this circuit is described below. The phase comparator 1 generates output signals S1 and S2 based on the result of comparison between the reference signal FREF and the divided signal CKV of the VCO. The signal S1 is a signal indicating the amount of phase advance of the reference signal FREF with respect to the CKV signal. The signal S2 is a signal indicating the amount of phase advance of the CKV signal with respect to the reference signal FREF. These signals S 1 and S 2 are input to the charge pump 2. The output signal S3 of the charge pump 2 is input to the loop filter 3 ', where high frequency components are removed therefrom, and then input as the control voltage S4 of the VCO 4.

In this PLL circuit, when it operates so that the phases of the reference signals FREF and CKV coincide with each other, the PLL circuit locks and the frequency (fVCO) obtained from the voltage control oscillator 4 becomes the frequency division number of the reference signal FREF.

The frequency of the VCO is determined, for example, by changing the control voltage of the MOS varactor in the case of the type utilizing the resonance frequency of the inductor and the MOS varactor capacitance. However, when the modulation sensitivity, which is the amount of change in frequency, to the change in control DC potential is increased, there is a problem that the frequency of the VCO fluctuates due to the influence of power supply noise and induced noise. In order to solve this, a method of switching a plurality of resonance circuits while setting the modulation sensitivity low has also been proposed. On the other hand, the control range of the capacitance is limited to the linear region of the varactor. Therefore, when the power supply voltage is lowered, the modulation sensitivity of the VCO has to be increased as a result, and there has been a problem that the frequency of the local oscillator fluctuates due to the noise outside the chip and the inside.

As a means for avoiding this problem, a circuit for digitally controlling a VCO has been disclosed (see, for example, Patent Document 1 and Non-patent Document 1). In this related art, the control of the varactor of the VCO is a method of repeating on / off temporally and changing the time ratio, instead of applying a direct current potential. In the above-mentioned patent and the literature, the signal is randomized by using a sigma delta (ΣΔ modulation) modulator because the time ratio causes a large spurious emission if it is performed at a constant period.

How this PLL detects and controls the frequency of the digitally controlled oscillator (VCO) will be described using FIG. The phase of the reference signal FREF output from the reference crystal oscillator is obtained by accumulating the frequency control word FCW in the latch 102 at each rise of the signal in the phase detector 51 (this frequency control word is This corresponds to the frequency ratio of the output signal CKV of the VCO 105 with respect to the reference signal, ie, the multiplication number). The phase of the output signal CKV of the oscillator is obtained by counting the number of clock transitions of its rising edge in the phase detector 52 in the latch 118 and further by accumulating the output on the reference signal in the latch 119. ing.

The relationship of the phase calculated by each phase detector will be specifically described with reference to FIGS. 7A to 7D. FIG. 7A is a circuit for detecting the phase of the output signal CKV of the VCO, and has the same configuration as that of the phase detector 52 in FIG. In this figure, a 4-bit adder and latch circuit are used. As shown in FIG. 7B, the value of the adder is accumulated at the rising edge of the CKV signal, and the value of the output of the VCO is latched at each rising edge of the reference signal. In this example, it is assumed that the initial value of the adder is 0 and the CKV count starts and the frequency ratio of the CKV signal and the reference signal FREF is 10. On the other hand, since the adder has a 4-bit configuration, the value of 16 or more that causes an overflow is counted from zero. Therefore, the latch outputs at the timing of FREF are 0, 10, 4, 14, 8.

On the other hand, the phase of the reference signal is performed by the circuit of FIG. 7C, which is also the same configuration as the phase detector 51 in FIG. As described above, 10 is input to the frequency control word (FCW) indicating the target multiplication number, and the phase signal is incremented by 10 each time the reference frequency FREF rises. FIG. 7D is a diagram for explaining this operation, and shows the case where the initial value of the adder is three. Since the initial value is 3 and incremented by 10 each time, the output of the circuit for each FREF is 3, 13, 7, 1, 11. In the example of this figure, the frequency of the VCO matches the target but the phase is shifted by three pulses of the VCO.

The means for detecting the phase difference signal of the detected VCO and the reference signal FREF will be described again by returning to FIG. The phase error of these signals is performed in a phase comparator 81 provided with

phase detectors

51 and 52 and an adder / subtractor 122. That is, the phase error is obtained by simply performing arithmetic subtraction in the adder / subtractor 122 of the two digital numerical values described above. The obtained phase error signal is fed back to the oscillator via the interface circuit 107 which performs processing such as gain adjustment to the oscillator after the high speed component is removed by the digital loop filter 103.

However, the resolution equal to or less than the oscillation period of the VCO can not be realized only by the phase detection method based on the accumulation of the number of transitions for each rising edge of the CKV signal described above. Therefore, in the example of the above document, the small phase comparator 82 is provided, and a minute phase error is detected using the time digital converter (TDC) 83.

In a time-to-digital converter (TDC), as shown in FIG. 8 and FIG. 9, the position of the detected “1” to “0” transition of the CKV signal is the sampling edge of FREF 110 and the rising edge of CKV signal. The position of the detected “0” to “1” transition of the CKV signal, indicated by the delay time Δtr during 302, is the delay time between the sampling edge of FREF 110 and the falling edge 400 of CKV signal 114 It is shown by Δtf. The delay times Δtr, Δtf are quantized and are shown as multiples of the circuit time resolution Δtres.
Here, the small phase error ΦF is given by −Δtr / 2 (Δtf−Δtr) when Δtf> Δtr, and 1−Δtr / 2 (Δtr−Δtf) when Δtr> Δtf. Given by

FIG. 10 is a circuit example of the time-to-digital converter 83 for detecting a phase error less than the CKV signal cycle shown in FIG. The time-to-digital converter 500 is composed of a plurality of inverter delay elements 502 and a latch / register 504. CKV signal 114 is sequentially delayed by a plurality of inverters, and the delayed vectors are latched in latch / register 504 on the rising edge of the reference clock from reference crystal oscillator FREF 110, respectively. As long as the total delay of the inverter array sufficiently covers the clock cycle of CKV 114, it is possible to detect a phase error up to the resolution Δtres of the delay time of the inverter.

FIG. 11 shows a timing chart 600 for explaining the operation of the circuit shown in FIG. At the positive transition 602 of the reference crystal oscillator FREF 110, the plurality of latches / registers 504 are accessed to obtain a plurality of instantaneous values 604 indicative of the delay of the CKV signal 114 relative to the rising edge of the reference oscillator FREF 110. This instantaneous value 604 can be viewed as indicating the time difference as a digital value.

The digital value is added to or subtracted from the output of the phase detector 51 by the adder-subtractor 123. The minute phase error signal calculated by the adder / subtractor 123 has its high speed component removed by the digital loop filter 104, and after being modulated by the ΔΔ modulator 108, the frequency of the VCO 105 is controlled with high accuracy.
Japanese Patent Laid-Open No. 2002-76886 Journal of Solid-State Circuit, Vol 39, No. 12, 2004, pp. 2278-2291

By thus controlling the VCO digitally, it is possible to realize a stable, highly accurate oscillation signal even in the low voltage operation of the fine CMOS device. However, as the oscillation frequency of the VCO increases, it is expected that the demand for time resolution will become severe. Since the time resolution of the related art described above is determined by the delay time of the inverter, a delay time less than a certain level can not be realized in semiconductor manufacturing technology. For example, where one cycle is 125 ps at 8 GHz, the resolution is about 20 ps at 90 nm process. In addition to this, even if the resolution is improved, the variation of the delay time of each inverter (in-chip variation) directly leads to the accuracy of the phase detector, so that the VCO can not be controlled with high accuracy.

An object of the present invention is to solve the problems of the related art described above, and its object is to increase the phase difference between a VCO and a reference signal as a digital signal without using a multistage inverter even in low voltage operation. An object of the present invention is to provide a phase comparator that can be detected with high accuracy, and it is possible to control the oscillation frequency with high accuracy even if the oscillation frequency of the VCO is further increased.

In order to achieve the above object, according to the present invention, a delay element to which a reference signal is input and a frequency control word which is a target multiplication number for a target signal of the reference signal are input and the cumulative number of frequency control words is the reference A first phase detector that latches at the timing of the signal, a second phase detector that latches the target signal at the timing of the output of the reference signal, and a target signal, and the count value A third phase detector that latches at the timing of the output of the delay element; a counter (counting means) that receives the target signal and counts the number of pulses of the target signal for the delay time of the delay element; A first adder / subtractor for adding / subtracting the output of the second phase detector with the output of the second phase detector, the sum of the output of the first phase detector and the output of the counter, and the second phase detector A second adder / subtractor for addition / subtraction with an output, a multiplexer (signal switching means) for receiving the outputs of the first and second adder / subtractors and alternately outputting them, an oscillator controlled by the output of the multiplexer A frequency synthesizer is provided.

Further, in order to achieve the above object, according to the present invention, a delay element to which a reference signal is input and whose delay time is approximately 1 / n (n is an integer of 2 or more) of the period of the reference signal A delay circuit having a cascade connection, and a first phase detector which receives a frequency control word which is a target multiplication number for a target signal of a reference signal and latches the accumulated number of frequency control words at the timing of the reference signal; (N + 1) phase detectors [each of the second, third,..., (N + 1) phase detectors inputs the target signal and latches its count value at the timing of the reference signal and the output of each delay element , (N + 2) phase detector], a first adder / subtractor for adding / subtracting the output of the second phase detector and the output of the (n + 2) phase detector, and the first addition / subtraction Divide the output of the A divider for calculating the number of pulses corresponding to the delay time of the latch timing in the (n + 1) th phase detector, and addition and subtraction between the output of the first phase detector and the output of the second phase detector , The outputs of the first phase detector, the outputs of the third, fourth,..., (N + 1) th phase detectors, and the third, fourth,. , (N−1) adders / subtractors performing addition / subtraction with the pulse number corresponding to the delay time of the latch timing in the (n + 1) th phase detector [each of the third, fourth,. And (n + 1) adder / subtractor], and a multiplexer (signal switching means) for sequentially outputting the outputs of the second, third,..., (N + 1) adder / subtractor, and control by the output of the multiplexer A frequency synthesizer comprising an oscillator It is subjected.

Further, in order to achieve the above object, according to the present invention, the delay time of the delay element to which the reference signal is input and whose delay time is equal to or less than that of the reference signal is measured by the target signal. The phase signal of the reference signal is acquired by accumulating the frequency control word which is the target multiplication number for the target signal of 1, the first phase signal of the target signal, the count value of the target signal, the timing accumulation of the output of the reference signal To obtain the second phase signal of the target signal by accumulating the count value of the target signal by the timing of the output of the delay element, and the first phase difference signal as the phase signal of the reference signal. The second phase difference signal is calculated from the first phase signal of the target signal, and the second phase difference signal is calculated from the measured value of the delay time, the phase signal of the reference signal, and the second phase signal of the target signal, Oscillation frequency control method of an oscillator and controls the oscillation frequency of the oscillator using the first phase difference signal and the second phase difference signals alternately, is provided.

Further, in order to achieve the above object, according to the present invention, a delay element to which a reference signal is input and whose delay time is approximately 1 / n (n is an integer of 2 or more) of the period of the reference signal The delay time of the delay circuit formed by cascade connection is measured by the target signal, and based on the result, the delay time to the k [k is 1, 2, ..., (n-1)] stage is calculated, and the reference A phase signal of a reference signal is acquired by accumulating a frequency control word which is a target multiplication number for a target signal of the signal, a first phase signal of the target signal, a count value of the target signal, and a timing of the output of the reference signal To obtain the second, third,..., N-th phase signal of the target signal, and the count value of the target signal to the first, second,. Acquired by accumulating at the timing of the output of the delay element The first phase difference signal is calculated from the phase signal of the reference signal and the first phase signal of the target signal, and the second, third,..., N-th phase difference signals are calculated as 1, 2,. n-1) Calculated from the delay time to the delay element of the stage, the phase signal of the reference signal, and the second, third,..., n-th phase signals of the target signal, and the first to n-th A method of controlling an oscillation frequency of an oscillator, characterized in that the oscillation frequency of the oscillator is controlled by sequentially using the phase difference signal of

According to the present invention, a reference signal can be input to delay elements connected in multiple stages in cascade, and a plurality of signals with different phases generated from the output of each stage can provide a frequency synthesizer multiple times in one cycle of the reference signal. . As a result, even with a digital synthesizer operating at a low voltage and at an extremely high speed, it is possible to realize a synthesizer that can perform phase control with high accuracy and has low phase noise with low power consumption. Therefore, it is possible to provide a phase comparator suitable for advanced wireless systems using future micro CMOS devices and a PLL using the same.

FIG. 1 is a block diagram of a frequency synthesizer according to a first embodiment of this invention. FIG. 7 is a block diagram of a phase comparison unit of a frequency synthesizer according to a second embodiment of the present invention. FIG. 7 is a timing chart for explaining the circuit operation of the second embodiment of the present invention. FIG. 10 is a block diagram of a phase comparison unit of a frequency synthesizer according to a third embodiment of the present invention. The block diagram of the related art PLL circuit of an analog system. FIG. 8 is a block diagram of a related art digital PLL circuit. The block diagram of the circuit which detects the phase of output signal CKV of VCO. FIG. 7B is a timing chart explaining the operation of FIG. 7A. The block diagram of the circuit which detects the phase of reference signal FREF. FIG. 7C is a timing chart explaining the operation of FIG. 7C. FIG. 7 is a timing chart (part 1) for explaining the principle of the small phase comparison in the related art of FIG. 6; FIG. 7 is a timing chart (part 2) for explaining the principle of the small phase comparison in the related art of FIG. 6; FIG. 7 is a block diagram of a phase comparison circuit of a fractional part in the related art of FIG. 6. FIG. 11 is a timing chart for explaining the phase comparison operation in the circuit shown in FIG. 10;

Explanation of sign

1 phase comparator 2 charge pump 3 '

loop filter

105, 4 VCO
5

divider

51, 52, 53, 54, 55, 57

phase detector

61, 62, 63, 64 delay element 81 phase comparator 82 small phase comparator 83 time

digital converter

86, 87

divider

102, 118, 119

latch

103, 104 digital loop filter 107 interface circuit 108

ΔΔ modulator

122, 123 adder / subtractor

Next, embodiments of the present invention will be described in detail with reference to the drawings.
First Embodiment
FIG. 1 is a block diagram of a PLL for explaining a first embodiment of the present invention. In the following embodiments, the same components are denoted by the same reference symbols, and redundant description will be omitted as appropriate.

The reference signal FREF is a signal obtained from the reference crystal oscillator, and its phase is obtained by accumulating the frequency control word FCW indicating the target multiplication number in the phase detector 51 by the latch LT1 at each rise of the signal. . On the other hand, the phase of the output signal CKV of the VCO 105 is obtained by counting the number of rising edge clock transitions in the phase detector 52 in the latch LT2, and accumulating the count value in the latch LT3. The phase error between the phase of the detected CKV digital number and the phase of the digital number of the reference signal FREF is obtained by simply arithmetic subtraction of these two digital numbers in the adder / subtractor 122.

When the oscillation frequency of the VCO is high, the related art time-to-digital converter determined by the delay time of the inverter can not sufficiently reduce the time resolution for the CKV period. Therefore, in the present embodiment, phase comparison is performed a plurality of times within one cycle of the reference signal using the reference signal delayed by a certain constant delay element. Thus, even if the oscillation frequency of the VCO is further increased, the oscillation frequency can be controlled with high accuracy.
In the phase detector 53, the number of clock transitions of CKV is counted by the latch LT4, and the count value is accumulated by the latch LT5 using the reference signal fR1 delayed by the delay element 61. The value latched after the accumulation should be larger than the target output of the phase detector 51 by the number of counts of the CKV rising edge corresponding to the delay amount of the delay element 61. By detecting the count number corresponding to the count number with the counter 131 and performing addition / subtraction with the adder / subtractor 123, it is possible to perform phase comparison at the timing of the delayed reference signal. The two phase errors described above are synthesized by the multiplexer 126 and fed back to the oscillator via the interface circuit 107 which performs processing such as gain adjustment to the oscillator after the high speed component is removed by the digital loop filter 103. ing.

Thus, two phase comparisons are performed in one cycle of the reference signal. By preparing a plurality of reference signals delayed in this manner, it is possible to control the oscillation frequency with high accuracy and reduce the phase noise of the PLL without increasing the time resolution within one cycle of CKV.

Second Embodiment
FIG. 2 is a block diagram of a phase comparison unit of a PLL for explaining a second embodiment of the present invention. This circuit is a diagram showing in detail how to extract the count number of the rising edge of the VCO from the delay time of the delay element 61 in the phase comparison section described with reference to FIG. In this embodiment, means for generating a delayed reference signal using

delay elements

61 and 62 having a delay of about 1⁄2 period of the reference signal and a circuit for measuring the delay amount between the reference signals are added. There is. The

delay elements

61 and 62 are realized, for example, in a multistage configuration of inverter circuits, and in this embodiment, a delay of about one cycle of the reference signal is generated by two delay elements. Therefore, it is assumed that the reference signal fR1 is delayed by about 1⁄2 cycle from the original reference signal inputted, the reference signal fR2 is delayed by about 1 cycle, and each delay amount is assumed to be the same. doing. The phase detector 57 accumulates the edge of CKV by the latches LT6 and LT7 using the reference signal delayed about one cycle by the

delay elements

61 and 62, and the value latched after the accumulation is the phase detector 52. The number of CKV rising edges corresponding to the delay amount corresponding to two stages of delay elements should be larger than the output of the circuit. Therefore, the difference between these accumulated results is calculated by the adder / subtractor 124, and the result is divided by 2 in the divider 86. The division result corresponds to the CKV count number of one delay element stage.

The phase RR01 of the reference signal FREF is obtained by accumulating the frequency control word FCW indicating the target multiplication number in the phase detector 51 at each rise of the signal. The phase VV01 of the oscillator output signal CKV is obtained by accumulating in the phase detector 52 the number of clock transitions of its rising edge. The phase error between the detected VCO and the reference signal FREF is obtained by simple arithmetic subtraction of the two digital values described above in the adder / subtractor 122.

The phase detector 53 accumulates the edge of CKV using the reference signal fR1 delayed by the delay element 61. The post-accumulation latched digital phase value VV 02 should be larger than the target output of the phase detector 51 by the number of counts of the CKV rising edge corresponding to the delay amount of the delay element 61. The count number (Φ0) corresponding to the count number is calculated as follows. The phase detector 57 accumulates the number of CKV clocks with the delay element 61 of FREF with the reference signal fR2 delayed by 62 minutes to detect the phase ΦV00 of CKV. This and the output 01V01 of the phase detector 52 are added / subtracted by the adder / subtractor 124, and the result is divided by 2 by the divider 86 to calculate the count number 数 0 of CKV for one delay element stage. The phase error in the reference signal fR1 is calculated by adding / subtracting the sum of the output (ΦR01) of the phase detector 51 and the output (Φ0) of the divider 86 and the output (ΦV02) of the phase detector 53 with an adder / subtractor 123 It is obtained. These two phase errors are synthesized by the multiplexer 126, and after the high speed component is removed by the digital filter, are fed back to the oscillator through an interface unit that performs processing such as gain adjustment to the oscillator.

Thus, two phase comparisons are performed in one cycle of the reference signal. If a plurality of reference signals delayed in this way are prepared, frequency control with high accuracy becomes possible and phase noise of the PLL can be reduced without increasing the time resolution within one cycle of CKV.

FIG. 3 is a time chart showing the operation. Since the output of the phase detector 57 accumulates the edge of the output signal CKV of the VCO for the time shown in the figure with respect to the output of the phase detector 52, the difference between the accumulated values is the delay element 2 It corresponds to the stage. By dividing this by 2, it is possible to calculate the number of counts for one delay element stage. As described above, the delay amount can be accurately estimated by calculating the count number using a plurality of delay elements.

Third Embodiment
FIG. 4 is a block diagram of a phase comparison unit of a PLL for explaining the third embodiment of the present invention. In this embodiment, the reference signals fR1-fR4 delayed using delay elements 61-64 having a delay time of about 1/4 period of the reference signal are generated, and the phase detector 57 determines the number of clock transitions of CKV by fR4. Accumulate. The accumulated value and the output of the phase detector 52 are added / subtracted to calculate the number of clock transitions of CKV for about one cycle of the reference signal, and the calculated value is divided by the divisor 2

divider

86, 87 The number of CKV clock transitions in about 1/4 period-3/4 period of the reference signal is calculated.

The phase error when there is no delay of the reference signal is calculated by directly comparing the outputs of the phase detector 51 of the reference signal and the phase detector 52 of CKV. The phase error at the delay timing of 1⁄4 cycle of the reference signal is a value obtained by calculating the CKV count number for the delay of 4 stages of delay elements as the output difference between phase detector 51 and phase detector 53. It is obtained by adding the value divided by.

The phase error at the timing of delaying the reference signal by a half cycle thereof is similarly to the phase error between the output of the phase detector 51 of the reference signal and the output of the phase detector 54 of CKV. It is calculated by adding the CKV counts for two stages.

The phase error at the timing when the reference signal is delayed by 3⁄4 period is obtained by subtracting the CKV count number increased by 3 stages of delay elements obtained by the phase detector 55 from the output of the phase detector 51, and further delay elements It is obtained by adding 1/2 and 1/4 of the CKV count numbers for four stages.
These results can be synthesized by the multiplexer 126, and the output can control the oscillator to perform frequency control with high accuracy.

As mentioned above, although preferable embodiment was described, this invention is not limited to these embodiment, A suitable change is possible in the range which does not deviate from the summary of this invention. For example, in the embodiment, the delay amount is set to 1⁄2 cycle or 1⁄4 cycle. However, the present invention is not limited to this, and may be set to 1⁄3 cycle or 1⁄5 cycle. Although four delay elements are stacked in the embodiment, the present invention is not limited to this, and more or less stages may be connected.
This application claims priority based on Japanese Patent Application No. 2008-089465 filed on March 31, 2008, the entire disclosure of which is incorporated herein.

The present invention detects a phase difference between an oscillation clock of a voltage controlled oscillator incorporated in a phase locked loop (PLL) and a reference clock as a digital signal, and outputs an output from the phase comparator. The present invention can be applied to a frequency synthesizer having a voltage controlled oscillator controlled as described above and a method of manufacturing an oscillation frequency of the oscillator.

Claims

Delay means into which the reference signal is input;
First phase detection means for inputting a frequency control word which is a target multiplication number for a target signal of a reference signal and latching the accumulated number of frequency control words at the timing of the reference signal;
Second phase detection means for inputting a target signal and latching its count value at the timing of output of the reference signal;
Third phase detection means for inputting a target signal and latching its count value at the timing of the output of the delay means;
A counting unit which receives a target signal and counts the number of pulses of the target signal for the delay time of the delay unit;
First addition and subtraction means for performing addition and subtraction between the output of the first phase detection means and the output of the second phase detection means;
Second addition / subtraction means for performing addition / subtraction between the sum of the output of the first phase detection means, the output of the counting means and the output of the second phase detection means;
Signal switching means which receives the outputs of the first and second addition and subtraction means and alternately outputs them;
Oscillating means controlled by the output of the signal switching means;
Frequency synthesizer with.
A delay circuit in which n stages of delay means in which a reference signal is input and whose delay time is approximately 1 / n (n is an integer greater than or equal to 2) of the period of the reference signal are connected in tandem;
First phase detection means for inputting a frequency control word which is a target multiplication number for a target signal of a reference signal and latching the accumulated number of frequency control words at the timing of the reference signal;
(N + 1) phase detection means (each phase detection means is a second, third,..., (N + 1) phase delay means for inputting the target signal and latching its count value at the timing of the reference signal and the output of each delay means , (N + 2) phase detection means],
First addition / subtraction means for performing addition / subtraction between the output of the second phase detection means and the output of the (n + 2) th phase detection means;
A division unit that divides the output of the first addition / subtraction unit and calculates the number of pulses corresponding to the delay time of the latch timing in the third to (n + 1) th phase detection units;
Second addition / subtraction means for performing addition / subtraction between the output of the first phase detection means and the output of the second phase detection means;
The output of the first phase detection means, the output of the third, fourth,..., (N + 1) th phase detection means, and the third, fourth,. (N-1) addition / subtraction means performing addition / subtraction with the number of pulses corresponding to the delay time of the latch timing in the phase detection means of [the third, fourth,..., (N + 1) th addition / subtraction As a means],
Signal switching means for receiving the outputs of the second, third,..., (N + 1) th addition / subtraction means and sequentially outputting them;
Oscillating means controlled by the output of the signal switching means;
Frequency synthesizer with.
The division means performs division by the number of delay means stages, and calculates the number of target signals corresponding to the delay time of the delay means up to the k [k is 1, 2, ..., (n-1)] stages. The frequency synthesizer according to claim 2, characterized in that
The frequency synthesizer according to claim 2 or 3, wherein the number of stages of the delay means is a multiple of 2, and the division is performed by bit shift.
Measuring a delay time of a delay element to which a reference signal is input and whose delay time is equal to or less than the period of the reference signal, using a target signal,
Obtaining a phase signal of the reference signal by accumulating a frequency control word which is a target multiplication number for the target signal of the reference signal;
Obtaining a first phase signal of the target signal by accumulating the count value of the target signal at the timing of the output of the reference signal;
Obtaining a second phase signal of the target signal by accumulating the count value of the target signal at the output of the delay element;
Calculating a first phase difference signal from the phase signal of the reference signal and the first phase signal of the target signal;
A second phase difference signal is calculated from the measured value of the delay time, the phase signal of the reference signal, and the second phase signal of the target signal,
A method of controlling an oscillation frequency of an oscillator, wherein the oscillation frequency of an oscillator is controlled by alternately using the first phase difference signal and the second phase difference signal.
Measure the delay time of a delay circuit consisting of n stages of cascade-connected delay elements whose delay time is approximately 1 / n (n is an integer of 2 or more) of the cycle of the reference signal. Then, based on the result, the delay time to the k [k is 1, 2, ..., (n-1)] stage is calculated,
Obtaining a phase signal of the reference signal by accumulating a frequency control word which is a target multiplication number for the target signal of the reference signal;
Obtaining a first phase signal of the target signal by accumulating the count value of the target signal at the timing of the output of the reference signal,
The second, third,..., N-th phase signal of the target signal is accumulated with the count value of the target signal at the timing of the output of the delay element of the first, second,. Get by
Calculating a first phase difference signal from the phase signal of the reference signal and the first phase signal of the target signal;
The second, third,..., N-th phase difference signal is represented by the delay time until the first, second,..., (N−1) th delay element, the phase signal of the reference signal, and the second of the target signal Calculated from the third to n th phase signals,
A method of controlling an oscillation frequency of an oscillator, wherein an oscillation frequency of an oscillator is controlled by sequentially using the first to n-th phase difference signals.