JP2012073169A - On-chip jitter data acquisition circuit, and jitter measurement device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an on-chip jitter data acquisition circuit that can perform jitter measurement without requiring a high-frequency probe.SOLUTION: An on-chip jitter data acquisition circuit 1 comprises: a variable delay part 10 that delays a clock signal with any one of plural delay amounts that can be selected by a delay amount selection signal; a phase comparison signal generation part 20 for generating a phase comparison signal by comparing the phase of the clock signal and the phase of the clock signal that has been delayed by the variable delay part; and a phase comparison signal acquisition part 30 for acquiring the phase comparison signal during a predetermined period.

Description

  The present invention relates to an on-chip jitter data acquisition circuit, a jitter measurement device, and a method thereof. Specifically, the present invention relates to an on-chip jitter data acquisition circuit, a jitter measurement device, and a method thereof that facilitate testing of a clock signal generated inside a semiconductor device such as a clock signal generated by a PLL circuit.

  In recent years, there is a concern about an increase in test cost, that is, test cost, in the manufacturing cost of LSI (Large Scale Integration) mounted on a semiconductor device. For this reason, in order to reduce the test cost, research and development relating to test facilitating technology has been actively conducted. Various general-purpose test facilitating techniques such as a scan path method and a signature analysis method have been proposed for digital circuit test facilitating techniques. However, analog circuit testability technology is still in the development stage. In particular, a PLL (Phase Locked Loop) is indispensable even in a digital rich LSI such as a microprocessor, and thus there is a great demand for easy testability. For this reason, many researches and developments have been made on circuits and methods for easily measuring the jitter of a clock signal generated by a PLL mounted on a semiconductor device with high accuracy. In other analog circuits as well, due to progress in miniaturization of semiconductor processes and improvements in circuit systems, for example, in digital-to-analog converters (ADC), jitter determines the quality of ADC performance. It is becoming one of the most important indicators. In this way, jitter measurement may become one of the most important test items in the future in the test process in the manufacturing process of an LSI circuit mounted on a semiconductor device.

  A jitter measurement circuit in the prior art employs a reference clock signal (see Non-Patent Documents 1 and 2). The reference clock signal is a reference signal when measuring jitter of a clock signal generated in an internal circuit of a semiconductor device such as a PLL circuit, and it is considered desirable to use a clock signal having no jitter. Yes. However, it is generally difficult to generate a clock signal having no jitter inside the semiconductor device 200. Therefore, as shown in FIG. 18, the reference clock signal is given to the jitter measurement circuit from the outside of the semiconductor device 200. When the reference clock signal is supplied from the outside of the semiconductor device 200, the reference clock signal needs to be input by the high-frequency probe 210 that can input a high-frequency signal. However, since a high-frequency probe is generally expensive, using a high-frequency probe to input a reference clock signal to an LSI causes an increase in test cost. Further, jitter may accumulate in the process of propagating the clock from the input pad to the jitter measurement circuit. For this reason, as shown in Non-Patent Document 3, it is proposed to mount a jitter data measurement circuit that does not use a reference clock signal in the semiconductor device 300. However, the jitter data measurement circuit proposed in Non-Patent Document 3 does not use a reference clock signal, and it is necessary to measure an output signal (High-speed output) having a high frequency as shown in FIG. A high frequency probe 310 is required.

K. Jenkins, et al., “On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Network,” IEEE 2007 Custom Integrated Circuits Conference (CICC)., Pp. 157-160, Sept. 2007. K. Jenkins, et al., “A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 185-188, Jun. 2009. M. Ishida, et al., “A Programmable On-Chip Picosecond Jitter-Measurement Circuit without a Reference-Clock Input,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) pp. 512-513, Feb. 2005.

  As described above, the conventional jitter measurement circuit requires a high-frequency probe to measure jitter, and thus has a problem that the test cost in the manufacturing process increases.

  Therefore, an object of the present invention is to provide an on-chip jitter data acquisition circuit that can solve the above-described problems.

  It is another object of the present invention to provide an on-chip jitter data acquisition circuit capable of measuring jitter without requiring a high frequency probe.

  To achieve the above object, an on-chip jitter data acquisition circuit according to the present invention is an on-chip jitter data acquisition circuit that acquires data relating to jitter of a clock signal, and the clock signal can be selected by a delay amount selection signal. Phase comparison that generates a phase comparison signal by comparing the phase of the variable delay unit that is delayed by one of a plurality of delay amounts, the phase of the clock signal, and the phase of the clock signal delayed by the variable delay unit It has a signal generation part and a phase comparison signal acquisition part which acquires a phase comparison signal over a predetermined period.

  Furthermore, in the on-chip jitter data acquisition circuit according to the present invention, the phase comparison signal is preferably a pulse signal indicating a comparison result, and the phase comparison signal acquisition unit is preferably a counter circuit that counts the number of pulse signals. By adopting such a configuration, the on-chip jitter data acquisition circuit according to the present invention can be realized with a relatively small circuit scale.

  Furthermore, in the on-chip jitter data acquisition circuit according to the present invention, the variable delay unit preferably further includes an offset delay circuit that delays the clock signal by a given offset delay amount. By adopting such a configuration, the on-chip jitter data acquisition circuit according to the present invention can reduce the correlation between the clock signal and the delayed clock signal and make both signals independent of each other.

  Further, the on-chip jitter data acquisition circuit according to the present invention is configured such that in the normal mode for acquiring jitter data, the clock signal is input to the variable delay unit, and in the calibration mode for calibrating the delay amount of the variable delay circuit, the variable delay unit is used. In the normal mode, the phase selection signal is input to the phase comparison signal acquisition unit, and in the calibration mode, the variable delay unit and the mode selection multiplexer input the inverted signal of the delayed clock signal to the variable delay unit. It is preferable to further include an output selection multiplexer that inputs the oscillation signal of the configured ring oscillation unit to the phase comparison signal acquisition unit. By adopting such a configuration, the on-chip jitter data acquisition circuit according to the present invention can accurately know the delay amount in the variable delay unit, and can realize jitter measurement with higher accuracy.

  Furthermore, the on-chip jitter data acquisition circuit according to the present invention preferably has two or more phase comparison signal acquisition units. By adopting such a configuration, the on-chip jitter data acquisition circuit according to the present invention can perform skew measurement in addition to jitter measurement.

  Further, the jitter measuring method according to the present invention is a method for measuring jitter of a clock signal generated on-chip, and includes a step of generating a delayed clock signal by delaying the clock signal by a predetermined delay amount; The step of comparing the clock signal with the delayed clock signal and generating a phase comparison signal based on the comparison result, the step of acquiring the phase comparison signal over a predetermined period, and the acquired phase comparison signal And processing to create a histogram.

  In the on-chip jitter data acquisition circuit according to the present invention, it is possible to perform jitter measurement without using a high frequency probe by adopting the above configuration.

It is a figure which shows an example of the on-chip jitter data acquisition circuit based on this invention. FIG. 2 is a diagram illustrating an example of a circuit of a variable delay unit of the on-chip jitter data acquisition circuit illustrated in FIG. 1. It is a figure which shows an example of the timing chart of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows the example of the histogram which can be produced | generated from the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows an example of the flow of the jitter measuring method which concerns on this invention. It is a figure which shows the comparison with the conventional jitter measurement and the jitter measurement which concerns on this invention. It is a figure which shows an example of the simulation result of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows the other example of the simulation result of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows the other example of the simulation result of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows the other example of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows the comparison of the conventional jitter data and the jitter data based on this invention. It is a figure which shows the other example of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows the other example of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows an example of TDC employ | adopted as this invention. It is a figure which shows the other example of the flow of the jitter measuring method which concerns on this invention. It is a figure which shows the other example of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows the other example of the on-chip jitter data acquisition circuit based on this invention. It is a figure which shows an example of the prior art of a jitter measurement circuit. It is a figure which shows the other example of the prior art of a jitter measurement circuit.

  Hereinafter, an on-chip jitter data acquisition circuit, a jitter measurement device, and a method thereof according to the present invention will be described in detail with reference to the accompanying drawings. In each drawing, components having the same or similar functions are denoted by the same or similar reference numerals. Therefore, a component having the same or similar function as the component described above may not be described again.

  An example of an on-chip jitter data acquisition circuit according to the present invention and an example of the method will be described with reference to FIGS. FIG. 1 shows an example of an on-chip jitter data acquisition circuit according to the present invention. As shown in FIG. 1, the on-chip jitter data acquisition circuit 1 formed on the semiconductor device 100 includes two input terminals, a CLKin terminal and a SELdly terminal, an output terminal CNTout, a variable delay unit 10, and a phase comparison. It has the signal generation part 20 and the phase comparison signal acquisition part 30 which is a counter circuit in this embodiment. Further, the phase comparison signal generation unit 20 includes a latch circuit 21 and a two-input AND element 23. In the on-chip jitter data acquisition circuit 1, the phase comparison signal generator 20 compares the clock signal input to the CLKin terminal with a signal obtained by delaying the clock signal by a predetermined delay amount, and a pulse signal indicating the comparison result Is generated. The phase comparison signal acquisition unit 30 acquires the pulse signal generated by the phase comparison signal generation unit 20 and counts the number of pulse signals. With such a configuration, the on-chip jitter data acquisition circuit 1 can measure the jitter of the clock signal input to the CLKin terminal at an arbitrary frequency without using a high-frequency probe.

  A clock signal generated by a circuit such as a PLL circuit formed inside the semiconductor device 100 is input to the CLKin terminal. This clock signal ideally has a constant pulse width and becomes a plurality of pulse signals input at a constant cycle. However, a clock signal generated by a circuit formed in the semiconductor device 100 is jitter (Jitter) depending on various operating conditions such as manufacturing conditions, temperature conditions, and operating states of other circuits formed in the semiconductor device 100. ). For this reason, a plurality of pulse signals with different periods and pulse widths are actually input to the CLKin terminal due to the occurrence of time shifts and fluctuations in each pulse signal due to jitter. Will be.

  A signal for determining the delay amount of the variable delay unit 10 is input to the SELdly terminal from the inside or the outside of the semiconductor device 100. The clock signal input to the CLKin terminal is input to the variable delay unit 10, delayed by a delay amount determined based on the signal input to the SELdly terminal, and output. A clock signal input to the CLKin terminal is input to the D input of the latch circuit 21. On the other hand, the clock signal input to the CLKin terminal is input to the CK terminal after being delayed by a predetermined delay amount in the variable delay unit 10. Therefore, a signal delayed by a predetermined delay amount from the clock signal input to the D terminal is input to the CK terminal of the latch circuit 21. The delay amount given by the variable delay unit 10 can be defined to an arbitrary value. For example, a delay amount from 0.5 times to 1.5 times the period T of the clock signal may be given.

  The latch circuit 21 has a function of holding the signal input to the D terminal and outputting it to the Q terminal at the rising edge of the signal input to the CK terminal. For example, if the input signal of the D terminal at the rising edge of the signal input to the CK terminal is at the low level, the low level is output to the Q terminal of the latch circuit 21. Further, if the input signal of the D terminal at the rising edge of the signal input to the CK terminal is at a high level, the high level is output to the Q terminal of the latch circuit 21. The latch circuit 21 is generally also called a D flip-flop circuit.

  The 2-input AND element 23 outputs a logical product of the output signal from the Q terminal of the latch circuit 21 input to one input terminal and the clock signal input to the other input terminal. For this reason, when the output signal from the Q terminal of the latch circuit 21 is at the low level, the signal output from the output terminal of the two-input AND element 23 is always at the low level. On the other hand, when the output signal from the Q terminal of the latch circuit 21 is at a high level, the signal output from the output terminal of the 2-input AND element 23 changes according to the input state of the clock signal. That is, when the clock signal is at high level, the signal output from the output terminal of the 2-input AND element 23 is at high level, and when the clock signal is at low level, the output terminal of the 2-input AND element 23 is output. The signal output from becomes a low level. As a result, when the output signal from the Q terminal of the latch circuit 21 is at a high level, the pulse width defined by the rising edge of the signal output from the Q terminal of the latch circuit 21 and the falling edge of the clock signal is set. The pulse signal is output from the output terminal of the 2-input AND element 23. In this circuit, a signal from the CLKin terminal is input to one input of the 2-input AND element 23, but a signal output from the variable delay unit 10 can be input instead of this signal.

  The pulse signal output from the output terminal of the 2-input AND element 23 is input to the input terminal of the counter circuit 30. The counter circuit 30 counts the pulse signal input to the input terminal and outputs it as an n-bit digital signal to the outside of the semiconductor device 10 via the CNTout terminal. Here, n is an integer of 1 or more.

  FIG. 2 shows an example of the circuit configuration of the variable delay unit 10. As shown in FIG. 2, the variable delay unit 10 can include a coarse adjustment delay unit 11 and a fine adjustment delay unit 14. The coarse adjustment delay unit 11 includes a plurality of delay elements 12a to 12n and a multiplexer 13 that selectively outputs output terminals of the respective delay elements. The fine adjustment delay unit 14 is connected to a plurality of delay elements 15a to 15c, capacitors 16a and 16b having one terminal connected to an output terminal of each delay element, and the other terminals of the capacitors 16a and 16b. Switching elements 17a and 17b are included. The capacitors 16a and 16b can be configured by forming two electrode plates with a metal wiring layer and using an insulating layer formed between both metal wiring layers as a dielectric. The switching elements 17a and 17b can be formed of nMOS transistors, but may be formed of other switching elements such as pMOS transistors or varactors. The number of delay elements 12 and 15 can be set to an appropriate number based on the delay amount of each delay element and the period of the clock signal to be measured. For example, a delay amount from 0 to 1 times the period T of the clock signal can be given. Further, a delay amount from 0.5 to 1.5 times the period T of the clock signal may be given.

  Hereinafter, an example of a method for measuring jitter of a clock signal using the on-chip jitter data acquisition circuit 1 will be described with reference to FIGS. FIG. 3 shows an example of a timing chart of the on-chip jitter data acquisition circuit 1. The pulse signal sequence indicated by “CLK” is a clock signal to be measured that is generated by a PLL circuit or the like and is input to the CLKin terminal of the on-chip jitter data acquisition circuit 1, and includes eight pulse signals CK1 to CK8. The pulse signal is shown. The rising edge and falling edge of the CLK signal actually have a slope with respect to the time axis due to the load capacity and the like, but here, for simplicity of explanation, the edge is perpendicular to the time axis. Indicated. A rising edge and a falling edge indicated by broken lines represent edges when there is no jitter. On the other hand, rising edges and falling edges indicated by solid lines indicate edges that have transitioned due to jitter. In FIG. 3, CK1, CK4, and CK6 transition in a direction in which the pulse signal rises early due to jitter, and CK2, CK3, CK5, and CK8 transition in a direction in which the pulse signal rises late due to jitter. The pulse signal sequence indicated by “CLK with 0.95T delay” is a signal obtained by delaying the pulse signal sequence indicated by “CLK” by a delay amount 0.95 times the period T of the clock signal in the variable delay unit 10. Is a column. Similarly, pulse signal sequences indicated by “CLK with 1.00T delay” and “CLK with 1.05T delay” are respectively 1.00 times and 1.05 times the period T of the clock signal in the variable delay unit 10. It is a signal sequence delayed by the delay amount.

  For the signal sequence indicated by “Output from 2-AND with 0.95T delay”, the signal sequence indicated by “CLK” is input to the D terminal of the latch circuit 21, and the signal sequence indicated by “CLK with 0.95T delay” is input. A signal string output to the output terminal of the 2-input AND element 23 when input to the CK terminal of the latch circuit 21 is shown. Assuming that there is no jitter, the signal sequence indicated by “Output from 2-AND with 0.95T delay” does not generate one pulse signal. When there is no jitter, all the rising edges of “Output from 2-AND with 0.95T delay” input to the CK terminal of the latch circuit 21 are “CLK” pulse signals input to the D terminal of the latch circuit 21. This is because it occurs at a low level. However, in the example shown in FIG. 3, the added value of the transition amounts of the pulse signals C3 and C4 and the added value of the transition amounts of the pulse signals C5 and C6 are each from 0.05T which is the delay difference between both pulses. Therefore, two pulse signals are generated in “Output from 2-AND with 0.95T delay”.

  For the signal sequence indicated by “Output from 2-AND with 1.00T delay”, the signal sequence indicated by “CLK” is input to the D terminal of the latch circuit 21, and the signal sequence indicated by “CLK with 1.00T delay” is input. A signal string output to the output terminal of the 2-input AND element 23 when input to the CK terminal of the latch circuit 21 is shown. Here, one pulse signal is added to “Output from 2-AND with 0.95T delay” due to the effect that the transition amount of the pulse signal C2 is slightly larger than the transition amount of the pulse signal C3, and three pulse signals are generated. .

  For the signal sequence indicated by “Output from 2-AND with 1.05T delay”, the signal sequence indicated by “CLK” is input to the D terminal of the latch circuit 21, and the signal sequence indicated by “CLK with 1.05T delay” is input. A signal string output to the output terminal of the 2-input AND element 23 when input to the CK terminal of the latch circuit 21 is shown. Assuming that there is no jitter, eight pulse signals corresponding to all pulse signals indicated by “CLK” are generated from the signal sequence indicated by “Output from 2-AND with 1.05T delay”. When there is no jitter, all the rising edges of “Output from 2-AND with 1.05T delay” input to the CK terminal of the latch circuit 21 correspond to the “CLK” pulse signal input to the D terminal of the latch circuit 21. This is because it occurs at a high level. However, in this example, since the addition amount of the transition amounts of the pulse signals C1 and C2 is larger than the delay difference 0.05T of both pulses, a pulse signal is generated in “Output from 2-AND with 1.05T delay”. There is one missing clock signal.

  As described above, the on-chip jitter data acquisition circuit 1 uses the latch circuit 21 and the two-input AND element for the clock signal of the PLL circuit and the rising edge of the delayed clock signal obtained by delaying the clock signal by an appropriate delay amount. When the phase of the rising edge of the clock signal is advanced, the pulse signal is output to the counter circuit 30. Here, a plurality of delay amounts for delaying the clock signal are set by the variable delay unit 10 at appropriate delay intervals. The on-chip jitter data acquisition circuit 1 counts the number of generated pulse signals by the counter circuit 30 over a predetermined period for each set delay amount. For example, the on-chip jitter data acquisition circuit 1 counts the number of pulse signals for each delay amount obtained by dividing the period T of the clock signal by 100. When the semiconductor device 100 is tested by the semiconductor test device 500, the number of pulse signals counted over a predetermined period for each delay amount is read out via a probe aligned with the CNTout terminal. Are stored in the storage devices 510 included in the semiconductor test apparatus 500. Based on the number of pulse signals stored in the storage device 510, a central processing unit (CPU, Central Processing Unit) 520 included in the semiconductor test device 500 generates a histogram that statistically represents the jitter amount of the clock signal.

  FIG. 4 illustrates two histograms created in this way. In both of these histograms, the vertical axis indicates the number of pulse signals counted by the counter circuit 30, and the horizontal axis indicates the delay amount delayed by the variable delay unit 10. The histogram shown in FIG. 4A is an example with relatively small jitter, and the histogram shown in FIG. 4B is an example with relatively large jitter. Comparing the histograms shown in FIGS. 4A and 4B, the histogram shown in FIG. 4A has an increase in the number of pulse signals with respect to the increase in the delay amount, compared to the histogram shown in FIG. 4B. It can be seen that is steep. When the jitter is small, the probability of occurrence or non-occurrence of a pulse signal due to jitter as shown in FIG. 3 is low, so that the increase in the number of pulse signals for increasing the delay amount becomes steep. On the other hand, when the jitter is large, the probability of occurrence or non-occurrence of the pulse signal due to the jitter increases, and the increase in the number of pulse signals that increases the delay amount becomes moderate. In the present invention, the non-defective / defective product can be determined at the time of shipment by using the histogram shown in FIG. For example, when the rising edge of the histogram is gentler than a predetermined inclination, it can be determined as a defective product, and when the rising edge of the histogram is steeper than the predetermined inclination, it can be determined as a non-defective product.

  FIG. 5 shows a flowchart of a method for measuring the jitter of a clock signal using the on-chip jitter data acquisition circuit 1. In step 101, the CPU 520 inputs a clock signal such as a PLL circuit to the CLKin terminal of the on-chip jitter data acquisition circuit 1. In step 102, the CPU 520 determines a delay amount for delaying the clock signal. In step 103, the phase comparison signal generation unit 20 compares the phases of the clock signal and the signal obtained by delaying the clock signal, and outputs a pulse signal based on the comparison result. In step 104, the counter circuit 30 counts the number of output pulse signals over a predetermined period, and the CPU 520 stores the count number in the storage device 510. In step 105, the CPU 520 determines whether or not to execute the processing in steps 101 to 104 with all predetermined delay amounts. If the processing has not ended, the processing of steps 101 to 104 is executed again. If the processing has been completed, in step 106, the CPU 520 appropriately arranges the stored count numbers to generate a histogram.

  As described above, the on-chip jitter data acquisition circuit 1 can measure the jitter of a clock signal of a PLL circuit or the like formed inside the semiconductor device 100 without inputting a reference clock from the outside of the semiconductor device 100. it can. In addition, the on-chip jitter data acquisition circuit 1 employs a method in which the CPU 520 statistically processes the result of the counter circuit 30 counting the number of pulse signals generated by the phase comparison signal generation unit 20 over a predetermined period. To do. In this method, by adopting a statistical method, the on-chip jitter data acquisition circuit 1 statistically measures jitter without directly measuring jitter having a size of several [ps] to several tens [ps]. Can be measured automatically. For this reason, the on-chip jitter data acquisition circuit 1 does not need to directly measure jitter and does not need to detect a signal output at a high-speed clock signal period such as a PLL circuit. Therefore, when the on-chip jitter data acquisition circuit 1 is employed to measure jitter, it is not necessary to input a high-speed input signal to the semiconductor device 100, and it is necessary to detect a high-speed output signal from the semiconductor device 100. Nor. For this reason, it is not necessary to use a high-frequency probe in jitter measurement, and an increase in test cost can be suppressed.

  Further, as shown in FIG. 1, the on-chip jitter data acquisition circuit 1 includes a variable delay unit 10, a phase comparison signal generation unit 20, and a counter circuit 30. As shown in FIG. 2, the variable delay unit includes delay elements 12 a to 12 n and a multiplexer 13, and the phase comparison signal acquisition unit includes a latch circuit 21 and a two-input AND element 23. Further, as will be apparent to those skilled in the art, the counter circuit 30 can be composed of a plurality of latch circuits, exclusive OR elements, and the like. For this reason, the on-chip jitter data acquisition circuit 1 has an advantage that it can be realized with a comparatively small circuit scale.

  Furthermore, the method of measuring the jitter of the clock signal using the on-chip jitter data acquisition circuit 1 is more variable than the conventional method of measuring the jitter of the clock signal by comparing with the reference clock signal. This has the advantageous effect that the time resolution of the delay element is relaxed. This effect will be described in detail below with reference to FIGS. FIG. 6 shows a difference between a conventional method using a reference clock signal and a method using the on-chip jitter data acquisition circuit 1. A conventional method is shown on the left side of FIG. 6, and a method of using the on-chip jitter data acquisition circuit 1 is shown on the right side of FIG. FIG. 6A conceptually shows the trigger edge in both methods. In the conventional method described on the left side, a plurality of reference clock signals whose delay amounts are changed are indicated by broken line arrows for one clock signal indicated by a solid line. As described above, in the conventional method, the edge of the clock signal to be measured has a certain degree of (dispersion), but the trigger edge of the reference clock signal does not have (dispersion) and is relative to the time axis. It becomes vertical. For this reason, when a histogram is generated by changing the delay amount of the reference clock, the distribution of the cumulative distribution function (CDF) depends only on the clock signal to be measured. It is assumed that the standard deviation in this case is σ and the distribution is as shown in FIG. In this case, it is assumed that the probability density function (PDF) has the distribution shown in FIG.

Next, a method of using the on-chip jitter data acquisition circuit 1 will be considered. As shown on the right side of FIG. 6 (a), in the method using the on-chip jitter data acquisition circuit 1, the delay clock signal indicated by the broken line also has a certain amount of edge (like the clock signal to be measured). Dispersion). As described above, the delayed clock signal to be compared with the clock signal to be measured is a pulse signal advanced by one cycle from the clock signal to be measured. Here, it is assumed that the probability that jitter occurs in one pulse signal forming the clock signal and the probability that jitter occurs in the pulse signal are completely independent. If this assumption holds, the variance of the cumulative distribution function depends on the clock signal to be measured and the delayed clock signal that is independent of the clock signal, so the standard deviation is
Double. That is, in the method using the on-chip jitter data acquisition circuit 1, the standard deviation is
become. As a result, as shown on the left side of FIG. 6B, the CDF of the method using the on-chip jitter data acquisition circuit 1 has a larger dispersion than the CDF of the conventional method shown by the broken line. In FIG. 6 (c), PDFs of both methods are shown. Again, the broken line shows the PDF of the conventional method, and the solid line shows the PDF of the method using the on-chip jitter data acquisition circuit 1.

  As described above, in the method according to the present invention, the standard deviation of the cumulative distribution function can be increased by using a signal obtained by delaying a clock signal whose edge has (dispersion) without using the reference clock signal. It is possible to relax the demand for time resolution. FIG. 7 shows a SPICE (Simulation Program with Integrated Circuit Emphasis) simulation result of jitter measurement when the conventional method is used and when the on-chip jitter data acquisition circuit 1 is used. In both simulations, the period of the clock signal to be measured and the reference clock signal is 500 [ps]. The jitter is generated by adding legal white Gaussian noise (AWGN) to the reference clock signal. FIG. 7A shows a simulation result by a conventional method. Here, a clock signal having jitter is input to the D terminal of the latch circuit 21, and a clock signal having no jitter is input to the variable delay unit 10. FIG. 7B shows a simulation result by a method using the on-chip jitter data acquisition circuit 1. Here, a clock signal having jitter is input to both the D terminal of the latch circuit 21 and the variable delay unit 10. As shown in the simulation result, the simulation result of the method using the on-chip jitter data acquisition circuit 1 shown in FIG. 7B is more distributed than the simulation result of the conventional method shown in FIG. Is getting bigger. From these results, it is clear that the method using the on-chip jitter data acquisition circuit 1 can alleviate the demand for time resolution in jitter measurement. Generally, as CMOS technology miniaturization technology advances, it tends to be difficult to improve time resolution due to device variations. For this reason, the on-chip jitter data acquisition circuit 1 can alleviate the demand for time resolution in jitter measurement, and thus has a high affinity with CMOS technology that is increasingly miniaturized, and its effectiveness increases as the miniaturization progresses. You can say that.

  FIG. 8 shows a SPICE simulation result of jitter measurement when the conventional method is used as in FIG. 7 and when the on-chip jitter data acquisition circuit 1 is used. Here, the dispersion when the magnitude of jitter is changed is conceptually shown. As apparent from FIG. 8, in the simulation result of the method using the on-chip jitter data acquisition circuit 1, the increase in dispersion accompanying the change in the magnitude of jitter is larger than the simulation result of the conventional method. From this, it becomes clear that the method using the on-chip jitter data acquisition circuit 1 can alleviate the demand for time resolution in jitter measurement as the jitter increases. It will also be appreciated that the ratio is greater than conventional methods.

  FIG. 9 shows an example of a SPICE simulation result of the on-chip jitter data acquisition circuit 1. Here, the process uses a 180 [nm] CMOS process, VDD is 1.8 [V], the amplitude of AWGN is 0.8 [V], and the frequency of the clock signal is 2 [GHz]. ]. Since the sweep time of the graph is 100 [ns], the maximum count number is 200 times.

  With reference to FIGS. 10 and 11, another example of the on-chip jitter data acquisition circuit according to the present invention will be described. FIG. 10 shows another example of the on-chip jitter data acquisition circuit according to the present invention. As shown in FIG. 10, the on-chip jitter data acquisition circuit 2 formed on the semiconductor device 100 includes two input terminals, a CLKin terminal and a SELdly terminal, an output terminal CNTout, a variable delay unit 10, and a phase comparison. In addition to the signal generation unit 20 and the phase comparison signal acquisition unit 30, an offset delay circuit 17 is provided. The offset delay circuit 17 can have a delay amount of several times to 10 times the period of the clock signal input to the CLKin terminal. Preferably, the delay amount of the offset delay circuit 17 can have a cycle that is substantially an integral multiple of the cycle of the clock signal input to the CLKin terminal. The on-chip jitter data acquisition circuit 2 includes an offset delay circuit 17 having a delay amount that is several times to 10 times the period of the clock signal, so that the clock signal input to the D terminal of the latch circuit 21 and the CK terminal It is possible to make the correlation with the delayed clock signal input to the low and independent relationship.

  With reference to FIG. 11, the concept of reducing the correlation with the clock signal by providing the offset delay circuit 17 will be described. FIG. 11A shows an autocorrelation function of a typical clock signal. A position indicated by a one-dot chain line indicates a correlation with a signal separated by one cycle, and a position indicated by a broken line indicates a correlation with a signal separated by four cycles. From this, the effect of providing the offset delay circuit 17 and increasing the delay amount of the delayed clock signal becomes statistically clear. That is, it will be understood that the correlation between the clock signal to be measured and the delayed clock signal is reduced by increasing the delay amount of the delayed clock signal by the offset delay circuit. In FIG. 11B, an example of simulation results of the conventional method, the method using the on-chip jitter data acquisition circuit 1 without the offset delay circuit 17, and the method using the jitter circuit 2 including the offset delay circuit 17 are shown. Indicates. Here, the solid line is a conventional method, and the circuit shown in FIG. A one-dot chain line is a method using the on-chip jitter data acquisition circuit 1 that does not have the offset delay circuit 17, and a broken line is a method using the jitter circuit 2 including the offset delay circuit 17. In this example, the result of the simulation by the method using the on-chip jitter data acquisition circuit 1 that does not have the offset delay circuit 17 is increased due to the measurement error caused by autocorrelation. In general, the possibility of such a phenomenon occurring is very low, but measurement error due to autocorrelation may occur when jitter measurement is performed using adjacent pulse signals. It is shown that there is. Therefore, the jitter circuit 2 including the offset delay circuit 17 can reduce the measurement error as compared with the on-chip jitter data acquisition circuit 1 that does not include the offset delay circuit 17.

  With reference to FIG. 12, still another example of the on-chip jitter data acquisition circuit according to the present invention will be described. FIG. 12 shows another example of the on-chip jitter data acquisition circuit according to the present invention. As shown in FIG. 12, the on-chip jitter data acquisition circuit 3 formed on the semiconductor device 100 includes two input terminals, a CLKin terminal and a SELdly terminal, an output terminal CNTout, a variable delay unit 10, and a phase comparison. In addition to the signal generation unit 20 and the phase comparison signal acquisition unit 30, a mode selection multiplexer 41, an output selection multiplexer 43, and an inverting element 45 are included. The inverting element 45 inputs a signal obtained by inverting the output signal of the variable delay unit 10 to one signal input terminal of the mode selection multiplexer 41. The mode selection multiplexer 41 receives the clock signal input to the CLKin signal at the other input terminal. The mode selection multiplexer 41 outputs one of the two input signals to the variable delay unit 10 based on a selection signal input to the SELmode terminal that is a mode selection signal. Hereinafter, the mode in which the mode selection multiplexer 41 outputs the clock signal input to the CLKin signal is referred to as a normal mode. In the normal mode, the on-chip jitter data acquisition circuit 3 measures the jitter of the input pulse signal at CLKin. A mode for outputting an inverted signal of the output signal of the variable delay unit 10 is referred to as a calibration mode. In the calibration mode, the on-chip jitter data acquisition circuit 3 can measure the delay amounts of the delay elements 12 and 15 constituting the variable delay unit 10.

  The measurement principle of the delay amounts of the delay elements 12 and 15 constituting the variable delay unit 10 in the on-chip jitter data acquisition circuit 3 will be described in detail below. In the calibration mode, the on-chip jitter data acquisition circuit 3 forms a ring oscillation circuit by the variable delay unit 10, the inverting element 45, and the multiplexer 43. The output of the ring oscillation circuit is input to the counter circuit 30 via the output selection multiplexer 43. In the calibration mode, after appropriately setting the selection signal input to the SELdly terminal, the number of pulses output from the counter circuit 30 is counted at an appropriate period, whereby the delay element 12 constituting the variable delay unit 10, And 15 respectively can be measured. As described above, by measuring the actual delay amount of the delay elements 12 and 15 constituting the variable delay unit 10, it is possible to improve the measurement accuracy of the jitter measurement using the on-chip jitter data acquisition circuit 3. is there.

  A further example of the on-chip jitter data acquisition circuit according to the present invention will be described with reference to FIG. FIG. 13 shows another example of the on-chip jitter data acquisition circuit according to the present invention. As shown in FIG. 13, the on-chip jitter data acquisition circuit 4 formed on the semiconductor device 100 includes two input terminals, a CLKin terminal and a SELdly terminal, an output terminal CNTout, a variable delay unit 10, and the present embodiment. In the embodiment, it includes a phase comparison signal generation unit 25 that is a time-to-digital converter (TDC), and a phase comparison signal acquisition unit 32 that is a storage circuit in the present embodiment. The on-chip jitter data acquisition circuit 4 is different from the on-chip jitter data acquisition circuit 3 shown in FIG. 12 in that the TDC 25 is used as the phase comparison signal generation unit and the storage circuit 32 is used as the acquisition signal acquisition unit. . The present embodiment is also different from the on-chip jitter data acquisition circuit 3 in that it includes a calibration counter 51 that acquires an oscillation signal of a ring oscillation circuit formed by the variable delay unit 10, the inverting element 45, and the multiplexer 43. The TDC 25 compares the phase of the clock signal input to CLKin and the phase of the clock signal delayed by a predetermined delay amount by the variable delay unit 10, and outputs the comparison result as a digital signal such as an encode signal. The digital signal output from the TDC 25 is stored in the storage circuit 32. The CPU 520 reads out the digital signal stored in the storage circuit 32 at an arbitrary period, and generates a histogram for statistically measuring jitter. Note that the variable delay unit 10 can perform jitter measurement without being variable.

  FIG. 14 is a diagram illustrating an example of a circuit configuration of the TDC 25 employed in the on-chip jitter data acquisition circuit 4. As shown in FIG. 14, the TDC 25 includes a delay circuit row (delay line) in which a plurality of delay elements (non-inverter buffers) 65 that sequentially delay the original clock CK by a predetermined delay amount τ1, and the delay line. The delay clocks CK 1, CK 2, CK 3,... That are sequentially delayed in step S 1 are used as data inputs, and a plurality of D flip-flops 67 that receive the signal to be measured SC as clock inputs, and outputs Q 1, Q 2, Q 3 of the plurality of D flip-flops 67. ,... And an encoder circuit 69 for calculating jitter of the signal under measurement with respect to the original clock CK. The non-inverter buffer 65 is realized by connecting, for example, two stages of inverters. The number of non-inverter buffers 65 to be connected must be equal to or greater than the number obtained by dividing the expected magnitude of jitter of the signal SC to be measured by the delay amount of the non-inverter buffer 65 plus a predetermined margin.

  FIG. 15 shows a flowchart of a method for measuring the jitter of a clock signal using the on-chip jitter data acquisition circuit 4. In step 201, the CPU 520 inputs a clock signal such as a PLL circuit to the CLKin terminal of the on-chip jitter data acquisition circuit 4. In step 202, the CPU 520 determines a delay amount for delaying the clock signal. In step 203, the phase comparison signal generation unit 25, which is a TDC, compares the phase of the clock signal and the signal obtained by delaying the clock signal, and outputs an encoded signal over a predetermined period based on the comparison result. In step 204, the storage circuit 32 stores the output encoded signal. In step 205, the CPU 520 determines whether or not to execute the processes in steps 201 to 204 with all the predetermined delay amounts. If the process has not ended, the processes of steps 201 to 204 are executed again. If the processing has been completed, in step 206, the CPU 520 generates a histogram by reading the encoded signals stored in the storage circuit 32 at a period that can be read by a normal probe and arranging them appropriately. .

  A further example of the on-chip jitter data acquisition circuit according to the present invention will be described with reference to FIG. FIG. 16 shows another example of the on-chip jitter data acquisition circuit according to the present invention. As shown in FIG. 16, the on-chip jitter data acquisition circuit 5 formed on the semiconductor device 100 measures the jitter of the clock signal of the PLL circuit as in the jitter circuit described so far. It is possible to measure the skew between a plurality of paths indicated by two. Each of DUTs (Device Under Test) 1 to 3 is a logic circuit existing in a path between the clock output terminal of the PLL circuit and the D terminal of the latch circuit 21. In the path between the clock output terminal of the PLL circuit and the D terminal of the latch circuit 21, the circuit delay amount of the DUT, the capacitive coupling of the wiring layer, the wiring delay amount caused by the resistance of the wiring layer, and the clock output terminal Depending on various factors such as the gate capacitance of each element, there may be various delay amounts. The on-chip jitter data acquisition circuit 5 measures the jitter that has passed through each path by comparing the clock signal that has passed through each path with the clock signal that has been delayed by a predetermined delay amount by the variable delay unit 10. In addition, skew between paths can be measured. Note that the on-chip jitter data acquisition circuit 5 shown in FIG. 16 has three latch circuits 20, three counter circuits 30, and three CNTout terminals, but these are two, or four or more. Also good.

  Also, as in the on-chip jitter data acquisition circuit 6 shown in FIG. 17, instead of arranging a plurality of counter circuits 30 and CNTout terminals, the outputs of a plurality of 2-input AND elements are selected based on signals input to the SELin terminals. It is also possible to arrange an output multiplexer 61, one counter circuit 30, and a CNTout terminal. By adopting such a configuration, the number of counter circuits 30 can be reduced to one, so that the circuit scale of the on-chip jitter data acquisition circuit 6 can be made relatively small.

  As mentioned above, although several embodiment which concerns on this invention has been described referring an accompanying drawing, it cannot be overemphasized that there may be various modifications, without deviating from the spirit and scope of this invention. In this specification, examples of the phase comparison signal generation unit include a latch circuit, a circuit having a two-input AND element, and a circuit having a TDC, but the phase of a clock signal and a signal obtained by delaying the clock signal are compared. Other possible circuit configurations can be used. Moreover, you may use the other circuit which can acquire the information regarding a phase comparison signal as a phase comparison signal acquisition part.

  Further, for example, the latch circuit 21 constituting the phase comparison signal generation unit 20 may have a Reset terminal that resets the signal of the Q terminal. The latch circuit 21 holds the signal input to the D terminal and outputs it to the Q terminal at the falling edge of the signal input to the CK terminal instead of the rising edge of the signal input to the CK terminal. Also good. Further, the latch circuit 21 may hold an inverted signal of the signal input to the D terminal and output it to the QN terminal.

  In this specification, the on-chip jitter data acquisition circuit 4 that constitutes the phase comparison signal generation unit 25 by TDC adopts the TDC shown in FIG. 15, but adopts a vernier (Vernier) delay line TDC. May be. Further, a TDC having a self-calibration function may be adopted as the TDC.

1, 2, 3, 4, 5, 6 On-chip jitter data acquisition circuit 10 Variable delay unit 12, 14 Delay element 17 Offset delay unit 20, 25 Phase comparison signal generation unit 21 Latch circuit 23 2-input AND element 30, 32 Phase Comparison signal acquisition unit 100 Semiconductor device 500 Semiconductor test device 510 Storage device 520 CPU

Claims (11)

An on-chip jitter data acquisition circuit for acquiring data relating to jitter of a clock signal,
A variable delay unit that delays the clock signal by one of a plurality of delay amounts selectable by a delay amount selection signal;
A phase comparison signal generator that compares the phase of the clock signal with the phase of the clock signal delayed by the variable delay unit to generate a phase comparison signal;
A phase comparison signal acquisition unit for acquiring the phase comparison signal over a predetermined period;
An on-chip jitter data acquisition circuit comprising:   The on-chip jitter data acquisition circuit according to claim 1, wherein the phase comparison signal is a pulse signal indicating a result of the comparison, and the phase comparison signal acquisition unit is a counter circuit that counts the number of the pulse signals.   The on-state according to claim 1, wherein the first phase comparison signal generation unit is a time digital conversion circuit, and the phase comparison signal acquisition unit is a storage unit that stores the phase comparison signal output by the time digital conversion circuit. Chip jitter data acquisition circuit.   The on-chip jitter data acquisition circuit according to claim 1, wherein the variable delay unit further includes an offset delay circuit that delays the clock signal by a given offset delay amount.   The on-chip jitter data acquisition circuit according to claim 4, wherein the offset delay amount is a delay amount that is substantially an integral multiple of the period of the clock signal. In the normal mode for acquiring jitter data, the clock signal is input to the variable delay unit, and in the calibration mode for calibrating the delay amount of the variable delay circuit, an inverted signal of the clock signal delayed by the variable delay unit is used. A mode selection multiplexer for input to the variable delay unit;
In the normal mode, the pulse signal is input to the counter circuit. In the calibration mode, an output signal is input to the counter circuit that receives the oscillation signal of the ring oscillation unit configured by the variable delay unit and the mode selection multiplexer. A multiplexer,
The on-chip jitter data acquisition circuit according to claim 2, further comprising: In the normal mode for acquiring jitter data, the clock signal is input to the variable delay unit, and in the calibration mode for calibrating the delay amount of the variable delay circuit, an inverted signal of the clock signal delayed by the variable delay unit is used. A mode selection multiplexer for input to the variable delay unit;
A calibration counter circuit that counts oscillation signals of a ring oscillation unit configured by the variable delay unit and the mode selection multiplexer;
The on-chip jitter data acquisition circuit according to claim 3, further comprising:   The on-chip jitter data acquisition circuit according to claim 1, comprising two or more phase comparison signal acquisition units. A clock signal generation circuit for generating a clock signal;
The on-chip jitter data acquisition circuit according to any one of claims 1 to 8, which acquires data relating to jitter of a clock signal generated by the clock signal generation unit,
A semiconductor device comprising: A semiconductor test apparatus for testing the semiconductor device according to claim 9,
A probe for reading out the data acquired by the comparison signal acquisition unit from the semiconductor device;
A storage unit for storing data read by the probe;
A processing unit for determining a jitter amount of the semiconductor device based on a histogram created by statistically processing data stored in the storage unit;
A semiconductor test apparatus. A method for measuring jitter of a clock signal generated on-chip,
Delaying the clock signal by a predetermined delay amount to generate a delayed clock signal;
Comparing the clock signal with the delayed clock signal and generating a phase comparison signal based on the comparison result;
Obtaining the phase comparison signal over a predetermined period;
Processing the acquired phase comparison signal to create a histogram;
A method characterized by comprising: