JP2003121505A - Testing circuit and testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the testing circuit of an oscillation circuit, capable of realizing the measurement of jitter using high accuracy by only a logic circuit. SOLUTION: Circuit configuration is formed by incorporating a Base Delay 6, capable of variably controlling delay quantity and a Adjustable Delay 7 in an LSI and the timing difference between the signal, which is obtained by having the output signal of a VCO 26 equipped with a PLL circuit being the oscillation circuit delayed by one cycle, and the signal of the VCO 26 is detected by the Base Delay 6 and the Adjustable Delay 7 to enable measurement of jitters, immediately after the output of the VCO 26. By detecting the timing difference between the signal, which is obtained by delaying the output signal of the VCO 26 by a half cycle, and the signal of the VCO 26 by the Base Delay 6 and the Adjustable Delay 7, the jitters of the section from the rising of the output signal of the VCO 26 to the falling thereof or the section from the falling of the output signal of the VCO 26 to the rising thereof can be measured. Further, the duty ratio of the output of the VCO 26 can be also calculated, on the basis of the value of the measuring result of jitter, without having to change the circuit configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit and a test method for an oscillation circuit incorporated in a semiconductor integrated circuit, and more particularly to a test circuit and a test method capable of measuring a jitter and a duty ratio of an oscillation signal. .

[0002]

2. Description of the Related Art With the progress of technology related to semiconductor integrated circuits, in order to operate only the internal processing section of the LSI and the interface section with external equipment at a speed higher than the system clock, a PLL (Phase Locked) is used as a clock source inside the LSI. Loo
p) Technology for mounting circuits has been developed and widely used. Jitter (clock signal fluctuation) occurs when using the PLL circuit. This jitter can adversely affect other circuits used with LSIs that incorporate PLL circuits. Therefore, it was incorporated in the manufactured LSI.
Jitter data must be measured accurately during PLL circuit evaluation and shipping inspection.

A high-performance analog LSI is used for measuring jitter.
It is common to use a tester or measuring equipment.The high-speed clock generated by the PLL circuit is output to the outside through the LSI pin, and measuring equipment is connected to that pin to measure the jitter. Become. In this measurement method, the output clock of the PLL circuit is taken out through the pads of the LSI chip, the wires, the package terminals, and the cable to the measuring device. Therefore, there is a problem that the clock waveform becomes dull due to the influence of the wiring capacitance and the wiring resistance, and the influence of noise is exerted, so that accurate jitter measurement cannot be performed. Further, as described above, the jitter measurement requires a high-performance analog LSI tester and a measuring instrument, which causes a problem that the cost of shipping inspection at the time of LSI production increases.

In order to solve these problems, there is a method of measuring the PLL signal without taking it out. For example,
Stephen Sunter & Aubin Roy, LogicVision, Inc. "BIST
forPhase-Locked Loops in Digital Applications ", P
roceedings IEEE International Test Conference, 199
9, pp.532-540 proposes a method of incorporating a measurement circuit inside the LSI and performing a test with a logic tester. Figure 2
0 is a block diagram showing the circuit configuration of the conventional technique.
According to this paper, as shown in FIG. 20, the built-in jitter test circuit 101 includes a constant delay block 111,
Adjustable Delay block 112, D flip-flop 113, Error Counter block 114, OSC.Freq. Co
It is composed of an unter block 115 and a selector 116. Also, the clock fREF supplied to the PLL circuit 102 and the VCO 124 of the PLL circuit 102 outputs the clock fREF, and the N frequency divider 125 outputs 1
And the signal multiplied by N is used. The operation of this circuit 101 is an operation of observing the difference between the clock fREF supplied to the PLL circuit 102 and the timing of the signal multiplied by 1 / N by the VCO 124 in the PLL circuit 102 with the Error Counter 114 while operating the Adjustable Delay 112. And the absolute delay time of Adjustable Delay 112 is set to OSC.Fre
q. Counter 115 is used for measurement. This enables highly accurate jitter measurement and measurement with a logic tester.

[0005]

[Problems to be Solved by the Invention]
In “For Phase-Locked Loops in Digital Applications”, the output point of the signal after being multiplied by 1 / N by the N divider 125 is the jitter measurement point.
In the jitter test circuit 101, the signal after being 1 / N-divided by the N frequency divider 125 and the clock (reference clock) fREF supplied to the PLL circuit 102 are compared to perform the measurement. However, the signal actually used inside the LSI is the signal immediately after being output from the VCO 124 of the PLL circuit 102, and the jitter value may be specified as a specification by the value measured immediately after this VCO 124. Many. Therefore, this conventional measuring method is difficult to adopt because it measures a signal different from the signal actually used in the LSI. Also, the reference clock input to the PLL circuit 102 and the signal fed back via the N frequency divider 125,
Since the circuit configuration detects the phase difference of
It cannot be applied to oscillator circuits other than L circuits. Furthermore, the conventional circuit has a configuration in which the duty ratio of the oscillation clock output from the VCO circuit 124 cannot be measured.

Therefore, the present invention was created in order to solve the above problems, and an object thereof is to provide a test circuit and a test method for an oscillation circuit that can realize highly accurate jitter measurement only with a logic circuit. is there.

[0007]

The present invention has the following structure as means for solving the above problems.

(1) In a test circuit for performing a jitter test of an oscillation circuit incorporated in a semiconductor integrated circuit, one cycle or a half period depends on a current output signal of the oscillation circuit and a delay circuit included in the semiconductor integrated circuit. The output signal of the oscillation circuit delayed by the period and at least one of the rising edge and the falling edge of the two signals are detected a plurality of times to measure the jitter of one cycle or half cycle in the output signal of the oscillation circuit. It is characterized by doing.

In this configuration, in the test circuit for performing the jitter test of the oscillation circuit incorporated in the semiconductor integrated circuit, the output signal of the oscillation circuit delayed by one cycle or half cycle by the delay circuit included in the semiconductor integrated circuit. And the current output signal of the oscillator circuit and at least one of the rising edge and the falling edge of the two signals are detected a plurality of times to measure the jitter of one cycle or half cycle of the output signal of the oscillator circuit. Therefore, since only the output signal of the oscillation circuit is used, the reference signal to be compared is not required, so it can be applied not only to the PLL circuit but also to all oscillation circuits, and the jitter immediately after the output of the oscillation circuit can be accurately measured. It becomes possible to measure. Also, the jitter can be measured only by a relatively inexpensive logic tester.

(2) A delay value that can adjust the delay value from outside the semiconductor integrated circuit, and delays the output signal of the oscillation circuit by one cycle or half cycle; and the semiconductor integrated circuit, A second delay circuit block capable of adjusting a delay amount by a predetermined amount from the outside, and the oscillation circuit delayed by one cycle or half cycle by the first delay circuit block and the second delay circuit block. An output signal and a current output signal of the oscillator circuit,
And a number counter that counts the number of times that the current output signal of the oscillation circuit first arrives.

In this configuration, the test circuit for performing the jitter test of the oscillation circuit includes the first delay circuit block, the second delay circuit block, and the frequency counter, and is external to the semiconductor integrated circuit. A first delay circuit block having a delay value adjustable from 1 to 1, which delays the output signal of the oscillation circuit by one cycle or half cycle,
And an output signal of the oscillation circuit delayed by one cycle or a half cycle by a second delay circuit block capable of adjusting a delay amount by a predetermined amount from outside the semiconductor integrated circuit,
A signal arrival time of the current output signal of the oscillator circuit is compared with a plurality of times, and the number of times that the current output signal of the oscillator circuit first arrives is counted by a number counter. Therefore,
Since only the output signal of the oscillation circuit is used, the reference signal to be compared is not required, so it is applicable not only to the PLL circuit but also to all oscillation circuits, and the jitter immediately after the output of the oscillation circuit is measured accurately. It becomes possible.

(3) A ring oscillator comprising the first delay circuit block and the second delay circuit block, and a frequency counter for measuring the frequency when the ring oscillator is oscillated. Is characterized by.

In this configuration, the test circuit for performing the jitter test of the oscillation circuit includes a ring oscillator composed of the first delay circuit block and the second delay circuit block, and a ring oscillator when the ring oscillator is oscillated. And a frequency counter for measuring the frequency of. Therefore, accurate jitter measurement is possible without being affected by variations in LSI manufacturing process, temperature, and power supply voltage.

(4) An inverter element which can be connected and disconnected is provided immediately after the output terminal of the oscillation circuit.

In this structure, the test circuit for performing the jitter test of the oscillation circuit includes an inverter element that can be connected and disconnected immediately after the output terminal of the oscillation circuit. Therefore, the time from the falling edge to the rising edge of the output signal of the oscillation circuit can be measured, and the duty ratio test of the oscillation circuit can be performed.

(5) A switching counter capable of switching the function of the frequency counter and the function of the frequency counter is provided in place of the frequency counter and the frequency counter.

In this configuration, the test circuit for performing the jitter test of the oscillation circuit includes a switching counter capable of switching the function of the frequency counter and the function of the frequency counter instead of the frequency counter and the frequency counter.
Therefore, the circuit scale can be reduced, and the product cost can be reduced.

(6) In a test circuit for performing a duty ratio test of an oscillation circuit incorporated in a semiconductor integrated circuit, a first delay circuit block for delaying an output signal of the oscillation circuit by a half cycle, and a semiconductor integrated circuit. A second delay circuit block whose delay amount can be adjusted by a predetermined amount from outside, and a signal delayed by a half cycle by the first delay circuit block and the second delay circuit block,
A number counter that compares the signal arrival times of the two signals of the current oscillation circuit output signal and the current oscillation signal a plurality of times, and counts the number of times that the current output signal of the oscillation circuit has reached first;
Ring oscillator configured by the second delay circuit block and the second delay circuit block, a frequency counter for measuring the frequency when the ring oscillator is oscillated, and a connection / separation possible immediately after the output terminal of the oscillation circuit An inverter element connected to, the inverter element is separated, a current output signal of the oscillator circuit, and a signal obtained by delaying the output signal of the oscillator circuit by a half cycle by an adjustable delay circuit block, The signal arrival times of the two signals are compared a plurality of times while increasing the delay amount for a half cycle by a predetermined amount, and the number of times that the current oscillation circuit output signal arrives first is counted by the number counter, The signal delayed by a half cycle by the first delay circuit block and the second delay circuit block is oscillated by the ring oscillator to generate a frequency. A first average time obtained by measuring the average time from the rising edge to the falling edge of the output signal of the oscillation circuit using the measured frequency, and connecting the inverter element to the output signal of the oscillation circuit. By inverting the current output signal of the oscillating circuit and a signal obtained by delaying the output signal of the oscillating circuit by a half cycle by an adjustable delay circuit block The number of times the current oscillation circuit output signal arrives first is counted by the number of times counter by increasing the delay amount by a predetermined amount, and the first delay circuit block and the second delay circuit block A signal delayed by a half cycle is oscillated by the ring oscillator to measure the frequency, and the rising edge of the output signal of the oscillating circuit is measured using the measured frequency. A second average time of measuring the average time to Luo falling edge, to the difference between the feature that it is possible calculate the duty ratio.

In this configuration, the test circuit for performing the duty ratio test of the oscillation circuit incorporated in the semiconductor integrated circuit measures the average time from the rising edge to the falling edge of the output signal of the oscillation circuit.
The duty ratio is calculated from the difference between the average time and the second average time obtained by measuring the average time from the rising edge to the falling edge of the output signal of the oscillation circuit. For the first average time, the inverter element connected so that it can be contacted and separated is disconnected, and the current output signal of the oscillation circuit and the first delay circuit block and the second delay circuit capable of adjusting the output signal of the oscillation circuit are adjusted. The signal arrival time of the signal delayed by a half cycle by the circuit block and the signal arrival times of the two signals are compared multiple times while increasing the delay amount for a half cycle by a predetermined amount, and the current oscillation circuit output signal arrives first. The number of times is counted by the number counter, and the first delay circuit block and the second delay circuit block are counted.
A signal delayed by a half cycle by the delay circuit block is oscillated by the ring oscillator to measure the frequency, and the average time from the rising edge to the falling edge of the output signal of the oscillation circuit is measured using the measured frequency. Ask for. In the second averaging time, the inverter element connected so that it can be contacted and separated is connected, the output signal of the oscillation circuit is inverted, and the current output signal of the oscillation circuit and the output signal of the oscillation circuit can be adjusted. A signal delayed by a half cycle by the delay circuit block and the signal arrival times of the two signals are compared multiple times while increasing the delay amount for the half cycle by a predetermined amount, and the current oscillation circuit output signal arrives first. The counted number is counted by the counter, the signal delayed by a half cycle by the first delay circuit block and the second delay circuit block is oscillated by the ring oscillator to measure the frequency, and the oscillating circuit is measured by using the measured frequency. It is calculated by measuring the average time from the rising edge to the falling edge of the output signal.

Therefore, the duty ratio can be accurately measured without being affected by variations in LSI manufacturing process and temperature by the power supply voltage.

(7) In a test method for performing a jitter test of an oscillation circuit incorporated in a semiconductor integrated circuit, a delay circuit block capable of adjusting a delay value of an output signal of the oscillation circuit is used for one cycle or a half cycle. Compare the signal arrival times of the two signals, the delayed signal and the current output signal of the oscillation circuit, multiple times while increasing the delay amount for one cycle or a half cycle by a predetermined amount, and calculate the current oscillation time. It is characterized in that the number of times the circuit output signal reaches first is counted to obtain the minimum period width and the maximum period width of the output signal of the oscillation circuit.

In this structure, the delay circuit block capable of adjusting the delay value of the output signal of the oscillation circuit incorporated in the semiconductor integrated circuit delays the signal by one cycle or half cycle and the current output signal of the oscillation circuit. And the signal arrival times of the two signals are compared a plurality of times while increasing the delay amount for one cycle or a half cycle by a predetermined amount, and counting the number of times that the current oscillator circuit output signal arrives first. , The minimum period width and the maximum period width of the output signal of the oscillation circuit are obtained. Therefore, since only the output signal of the oscillation circuit is used, the reference signal to be compared is not required,
Not only the PLL circuit but also all the oscillation circuits can be applied, and the jitter immediately after the output of the oscillation circuit can be accurately measured.

(8) A characteristic is characterized in that the output signal having the minimum period width and the output signal having the maximum period width in the oscillation circuit is oscillated by a ring oscillator, and the jitter of one period or half period is obtained. To do.

In this configuration, the frequency oscillated by the ring oscillator is measured, and the frequency at which the output signal having the minimum period width and the output signal having the maximum period width in the oscillation circuit are oscillated by the ring oscillator is measured to obtain 1 Find the jitter in cycles or half cycles. Therefore, without being affected by variations in LSI manufacturing process, temperature, and power supply voltage,
Accurate jitter measurement is possible.

(9) In a test method for performing a duty ratio test of an oscillator circuit incorporated in a semiconductor integrated circuit, a delay circuit block capable of adjusting the current output signal of the oscillator circuit and the output signal of the oscillator circuit. By comparing the signal arrival times of the two signals delayed by a half cycle and the signal arrival times of the two signals a plurality of times while increasing the delay amount for a half cycle by a predetermined amount, the number of times that the current oscillation circuit output signal arrives first is determined. A counting step of counting, a frequency measuring step of oscillating a signal delayed by a half cycle by a delay circuit block by a ring oscillator to measure a frequency, and an output signal of the oscillation circuit using the frequency measured in the frequency measuring step. A first averaging time measuring step of measuring an averaging time from a rising edge to a falling edge, and inverting the output signal of the oscillation circuit Second averaging time measuring step for measuring the averaging time from the falling edge to the rising edge of the output signal of the oscillation circuit by using the frequency measured by performing the counting step, the frequency measuring step and the averaging time measuring step And a duty ratio calculating step of calculating a duty ratio from the difference between the two average times measured in the first average time measuring step and the second average time measuring step.

In this configuration, two signals, that is, a current output signal of the oscillator circuit incorporated in the semiconductor integrated circuit and a signal obtained by delaying the output signal of the oscillator circuit by a half cycle by an adjustable delay circuit block are used. The arrival time is compared with a plurality of times while increasing the delay amount for a half cycle by a predetermined amount, and the counting step of counting the number of times that the current oscillation circuit output signal has reached first and the delay circuit block are delayed by a half cycle. A frequency measurement step in which a signal is oscillated by a ring oscillator to measure a frequency, and a first average time for measuring an average time from a rising edge to a falling edge of an output signal of an oscillation circuit using the frequency measured in the frequency measurement step. Measurement is performed by inverting the output signal of the oscillation circuit, counting step, frequency measuring step and averaging time measuring step The second averaging time measuring step for measuring the averaging time from the falling edge to the rising edge of the output signal of the oscillating circuit using the frequency, and the first averaging time measuring step and the second averaging time measuring step. Two
A duty ratio test of the oscillation circuit incorporated in the semiconductor integrated circuit is performed by a duty ratio calculation step of calculating the duty ratio from the difference between the two average times.

Therefore, it is possible to measure the duty ratio accurately without being influenced by the power supply voltage on the variation of the LSI manufacturing process and the temperature.

(10) In the configurations of (1) to (9), the oscillation circuit can be a PLL circuit.

Therefore, it becomes possible to accurately test the jitter and duty ratio, which are problems in the PLL circuit.

[0030]

1 is a block diagram showing the configuration of a test circuit for an oscillator circuit according to an embodiment of the present invention. Figure 1 shows the output signal Outp of Oscillator 1.
ut2 is the system clock supply line System CLK (hereinafter,
Called System CLK. ) 3 is the example in which the jitter test circuit 61 is incorporated in the semiconductor integrated circuit used as the above. The test circuit 61 includes a selector 4, a first delay circuit block Base Delay (basic delay circuit) 6, a second delay circuit block Adjustable Delay (adjustable delay circuit) 7, a D flip-flop 8, and a Meas Count.
er (number counter) 9 and Freq. Counter (frequency counter) 10.

One input terminal of the selector 4 is System C
Connected to LK3, the other input terminal is Adjustable Delay 7
Is connected to the input terminal of the Base Delay 6 and the data input terminal of the D flip-flop 8. The output terminal of Base Delay 6 is Adjustable D
It is connected to the input terminal of elay7. Adjustable Delay
The output terminal of 7 is a clock input terminal of the D flip-flop 8, the other input terminal of the selector 4, and Freq. Counte.
It is connected to one input terminal of r 10. The output terminal of the D flip-flop 8 is connected to the input terminal of the Meas Counter 9. Further, the other input terminal of the Freq. Counter 10 is connected to the reference clock Ref CK11.

The selector 4 uses the Jitter / OSC select signal 5
If is “0”, it is Jitter measurement mode. If it is “1”, Ba
It becomes a ring oscillation mode in which se Delay 6 and Adjustable Delay 7 are connected in a ring shape. The Base Delay 6 can variably control the delay value from the outside and outputs the output signal Output 2 for one cycle.
Or it has a role of delaying for half a cycle, and is an Adjustable Delay
Reference numeral 7 is a circuit having a structure in which the delay amount can be controlled from the outside in fine steps compared to the Base Delay 6. Meas Count
The er 9 has a function of counting the number of times that the D flip-flop 8 latches “1” in the period of the designated cycle in the jitter measurement mode. Freq. Counter 10
Ref CK, which is the reference clock in ring oscillation mode
Base Del for the period of the specified cycle in 11.
It has a function to count the number of oscillations of the ring oscillator composed of ay6 and Adjustable Delay7.

Periodic jitter measured by this circuit (hereinafter referred to as Peri
Called od Jitter. ) Outline the test. FIG. 2 is a waveform diagram showing the output cycle of the Oscillator. FIG. 3 is a waveform diagram showing the concept of periodic jitter. As shown in FIG. 2, the clock cycle width 12 of each cycle of the signal output from the Oscillator 1 is sequentially measured. The result is as shown in FIG. At this time, a value obtained by taking the difference between the maximum value Tmax13 of the clock cycle width and the minimum value Tmin14 of the clock cycle width, that is, Tmax13-
Tmin14 becomes Peak-to-Peak's Period Jitter 15.
In general, the number of output cycles of the Oscillator is often about tens of thousands.

The measurement principle is that the base cycle 6 and the adjustable delay 7 are applied to the clock cycle width 12 of the oscillator 1.
When the delay amount due to is small, "0" is latched in the flip-flop 8, and conversely, when it is large, "1" is latched in the D flip-flop 8.
That is, the amount of delay by the Base Delay 6 and Adjustable Delay 7 is determined, and D is set for a predetermined number of cycles N times.
The number of times the flip-flop 8 latches "1" is Me
Count with as Counter 9. When the number of cycles N is completed, the contents of Meas Counter 9 are read out,
Delay amount by Base Delay 6 and Adjustable Delay 7,
The relationship between the clock cycle width 12 and is understood. This time,
If the value of the Meas Counter 9 is “0”, the cycle width is 12> the delay amount by the Base Delay 6 and the Adjustable Delay 7. If the value of Meas Counter 9 is “N”, cycle width 12 <Base Delay 6 and Adjustable
The delay amount by Delay 7 is In addition, Meas Counter
When the value of 9 is "1" to "N-1", the flip-flop 8 has both the values of "0" and "1", so the delay amount by the Base Delay 6 and Adjustable Delay 7 at that time. Will be within the jitter. By repeating these measurements while slightly changing the delay amount by Base Delay 6 and Adjustable Delay 7, Tmax 13 and Tmin
14 is calculated, and Peak-to-Peak Period Jitter 15 is calculated.

Next, details of the jitter measuring method using this circuit example will be described with reference to FIG. FIG. 4 is a flowchart for explaining the jitter measuring method. FIG. 5 is a time chart diagram of the input signal of the D flip-flop.

When measuring the jitter of the oscillation circuit provided in the semiconductor integrated circuit (LSI), first, the Jitter mode is set (S1). That is, “0” is input to the Jitter / OSC select signal 5, and the selector 4 selects the output signal Output 2 of the Oscillator 1.

Then, the Base Delay 6 is adjusted (S
2). That is, as shown in FIG. 5, the output signal Output
2 is delayed by one cycle. By this operation, the ck input of the D flip-flop 8 comes in one cycle later than the signal of the D input. If the delay value of Base Delay 6 is known in advance, use that value. However, Base D
If the value of elay6 is not clear, adjust the value of Base Delay 6 so that it corresponds to one cycle. Since the adjustment at this time may be roughly delayed by one cycle, the value of the Base Delay 6 when the value latched by the D flip-flop 8 changes from "0" to "1" is used. During the processing of S2, the Adjustable Delay 7 is set to a substantially central value of the adjustable range.

Next, the Adjustable Delay 7 is sequentially increased and the Meas Counter value is read (S3). That is, Adjust
Set able Delay 7 to the minimum value and set the number of cycles N times Me.
After operating as Counter 9, the value of Meas Counter 9 is read and recorded together with the setting value of Adjustable Delay 7. Next, the Adjustable Delay 7 is slightly increased, and the Meas Counter 9 is similarly operated for N cycles, and then Meas Cou
Read the value of nter9 and record it together with the setting value of Adjustable Delay7. This operation is repeated until the adjustment of Adjustable Delay 7 reaches the maximum value.

Here, the processing of this step will be described in detail with reference to FIG. FIG. 6 is an enlarged time chart diagram of the changed portion of the input signal of the D flip-flop, which is an enlarged portion of the signal 17 delayed by one cycle in FIG.
The D input waveform and the ck input waveform of the flip-flop 8 are shown. The jitter 18 indicates that the width of one cycle is slightly deviated in each cycle. Adjust in S3
able delay 7 is slightly increased from (1) to (3) in FIG.
Sequentially record the Meas Counter 9 value. Here, the D flip-flop 8 latches at the rising edge of the ck input waveform. Therefore, at the point (1) in FIG. 6, since the D flip-flop 8 always latches “0”, the Meas Count
The value of er9 becomes "0". Further, at the point (2) in FIG. 6, the D flip-flop 8 latches "0" and "1", so the value of the Meas Counter 9 becomes an intermediate value. Further, at the point (3) in FIG. 6, the D flip-flop 8 always latches “1”, so the Meas Count
The value of er9 becomes the same value as the measurement cycle number N.

FIG. 7 is a graph showing the relationship between the delay value and the count value of the Meas Counter, which is a graph of the results measured in step S3. Vertical axis is Me
It is a value of as Counter 9, the origin is “0”, and the cycle number N is a full value. The horizontal axis is Base Delay 6 and Adju
It is a delay value by stable Delay 7. The measurement points (1), (2) and (3) shown in FIG. 6 and the measurement points (1), (2) and (3) shown in FIG. 7 have the same value. Here, the place where the count value switches from "0" is Tmin2
It is 0, and Tmax21 immediately before the count value becomes Full. The jitter value (Period Jitter) is Tmax21.
-Tmin is 20.

At this time, it is determined whether or not the accurate delay times of Tmax and Tmin are known (S4). That is, Tmax2
If the exact delay time of 1, Tmin 20 is known, Tmax
21-Tmin20 is calculated (S7). However, LS
When Base Delay 6 and Adjustable Delay 7 are incorporated into I, it is usually impossible to specify the true delay time due to the influence of variations in the LSI manufacturing process, temperature, and power supply voltage. Therefore, in that case, as the next step,
Time measurement of Tmax21 and Tmin20 is performed.

First, the OSC mode is set (S5). That is, "1" is input as the Jitter / OSC select signal 5, and the selector 4 outputs the output of the Adjustable Delay 7 to Base Del.
As input of ay6, make ring oscillator structure. Here, in order to make sure that oscillation is performed, Base Delay 6
The circuit that is combined with Adjustable Delay 7 is an odd number of inverter circuits.

Next, the oscillation frequency at the Tmin and Tmax values is measured (S6). That is, Base Delay 6 and Adjustable D
Set the state of elay7 to Tmin20, Ref CK1 of fixed cycle
Input 1 from the outside, and in the period for the specified cycle,
The number of oscillations of the ring oscillator is counted by Freq. Counter 10.

Here, assuming that the cycle of the Ref CK11 is W and the designated number of cycles is M, how many times the ring oscillator oscillates in the period of W × M is Freq. Counter 1
Counted as 0. Then, the count value is recorded as Cmin. Similarly, Base Delay 6 and Adjustable
Set the state of Delay7 to Tmax21 and measure the count value. Then, the count value is recorded as Cmax.

Next, the Jitter width is calculated (S7). That is, Base Delay 6 and Adju at Tmin 20 and Tmax 21
Calculate the delay amount by stable Delay7. Base Delay6
Since the delay amount by the Adjustable Delay 7 is 1/2 of the cycle of the ring oscillator, the delay amount can be calculated by the following formula 1. In other words, Base Delay 6 and Adjustab
Assuming that the delay amount of le Delay 7 is D, the value counted by the Freq. Counter 10 is C, the cycle of the Ref CK11 is W, and the designated number of cycles is M, D = W × M / C / 2 ... Formula 1 The delay amount can be calculated with. Here, the count value C
By substituting Cmin recorded in S6 for, the delay value by Base Delay 6 and Adjustable Delay 7 at Tmin 20 is obtained. This value is Dmin. Similarly, if Cmax is substituted, Base Delay 6 and Adjustable Del at Tmax 21
The delay value due to ay7 is obtained. This value is Dmax. Then, the jitter width 22 is calculated by the following Expression 2.

Jitter = Dmax-Dmin .... Equation 2 With the above method, the peak-t in units of one cycle from the rising edge of the signal of the oscillation circuit to the next rising edge.
The Period Jitter 22 of o-Peak can be obtained.

FIG. 8 is a circuit diagram showing a configuration for testing the PLL circuit by the test circuit of the oscillator circuit according to the embodiment of the present invention. FIG. 9 is a configuration diagram of a modified example of the counter in the test circuit of the oscillator circuit according to the embodiment of the present invention.
As shown in FIG. 8, the Oscillator 1 shown in FIG.
Even if the circuit is replaced with the L circuit 23, measurement can be performed without any problem, as in the procedure described based on the flowchart of FIG. The PLL circuit 23 includes a PHASE DETECTOR (phase detector) 24, a CHARGE PUMP 25, and a VCO (voltage controlled oscillator).
26 and DIVIDER (N frequency divider) 27. Also, the VCO
The output terminal of 26 is connected to one input terminal of the selector 4.

In the embodiment described with reference to the flow chart of FIG. 4, the Meas Counter 9 and Freq. Coun
The ter 10 is never used at the same time. Therefore, FIG.
Adjustable Delay 7 output terminal Jitter
Controller2 that switches connection between OSC mode and OSC mode
8, the output terminal of Adjustable Delay 7, the output terminal of D flip-flop 8 and the input terminal of Ref CK11
In addition to being connected to the Controller 28, the output terminal of the Controller 28 is connected to the Counter 29 to share the Counter 29. As a result, the circuit scale can be reduced.

Next, in the test circuit of the oscillation circuit of the present invention,
A method of measuring the jitter from the rising edge to the falling edge of the signal output by the Oscillator 1 will be described. FIG. 10 is a waveform diagram showing the rising edge to the falling edge of the output of the oscillation circuit. Figure 1
FIG. 1 is a diagram showing a concept of a half-period Period Jitter. FIG. 12 is a second time chart diagram of the input signal of the D flip-flop. In this measuring method,
As shown in, the time 30 from the rising edge to the falling edge of each cycle is sequentially measured. Then, as a result, the value obtained by taking the difference between the maximum value Tmax31 and the minimum value Tmin32 shown in FIG. 11, that is, Tmax31-Tmi
n 32 is a Peak-to-Peak Period Jitter 33 from the rising edge to the falling edge.

The measuring circuit is the test circuit 61 shown in FIG.
To use. The procedure of the measuring method will be described with reference to the flowchart shown in FIG. First, Jitt
The er mode is set (S1). That is, "0" is input to the Jitter / OSC select signal 5 and Oscillator is selected by the selector 4.
Select the output signal Output2 of the llator1.

Next, the Base Delay is adjusted (S2). That is, as shown in FIG. 12, the output signal Output2 is delayed by a half cycle. By this operation, the ck input of the D flip-flop 8 is delayed by a half cycle from the signal of the D input. If the value of Base Delay 6 is known in advance, use that value. However, if the value of Base Delay 6 is not clear, adjust the value of Base Delay 6 so that it corresponds to a half cycle. The adjustment at this time may be roughly delayed by a half cycle, so the D flip-flop 8
Base when the value latched in is changed from "1" to "0"
Use the value of Delay6. During the processing of S2, Adju
The stable delay 7 is set to be approximately the center value of the adjustable range.

Then, the Adjustable Delay is sequentially increased and the Meas Counter value is read (S3). That is, Adjust
Set able Delay 7 to the minimum value and set the number of cycles N times Me.
After operating as Counter 9, the value of Meas Counter 9 is read and recorded together with the setting value of Adjustable Delay 7. Next, the Adjustable Delay 7 is slightly increased, and the Meas Counter 9 is similarly operated for N cycles, and then Meas Cou
Read the value of nter9 and record it together with the setting value of Adjustable Delay7. This operation is repeated until the adjustment of Adjustable Delay 7 reaches the maximum value.

Here, the processing of this step will be described in detail with reference to FIG. FIG. 13 is a second time chart diagram in which the changing portion of the input signal of the D flip-flop 8 is enlarged, and the portion of the signal 35 delayed by a half cycle in FIG. 12 is enlarged. The waveform and ck input waveform are shown. The jitter 36 shows that the width of the half cycle is slightly deviated in each cycle. In S3, the Adjustable Delay 7 is changed from (1) to (3) in FIG.
Slightly increase to, and record the value of Meas Counter 9 successively. Here, at the point (1) in FIG. 13, the D flip-flop 8 always latches “1”, so the Meas Counter 9
The value of is the same as the number of measurement cycles N. In addition, FIG.
At point (2), the D flip-flop 8 takes "1" and "0", so the value of the Meas Counter 9 becomes an intermediate value. Further, at the point (3) in FIG. 13, the D flip-flop 8 always latches "0", so the value of the Meas Counter 9 becomes "0".

FIG. 14 is a second graph showing the relationship between the delay value and the count value of the Meas Counter, which is a graph of the results measured in step S3.
The vertical axis is the value of Meas Counter 9, the origin is “0”,
The cycle number N is set to the Full value. The horizontal axis is Base Delay 6
And the delay value by Adjustable Delay 7. Figure 1
Measurement points (1), (2) and (3) shown in FIG.
The measurement points (1), (2) and (3) shown in (1) have the same value. Here, the place where the count value switches from Full is Tmin38, and the place just before the count value becomes “0”
It becomes Tmax39. And the jitter value (Period Jitter)
40 is Tmax39-Tmin38.

At this time, it is determined whether or not the accurate delay times of Tmax and Tmin are known (S4). That is, Tmax3
If the exact delay time of 9, Tmin 38 is known, Tmax 3
9-Tmin38 is calculated (S7). However, LSI
When the Base Delay 6 and Adjustable Delay 7 are incorporated in the, it is usually impossible to specify the true delay time due to the influence of variations in the LSI manufacturing process, temperature, and power supply voltage. Therefore, in that case, as the next step, Tm
The time of ax39 and Tmin38 is measured.

First, the OSC mode is set (S5). That is, "1" is input as the Jitter / OSC select signal 5, and the selector 4 outputs the output of the Adjustable Delay 7 to Base Del.
As input of ay6, make ring oscillator structure. Here, in order to make sure that oscillation is performed, Base Delay 6
The circuit including the Adjustable Delay 7 and the Adjustable Delay 7 should be an odd number of inverter circuits.

Next, the oscillation frequency at Tmin and Tmax is measured (S6). That is, Base Delay 6 and Adjustable D
Set the state of elay7 to Tmin38 and set Ref CK1 at a constant cycle.
Input 1 from the outside, and in the period for the specified cycle,
The number of oscillations of the ring oscillator is counted by Freq. Counter 10.

Here, assuming that the cycle of the Ref CK11 is W and the designated number of cycles is M, the Freq. Counter 10 determines how many times the ring oscillator oscillates in the period of W × M.
Is counted in. Then, the count value is recorded as Cmax. Similarly, Base Delay 6 and Adjustable
Set the state of Delay 7 to Tmax 39 and measure the count. Then, the count value is recorded as Cmax.

Next, the Jitter width is calculated (S7). That is, Base Delay 6 and Adju at Tmax 39 and Tmin 38
The delay amount of the stable delay 7 is calculated, and the Peak-to-Peak Peri in the unit of a half cycle from the rising edge to the falling edge of the signal of the oscillation circuit is calculated by using the above Equations 1 and 2.
Ask for the od Jitter 40.

FIG. 15 is a waveform diagram showing the falling edge to the rising edge of the output of the oscillator circuit. FIG. 16 is a configuration diagram in which an inverter element is added to the test circuit according to the embodiment of the present invention. Here, in order to obtain the jitter in units of half cycle from the falling edge to the next rising edge of the signal of the oscillator circuit shown in FIG.
As shown in FIG. 16, an INV 42, which is an inverter element, is provided between the output terminal of the Oscillator 1 and one input terminal of the selector 4. And the output signal of Oscillator1
By inverting Output2 with INV 42, it is possible to measure by exactly the same method as the method of obtaining the half cycle jitter from the rising edge to the next falling edge shown above.

In FIG. 16, the INV 42 is provided between the output terminal of the Oscillator 1 and one input terminal of the selector 4. However, in reality, a selector or the like is incorporated in the circuit to replace the INV 42 with the INV 42. It is advisable to adopt a configuration in which it is possible to select whether or not to connect the circuit. As a result, one circuit can be used without providing both the circuits of FIGS. 1 and 16.

Next, the duty of the oscillator circuit is measured using the half cycle jitter measuring method from the rising edge to the next falling edge and the half cycle jitter measuring method from the falling edge to the next rising edge. A method for obtaining the ratio will be described based on the flowchart shown in FIG. FIG. 17 is a flow chart for explaining the method for obtaining the duty ratio of the oscillation circuit using the test circuit of the present invention. FIG. 18 is a third graph showing the relationship between the delay value and the count value of the Meas Counter. FIG. 19 is a waveform diagram showing the duty ratio of the oscillation circuit.

When obtaining the duty ratio of the oscillation circuit, first, the Jitter mode is set (S11). That is, “0” is input to the Jitter / OSC select signal 5, and the selector 4 selects the output signal Output 2 of the Oscillator 1.

Then, the jitter is measured for a half period from the rising edge to the next falling edge. First, the Base Delay is adjusted (S12). That is, the output signal Output2 is delayed by a half cycle. During the processing of S2, the Adjustable Delay 7 is set to a substantially central value of the adjustable range.

Next, the Adjustable Delay is sequentially increased and the Meas Counter value is read (S13). Ie Adju
Set stable delay 7 to the minimum value and cycle N times
After operating Meas Counter 9, the value of Meas Counter 9 is read and recorded together with the setting value of Adjustable Delay 7. Next, the Adjustable Delay 7 is slightly increased, and the Meas Counter 9 is similarly operated for N cycles, and then Meas Cou
Read the value of nter9 and record it together with the setting value of Adjustable Delay7. This operation is repeated until the adjustment of Adjustable Delay 7 reaches the maximum value (counting step). Thereby, the result of Rise to Fall 43 shown in FIG. 18 is obtained. In addition, in FIG. 18, the vertical axis of the graph represents the Meas Count.
It is the value of er9, the origin is “0”, and the cycle number N is Fu
ll value. The horizontal axis is Base Delay 6 and Adjustable D
It is a delay value by elay7.

Subsequently, Ta at which the Meas Counter value becomes 50%
(S14). That is, the count value is "0" to Fu
The value of Ta45 is recorded when the value becomes an intermediate value of ll (first average time measuring step).

Next, the half cycle from the falling edge to the next rising edge is measured. First, Osci
The output of the llator is inverted (S15). Ie Output
By inverting the signal 2 with the INV 42, the half cycle from the rising edge shown above to the next falling edge is measured.

Next, the Base Delay is adjusted (S16).
Then, gradually increase Adjustable Delay to increase Meas Cou
The nter value is read (S17). That is, the processing is exactly the same as S12 and S13. As a result, the Fall shown in FIG.
The result of to Rise is 44. Then, Meas Count
A Tb having an er value of 50% is searched (S18). That is, Tb46 when the count value becomes an intermediate value between "0" and Full is recorded (second average time measuring step).

Here, it is determined whether or not the correct delay time of Ta and Tb is known (S19). At this time, Ta45, Tb
If the accurate time of 46 is known, Tb46-Ta45 is calculated to be Δt 47, and the duty ratio is calculated by the equations 3 and 4 described in S22 (S22).

On the other hand, when the time of Ta45 and Tb46 is unknown, the OSC mode is set (S20). That is, Ji
Input "1" to tter / OSC select signal 5 and select 4
Then, the output of Adjustable Delay 7 is used as the input of Base Delay 6, and the structure of the ring oscillator is created.

Next, the oscillation frequency at Ta and Tb values is measured (S21). That is, Base Delay 6 and Adjustable D
Set the state of elay7 to Ta45, Ref CK11 with a constant cycle
Is input from the outside, and the number of oscillations of the ring oscillator is counted by the Freq. Counter 10 in the period of the designated cycle (frequency measurement step). Here, assuming that the cycle of Ref CK11 is W and the designated number of cycles is M, how many times the ring oscillator oscillates in the period of W × M is Fr.
It is counted by eq. Counter 10. Then, the count value is recorded as Ca. Similarly, Base Delay6
And the state of AdjustableDelay7 is set to Tb46 and a count is measured. Then, the count value is recorded as Cb.

Next, the duty ratio is calculated (S2
2). That is, with Base Delay 6 when Ta45 and Tb46
The delay amount of Adjustable Delay 7 is calculated by Equation 1. As a result, the delay amount Da for Ca and the delay amount Db for Cb are obtained, and the difference Δt 47 is calculated as Db−Da. From Δt 47, the duty ratio, which is the ratio of the time from the rising edge to the falling edge and the time from the falling edge to the rising edge shown in FIG. 19, is obtained (duty ratio calculation step). When a change occurs in the center of Tcycle in FIG. 19, the ratio of Tr-f49 from the rising edge to the falling edge and Tf-r50 from the falling edge to the rising edge are the same, and the duty ratio at this time is It will be 50%. That is, this is the case when Δt 47 is 0.

Further, Tr-f49 when Δt 47 is not 0
And Tf-r50 can be calculated by the following equations 3 and 4.

Tr-f = (Tcycle / 2)-(Δt / 2) ... Equation 3 Tf-r = (Tcycle / 2) + (Δt / 2) ... Equation 4 If Δt 47 is not zero, The duty ratio is Tr-f: Tf-r, which is the ratio of the calculation results of Expression 3 and Expression 4.

[0075]

According to the present invention, the following effects can be obtained.

(1) In a test circuit for performing a jitter test of an oscillation circuit incorporated in a semiconductor integrated circuit, an output signal of the oscillation circuit delayed by one cycle or a half cycle by a delay circuit included in the semiconductor integrated circuit , The current output signal of the oscillation circuit and at least one of the rising edge and the falling edge of the two signals are detected a plurality of times to measure the jitter of one cycle or half cycle in the output signal of the oscillation circuit. Since only the output signal of the circuit is used, the reference signal to be compared is not required,
Not only the PLL circuit but also all oscillator circuits can be applied, and the jitter immediately after the output of the oscillator circuit can be measured accurately. Also, the jitter can be measured only by a relatively inexpensive logic tester.

(2) The test circuit for performing the jitter test of the oscillation circuit is provided with the first delay circuit block, the second delay circuit block, and the number of times counter, and is provided from the outside of the semiconductor integrated circuit. A first delay circuit block that can adjust a delay value and delays an output signal of the oscillation circuit by one cycle or a half cycle, and a second delay circuit block that can adjust a delay amount by a predetermined amount from outside the semiconductor integrated circuit. The delay circuit block compares the signal arrival times of the output signal of the oscillation circuit delayed by one cycle or a half cycle and the current output signal of the oscillation circuit a plurality of times,
By counting the number of times that the current output signal of the oscillation circuit arrives first with the frequency counter, only the output signal of the oscillation circuit is used, so that the reference signal to be compared is not required. Not limited to this, it can be applied to all oscillation circuits, and the jitter immediately after the output of the oscillation circuit can be accurately measured.

(3) The test circuit for performing the jitter test of the oscillation circuit is composed of the first delay circuit block and the second delay circuit block.
Since the ring oscillator including the delay circuit block and the frequency counter for measuring the frequency when the ring oscillator is oscillated are provided, the LSI
Accurate jitter measurement is possible without being affected by manufacturing process variations, temperature, and power supply voltage.

(4) Since the test circuit for performing the jitter test of the oscillation circuit is provided with the inverter element which can be connected and disconnected immediately after the output terminal of the oscillation circuit, the test signal from the falling edge of the output signal of the oscillation circuit It becomes possible to measure the time to the rising edge, and the duty ratio test of the oscillation circuit can be performed.

(5) Since the test circuit for performing the jitter test of the oscillation circuit has a switching counter capable of switching the function of the frequency counter and the function of the frequency counter instead of the frequency counter and the frequency counter, The scale can be reduced, and the product cost can be reduced.

(6) In the test circuit for performing the duty ratio test of the oscillation circuit incorporated in the semiconductor integrated circuit,
A first average time for measuring the average time from the rising edge to the falling edge of the output signal of the oscillation circuit, and a second average time for measuring the average time from the rising edge to the falling edge of the output signal of the oscillation circuit. , The duty ratio is calculated from the difference. For the first average time, the inverter element connected so that it can be contacted and separated is disconnected, and the current output signal of the oscillation circuit and the first delay circuit block and the second delay circuit capable of adjusting the output signal of the oscillation circuit are adjusted. The signal arrival time of the signal delayed by a half cycle by the circuit block and the signal arrival times of the two signals are compared multiple times while increasing the delay amount for a half cycle by a predetermined amount, and the current oscillation circuit output signal arrives first. The number of times is counted by the number counter, the signal delayed by a half cycle by the first delay circuit block and the second delay circuit block is oscillated by the ring oscillator to measure the frequency, and the measured frequency is used. The average time from the rising edge to the falling edge of the output signal of the oscillation circuit is measured and obtained. In the second averaging time, the inverter element connected so that it can be contacted and separated is connected, the output signal of the oscillation circuit is inverted, and the current output signal of the oscillation circuit and the output signal of the oscillation circuit can be adjusted. A signal delayed by a half cycle by the delay circuit block and a signal arrival time of the two signals are compared a plurality of times while increasing the delay amount for the half cycle by a predetermined amount.
The number of times that the current oscillation circuit output signal arrives first is counted by the frequency counter, and the signal delayed by a half cycle by the first delay circuit block and the second delay circuit block is oscillated by the ring oscillator to measure the frequency. , The average time from the rising edge to the falling edge of the output signal of the oscillation circuit is measured and obtained using the measured frequency. Therefore, an accurate duty ratio can be measured without being affected by variations in LSI manufacturing process and temperature by the power supply voltage.

(7) A signal delayed by one cycle or a half cycle by the delay circuit block capable of adjusting the delay value of the output signal of the oscillation circuit incorporated in the semiconductor integrated circuit, and the current output signal of the oscillation circuit. , The signal arrival times of the two signals are compared a plurality of times while increasing the delay amount for one cycle or a half cycle by a predetermined amount, and counting the number of times the current oscillation circuit output signal first arrives, Since the minimum period width and the maximum period width of the output signal of the oscillation circuit are obtained, only the output signal of the oscillation circuit is used.Therefore, the reference signal to be compared is not required. The jitter immediately after the output of the oscillation circuit can be accurately measured.

(8) The frequency oscillated by the ring oscillator is measured, and the frequency at which the output signal with the minimum period width and the output signal with the maximum period width in the oscillation circuit are oscillated by the ring oscillator is measured to obtain one period. Alternatively, since half-cycle jitter is obtained, accurate jitter measurement can be performed without being affected by variations in the LSI manufacturing process, temperature, and power supply voltage.

(9) Signal arrival of two signals, that is, a current output signal of the oscillation circuit incorporated in the semiconductor integrated circuit and a signal obtained by delaying the output signal of the oscillation circuit by a half cycle by an adjustable delay circuit block A counting step of comparing the times a plurality of times while increasing the delay amount for a half cycle by a predetermined amount and counting the number of times that the current oscillation circuit output signal reaches first, and a signal delayed by a half cycle by the delay circuit block. Frequency measurement step of oscillating a ring oscillator to measure the frequency, and first average time measurement for measuring the average time from the rising edge to the falling edge of the output signal of the oscillation circuit using the frequency measured in the frequency measurement step. Using the frequency measured by performing the counting process, frequency measuring process and averaging time measuring process by inverting the output signal of the oscillation circuit A second average time measuring step for measuring an average time from the falling edge to the rising edge of the output signal of the oscillation circuit, and two average times measured in the first average time measuring step and the second average time measuring step. The duty ratio calculation process for calculating the duty ratio from the difference between the duty ratio test and the duty ratio test of the oscillation circuit incorporated in the semiconductor integrated circuit is performed, so that variations in the LSI manufacturing process and temperature are not affected by the power supply voltage. Accurate duty ratio measurement can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a test circuit of an oscillator circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an output cycle of an Oscillator.

FIG. 3 is a waveform diagram showing the concept of periodic jitter.

FIG. 4 is a flowchart for explaining a jitter measuring method.

FIG. 5 is a time chart diagram of an input signal of a D flip-flop.

FIG. 6 is a time chart diagram in which a changed portion of an input signal of a D flip-flop is enlarged.

FIG. 7 is a graph showing the relationship between the delay value and the count value of the Meas Counter.

FIG. 8 is a circuit diagram showing a configuration for testing a PLL circuit with a test circuit for an oscillator circuit according to an embodiment of the present invention.

FIG. 9 is a configuration diagram of a modified example of the counter in the test circuit of the oscillation circuit according to the embodiment of the present invention.

FIG. 10 is a waveform diagram showing a rising edge to a falling edge of the output of the oscillation circuit.

FIG. 11 is a diagram showing a concept of a half-period Period Jitter.

FIG. 12 is a second time chart diagram of an input signal of a D flip-flop.

FIG. 13 is a second time chart diagram in which a changed portion of the input signal of the D flip-flop is enlarged.

FIG. 14 is a second graph showing the relationship between the delay value and the count value of the Meas Counter.

FIG. 15 is a waveform diagram showing a falling edge to a rising edge of the output of the oscillation circuit.

FIG. 16 is a configuration diagram in which an inverter element is added to the test circuit according to the embodiment of the present invention.

FIG. 17 is a flow chart diagram for explaining a method for obtaining the duty ratio of the oscillation circuit using the test circuit of the present invention.

FIG. 18 is a third graph showing the relationship between the delay value and the count value of the Meas Counter.

FIG. 19 is a waveform diagram showing the duty ratio of the oscillation circuit.

FIG. 20 is a block diagram showing a circuit configuration of a conventional technique.

[Explanation of symbols]

1-Oscillator 4-selector 5-Jitter / OSC select signal 6-Base Delay (basic delay circuit) 7-Adjustable Delay 8-D flip-flop 9-Meas Counter 10-Freq. Counter (frequency counter) 11-Ref CK (reference signal) 23-PLL circuit 26-VCO (Voltage controlled oscillator) 61-test circuit

Claims (9)

[Claims] 1. A test circuit for performing a jitter test of an oscillation circuit incorporated in a semiconductor integrated circuit, comprising one cycle or a half cycle depending on a current output signal of the oscillation circuit and a delay circuit included in the semiconductor integrated circuit. At least one of the rising edge and the falling edge of the two signals delayed by the amount and the output signal of the oscillation circuit is detected a plurality of times to measure the jitter of one cycle or half cycle in the output signal of the oscillation circuit. A test circuit characterized in that 2. A first delay circuit block capable of adjusting a delay value from the outside of the semiconductor integrated circuit and delaying an output signal of the oscillation circuit by one cycle or a half cycle, and outside the semiconductor integrated circuit. A second delay circuit block whose delay amount can be adjusted by a predetermined amount, and an output of the oscillation circuit delayed by one cycle or half cycle by the first delay circuit block and the second delay circuit block. A signal counter and a current output signal of the oscillation circuit are compared with each other a plurality of times, and a number counter for counting the number of times the current output signal of the oscillation circuit has reached first is provided. The test circuit according to claim 1. 3. A ring oscillator comprising the first delay circuit block and the second delay circuit block, and a frequency counter for measuring a frequency when the ring oscillator is oscillated. Claim 2 characterized by
Test circuit described in. 4. The test circuit according to claim 2, wherein an inverter element that can be connected and disconnected is provided immediately after the output terminal of the oscillator circuit. 5. The test according to claim 3, further comprising a switching counter capable of switching the function of the frequency counter and the function of the frequency counter, instead of the frequency counter and the frequency counter. circuit. 6. A test circuit for performing a duty ratio test of an oscillation circuit incorporated in a semiconductor integrated circuit, comprising: a first delay circuit block for delaying an output signal of the oscillation circuit by a half cycle; A second delay circuit block whose delay amount can be adjusted by a predetermined amount from the outside, a signal delayed by a half cycle by the first delay circuit block and the second delay circuit block, and a current oscillation circuit output signal And a second delay circuit block, which compares the signal arrival times of the two signals a plurality of times, and counts the number of times that the current output signal of the oscillation circuit first arrives, the first delay circuit block, and the second delay circuit. A ring oscillator including a circuit block, a frequency counter for measuring a frequency when the ring oscillator is oscillated, and the oscillation An inverter element connected to and detachable from the output terminal of the circuit immediately after the output terminal of the circuit, the inverter element is separated, and a current output signal of the oscillation circuit and a delay capable of adjusting the output signal of the oscillation circuit are provided. The signal arrival times of the two signals delayed by a half cycle by the circuit block and the signal arrival times of the two signals are compared multiple times while increasing the delay amount for half a cycle by a predetermined amount, and the current oscillation circuit output signal arrives first. Count the number of times with the number of times counter,
A signal delayed by a half cycle by the first delay circuit block and the second delay circuit block is oscillated by the ring oscillator to measure the frequency, and the rising edge of the output signal of the oscillation circuit is measured using the measured frequency. The first time to measure the average time from the edge to the falling edge
The average time, the inverter element is connected, the output signal of the oscillation circuit is inverted, and the current output signal of the oscillation circuit and the output signal of the oscillation circuit are adjusted by a half-cycle delay The signal arrival times of the two signals of the generated signal and the delayed signal are compared a plurality of times while increasing the delay amount for a half cycle by a predetermined amount, and the number of times that the current oscillation circuit output signal first arrives is counted by the frequency counter. A signal counted by the first delay circuit block and delayed by the second delay circuit block by half a cycle is oscillated by the ring oscillator to measure the frequency, and the output signal of the oscillation circuit is measured using the measured frequency. A test circuit characterized in that the duty ratio can be calculated from the difference between the average time from the rising edge to the falling edge and the second average time measured. . 7. A test method for performing a jitter test of an oscillation circuit incorporated in a semiconductor integrated circuit, comprising: a delay circuit block capable of adjusting a delay value of an output signal of the oscillation circuit; The signal arrival times of the delayed signal and the current oscillation circuit output signal are compared a plurality of times while increasing the delay amount for one cycle or a half cycle by a predetermined amount, and the current oscillation circuit is compared. A test method, wherein the number of times the output signal first arrives is counted to obtain the minimum period width and the maximum period width of the output signal of the oscillation circuit. 8. The jitter of one cycle or half cycle is obtained by measuring the frequency at which the output signal of the minimum cycle width and the output signal of the maximum cycle width in the oscillation circuit are oscillated by a ring oscillator. The test method according to claim 7. 9. A test method for performing a duty ratio test of an oscillator circuit incorporated in a semiconductor integrated circuit, comprising: a current output signal of the oscillator circuit; and a delay circuit block capable of adjusting the output signal of the oscillator circuit. A signal delayed by a half cycle and the signal arrival times of the two signals are compared a plurality of times while increasing the delay amount for the half cycle by a predetermined amount.
In the counting step of counting the number of times the current oscillation circuit output signal reaches first, the frequency measurement step of oscillating the signal delayed by a half cycle by the delay circuit block by the ring oscillator to measure the frequency, and the frequency measurement step. A first averaging time measuring step of measuring an average time from a rising edge to a falling edge of an output signal of the oscillation circuit using the measured frequency; and a counting step of inverting the output signal of the oscillation circuit, the frequency A second step of measuring the average time from the falling edge to the rising edge of the output signal of the oscillation circuit by using the frequency measured by performing the measuring step and the averaging time measuring step.
A test comprising an average time measuring step and a duty ratio calculating step of calculating a duty ratio from a difference between two average times measured in the first average time measuring step and the second average time measuring step. Method.